Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 05/30/2024.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/30/2024 and 09/04/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
Figures 1 and 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Objections
Claims 1, 4, 5, 6, 7, 11, 18, 19, and 20 are objected to because of the following informalities: Regarding claim 1, in line 8, “a first fixed time period” appears that it should read as “a fixed first time period”. Regarding claim 4, in line 1, “the DC current” appears that it should read as “the first DC current”. Regarding claim 5, in line 1, “the DC current” appears that it should read as “the first DC current”;in line 2, “the absolute value of the temperature” appears that it should read as “an absolute value of temperature”. Regarding claim 6, in line 1, “the regulator” appears that it should read as “the voltage regulator”. Regarding claim 7, in line 1, “the regulator” appears that it should read as “the voltage regulator”. Regarding claim 11, in line 11, “the end” appears that it should read as “an end”. Regarding claim 18, in line 3, “the regulator” appears that it should read as “the voltage regulator”. Regarding claim 19, in lines 1-2, “a capacitive element” appears that it should read as “the capacitive element”;in line 3, “the regulator” appears that it should read as “the voltage regulator”. Regarding claim 20, in line 4, “an inductive element” appears that it should read as “the inductive element”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 18, and 19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liu et al. (US 2014/0021930 A1, hereinafter “Liu”). Regarding claim 1, Liu discloses (see Fig. 2, Fig. 3, Fig. 5, and Fig. 6) a voltage regulator (see Fig. 5), comprising: a first output (output 550) intended to be connected to a capacitive element (536); a current source (comprising 574 and 576) coupled between the first output and a first node (node of 574) configured to receive a power supply voltage (Vg’), the current source being configured to deliver a first DC current (ILR) to the first output only in response to assertion of a first binary signal (EN1); a comparator (578) configured to deliver a second binary signal (output of 578) that is in an asserted state when a first voltage on the first output (Vout) is lower than a set point voltage (VR’); and a first circuit (see circuit of Fig. 6) configured to assert the first binary signal for a first fixed time period (see D1 of Fig. 3) when the second binary signal is in the asserted state (see Fig. 3, where EN1 is asserted for fixed time period D1 when Vout falls below VR’).
Regarding claim 2, Liu discloses (see Fig. 2, Fig. 3, Fig. 5, and Fig. 6) wherein the first time period is fixed and independent from the power supply voltage (D1 is fixed and independent from Vg’, see [0052] “an internal signal EN1 350 can be generated to indicate a beginning and ending of the load transient period D1 368.”).
Regarding claim 18, Liu discloses (see Fig. 2, Fig. 3, Fig. 5, and Fig. 6) a device (see device 200 of Fig. 2), comprising: the voltage regulator according to claim 1 (see above claim 1 rejection); and a load (see [0029] “A linear regulator can provide source current to an output load when the regulator detects an undershot voltage.”) connected to the first output of the regulator.
Regarding claim 19, Liu discloses (see Fig. 2, Fig. 3, Fig. 5, and Fig. 6) wherein the device further comprises a capacitive element (Cout) connected to the first output of the regulator.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Raghavan et al. (US Patent Application Publication US 2019/0033907 A1, hereinafter “Raghavan”). Regarding claim 4, Liu does not disclose wherein the DC current has a fixed value independent from temperature. However, Raghavan teaches (see Fig. 1B and Fig. 2D) a DC current source (100B) wherein the DC current (IB) has a fixed value independent from temperature (see 210A of Fig. 2D). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulator of Liu wherein the DC current has a fixed value independent from temperature, as taught by Raghavan, because it can help provide accurate DC current regardless of temperature changes.
Regarding claim 5, Liu does not disclose wherein the DC current has a value proportional to the absolute value of the temperature. However, Raghavan teaches (see Fig. 1B and Fig. 2D) a DC current source (100B) wherein the DC current (IB) has a value proportional to the absolute value of the temperature (see i.e. 210B of Fig. 2D). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage regulator of Liu wherein the DC current has a value proportional to the absolute value of the temperature, as taught by Raghavan, because it can help provide accurate DC current according to temperature changes.
Allowable Subject Matter
Claims 3, 6-17, 20, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 3, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the first time period is determined by the power supply voltage.”. Regarding Claim 6, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the regulator further comprises an inrush current regulation circuit configured, in an inrush current regulation phase, to periodically force the second binary signal to a nonasserted state for a second fixed time period.”. Regarding Claim 7, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the regulator comprises a measurement circuit configured to supply, at an end of each measurement period, a number of first time periods having begun during said measurement period.”. Regarding Claim 8, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the first time period and the current source are configured so that a quantity of charges supplied to the first output during each first time period is set dependent on a given temperature value and power supply voltage value.”. Regarding Claim 9, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “each first time period being determined based on at least one of the first and second control signals.”. Claim 10 is objected due to its dependency on claim 9. Regarding Claim 11, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the first circuit is further configured, in a first operating mode, to control an on state of the first switch when the first control signal is in the asserted state and control an on state of the second switch when the second control signal is in the asserted state, and, in a second operating mode, to set the first binary signal to the asserted state in response to either assertion of the first binary signal or the second control signal being in the asserted state.”. Claims 12-17, 20, and 21 are objected due to their dependency on claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Patent Application Publication 2016/0357205 A1 discloses a method of recovering a voltage drop at an output terminal of a voltage regulator. US Patent Application Publication 2002/0175747 A1 discloses a method for open loop enhanced control of power supply transients. US Patent Application Publication 2002/0135339 A1 discloses a dual loop regulator. US Patent Application Publication 2002/0046354 A1 discloses a system for providing transient suppression in power regulators. US Patent Application Publication 2007/0075692 A1 discloses a current controlled transient regulation method for voltage regulators. US Patent 9,122,292 B2 discloses an LDO/HDO circuit adding a supplementary current source to supply the output node. US Patent 9,257,905 B1 discloses an efficient power supply with fast transient response.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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/JYE-JUNE LEE/Examiner, Art Unit 2838
/MONICA LEWIS/Supervisory Patent Examiner, Art Unit 2838