DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment is made of applicant’s amendment, filed on 14 September 2026. The changes and remarks disclosed therein have been considered.
Claims 1-20 are pending in the application. Claims 1, 6, 8-9, 13, 18 and 20 are currently amended. Claims 1, 9 and 13 are independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
►Claims 1-7 and 9-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2025/0015161) (hereinafter, “Chang”) in view of Wang et al. (US 2024/0096992) (hereinafter, “Wang”).
Re: independent claim 1, Chang discloses in fig. 1 a semiconductor device, comprising: an active region (120) formed in a substrate (100); a gate dielectric layer (230) located on the active region and having an extension area (230a) on opposite sides of the gate dielectric layer respectively; a gate electrode (210) located on the gate dielectric layer and exposing the two extension areas; and source/drain regions (F) located in the active region on opposite sides of the gate dielectric layer, wherein the source/drain regions comprise two heavily doped regions (140), respectively.
Chang does not disclose wherein one of the heavily doped regions extends from an outer lateral side of a corresponding one of the extension areas away from the gate dielectric layer, and an inner lateral side of one of the heavily doped regions is aligned with the outer lateral side of the corresponding one of the extension areas.
Wang discloses in fig. 3D source/drain regions (202, 207) located in an active region (203) on opposite sides of a gate dielectric layer (204), wherein the source/drain regions comprise two heavily doped regions (207), respectively, one of the heavily doped regions (207) extends from an outer lateral side of a corresponding one of an extension areas away from the gate dielectric layer (204), and an inner lateral side of one of the heavily doped regions (207) is aligned with the outer lateral side of the corresponding one of the extension areas (Para. [0130] discloses performing a source drain injection on surfaces of the lightly doped drain regions 202. Therefore, the source drain implantation regions 207 are interpreted as having a dopant concentration greater than that of the lightly doped drain regions 202, i.e. regions 207 are heavily doped.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dispose a heavily doped region extending from an outer lateral side of a corresponding one of an extension area of the gate dielectric layer and aligning an inner lateral side of the heavily doped region with an outer lateral side of the extension area of the gate dielectric layer for the purpose of reducing a leakage current as exemplified by Wang [0102].
Re: claim 2, Chang in view of Wang discloses in fig. 1 of Chang the semiconductor device of claim 1, wherein the active region comprises a channel region (CH), a drain extension region (F) and a source extension region (F), and the channel region (CH) is located between the drain extension region (F) and the source extension region (F).
Re: claim 3, Chang in view of Wang discloses in fig. 1 of Chang the semiconductor device of claim 2, wherein an overlapping area of the gate dielectric layer (230) with the channel region (CH), the drain extension region (F), and the source extension region (F) is greater than an overlapping area of the gate electrode layer (210) with the channel region (CH), the drain extension region (F), and the source extension region (F).
Re: claim 4, Chang in view of Wang discloses in fig. 1 of Chang the semiconductor device of claim 3, wherein a distance between an edge of the gate dielectric layer (230) and an edge of the gate electrode (210) is a length of each of the extension areas (F).
Re: claim 5, Chang in view of Wang discloses in fig. 1 of Chang the semiconductor device of claim 4, wherein the length of each of the extension areas (F) is a length of the overlapping area of the gate dielectric layer (230) and the drain extension region (F) minus a length of the overlapping area of the gate electrode (210) and the drain extension region (F).
Re: claim 6, Chang in view of Wang discloses the semiconductor device of claim 4, wherein the edge of the gate dielectric layer (Chang: 230; Wang: 204) is flush with an edge of one of the source/drain region (Chang: 250; Wang: 207).
Re: claim 7, Chang in view of Wang discloses in fig. 1 of Chang the semiconductor device of claim 1, further comprising a gate spacer (220) covering sidewalls of the gate electrode (210).
Re: independent claim 9, Chang discloses in fig. 1 a semiconductor device, comprising: a drain extension region (F) formed in a substrate (100); a gate dielectric layer (230) located on the drain extension region (F), the gate dielectric layer (230) has an extension area (230a) on one side, and the extension area (230a) overlaps the drain extension region (F); a gate electrode (210) located on the gate dielectric layer (230) and exposing the extension area (230a); and a drain region (250) located in the substrate (100) on the side of the gate dielectric layer (230), wherein the drain region comprises a heavily doped region (140).
Chang does not disclose wherein the heavily doped region extends from an outer lateral side of the extension area away from the gate dielectric layer, and an inner lateral side of the heavily doped region is aligned with the outer lateral side of the extension area.
Wang discloses in fig. 3D a heavily doped region (207) extending from an outer lateral side of an extension area away from a gate dielectric layer (204), and an inner lateral side of the heavily doped region (207) is aligned with the outer lateral side of the extension area (Para. [0130] discloses performing a source drain injection on surfaces of the lightly doped drain regions 202. Therefore, the source drain implantation regions 207 are interpreted as having a dopant concentration greater than that of the lightly doped drain regions 202, i.e. regions 207 are heavily doped.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dispose a heavily doped region extending from an outer lateral side of an extension area of the gate dielectric layer and aligning an inner lateral side of the heavily doped region with an outer lateral side of the extension area of the gate dielectric layer for the purpose of reducing a leakage current as exemplified by Wang [0102].
Re: claim 10, Chang in view of Wang discloses in fig. 1 of Chang the semiconductor device of claim 9, wherein an overlapping area of the gate dielectric layer (230) and the drain extension region (F) is greater than an overlapping area of the gate electrode layer (210) and the drain extension region (F).
Re: claim 11, Chang in view of Wang discloses in fig. 1 of Chang the semiconductor device of claim 10, wherein a distance between an edge of the gate dielectric layer (230) and an edge of the gate electrode (210) is a length of the extension area (230a).
Re: claim 12, Chang in view of Wang discloses the semiconductor device of claim 11, wherein the edge of the gate dielectric layer (Chang: 230; Wang: 204) is flush with an edge of the drain region (Chang: 250; Wang: 207).
Re: independent claim 13, Chang discloses in fig. 1 a method of manufacturing a semiconductor device, comprising: forming an active region (120) in a substrate (100); depositing a gate dielectric layer (230) on the active region, the gate dielectric layer (230) having an extension area (230a) on opposite sides of the gate dielectric layer respectively; forming a gate electrode (210) on the gate dielectric layer (230) and exposing the two extension areas (230a) from the gate electrode (210); and performing an ion implantation [0040] by using the gate dielectric layer (230) as a mask to form source/drain regions (250) located in the active region on opposite sides of the gate dielectric layer (230).
Chang does not disclose wherein the source/drain regions comprise two heavily doped regions, respectively, one of the heavily doped regions extends from an outer lateral side of a corresponding one of the extension areas away from the gate dielectric layer, and an inner lateral side of one of the heavily doped regions is aligned with the outer lateral side of the corresponding one of the extension areas.
Wang discloses in fig. 3D source/drain regions comprising two heavily doped regions (207), respectively, one of the heavily doped regions (207) extends from an outer lateral side of a corresponding one of an extension area away from a gate dielectric layer (204), and an inner lateral side of one of the heavily doped regions (207) is aligned with the outer lateral side of the corresponding one of the extension areas (Para. [0130] discloses performing a source drain injection on surfaces of the lightly doped drain regions 202. Therefore, the source drain implantation regions 207 are interpreted as having a dopant concentration greater than that of the lightly doped drain regions 202, i.e. regions 207 are heavily doped.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dispose a heavily doped region extending from an outer lateral side of an extension area of the gate dielectric layer and aligning an inner lateral side of the heavily doped region with an outer lateral side of the extension area of the gate dielectric layer for the purpose of reducing a leakage current as exemplified by Wang [0102].
Re: claim 14, Chang in view of Wang discloses in fig. 1 of Chang the method of claim 13, wherein the active region (120) comprises a channel region (CH), a drain extension region (F) and a source extension region (F), and the channel region (CH) is located between the drain extension region (F) and the source extension region (F).
Re: claim 15, Chang in view of Wang discloses in fig. 1 of Chang the method of claim 14, wherein an overlapping area of the gate dielectric layer (230) with the channel region (CH), the drain extension region (F), and the source extension region (F) is greater than an overlapping area of the gate electrode layer (210) with the channel region (CH), the drain extension region (F), and the source extension region (F).
Re: claim 16, Chang in view of Wang discloses in fig. 1 of Chang the method of claim 15, wherein a distance between an edge of the gate dielectric layer (230) and an edge of the gate electrode (210) is a length of each of the extension areas (250).
Re: claim 17, Chang in view of Wang discloses in fig. 1 of Chang the method of claim 16, wherein the length of each of the extension areas (230a) is a length of the overlapping area of the gate dielectric layer (230) and the drain extension region (F) minus a length of the overlapping area of the gate electrode (210) and the drain extension region (F).
Re: claim 18, Chang in view of Wang discloses the method of claim 16, wherein the edge of the gate dielectric layer (Chang: 230; Wang: 204) is flush with an edge of one of the source/drain regions (Chang: 250; Wang: 207).
Re: claim 19, Chang in view of Wang discloses in fig. 1 of Chang the method of claim 13, further comprising forming a gate spacer (220) covering sidewalls of the gate electrode (210).
►Claims 8 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2025/0015161) (hereinafter, “Chang”) in view of Wang et al. (US 2024/0096992) (hereinafter, “Wang”) as applied to claims 1 and 13, respectively, in further view of Li et al. (US 2018/0012890) (hereinafter, Li).
Re: claims 8 and 20, Chang in view of Wang discloses the semiconductor device of claim 1 and the method of claim 13.
Chang in view of Wang does not expressly disclose forming at least one interlayer dielectric layer and at least one conductive plug formed in the interlayer dielectric layer, wherein the interlayer dielectric layer covers the active region, and the conductive plug is electrically connected to the source/drain region.
Li discloses in fig. 10 forming at least one interlayer dielectric layer (326) and at least one conductive plug (328) formed in the interlayer dielectric layer, wherein the interlayer dielectric layer (326) covers an active region (306), and the conductive plug (328) is electrically connected to a source/drain region (318).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form an interlayer dielectric layer and conductive plug as claimed for the purpose of insulating the device from other components in an integrated circuit and to facilitate connection of the device (Li, [0074]).
Response to Arguments
Applicant’s arguments with respect to claims 1, 9 and 13 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 9/28/2026
