Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated September 10, 2026, claims 1-20 are active in
this application.
Claim Objections
Claims 4, 5 and 16 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Haukness [US Patent Application #20160019962].
With respect to claim 17, Haukness discloses a method [pars. 0015-0016] comprising: accessing
a memory cell during a write operation [Haukness teaches an RRAM memory cell having an access transistor. The access transistor selectively allows voltage to be applied and current to be passed through the RRAM memory so that its state can be changed (i.e., written to). This shows accessing the memory cell during a write operation.], wherein the accessing comprises selecting a voltage based on a polarity [Haukness discloses applying opposite polarities to SET and RESET the RRAM memory. To perform either write action, the operating circuit must apply either a positive or negative voltage across the cell. Thus, accessing the cell inherently comprises selecting the operating voltage configuration based on the target polarity required for the write operation.]; and after accessing the memory cell, limiting a current through the memory cell [Haukness states that the access transistor "selectively allows current to be passed through, and voltage applied to, the rram memory." By selectively allowing current and controlling the transistor's gate/conduction path, the access transistor inherently serves to limit or meter the current passing through the RRAM memory cell during/after the state-changing access to prevent damage (compliance current limitation) or to isolate the cell after writing. Also, see steps 502 and 504 of fig. 6].
With respect to claim 18, Haukness disclose that the polarity is a program polarity. See par. 0015. It is noted that since both SET and RESET are actions that write or modify the binary data stored within the cell, the distinct electrical polarities required to achieve these transitions are directly referred to as the programming polarities.
With respect to claim 19, Haukness disclose accessing the memory cell comprises applying the voltage to a wordline. See par. 0015.
With respect to claim 20, Haukness discloses sensing the current [read current – see par. 0025].
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for
all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was
made.
Claims 1 and 6 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Tortorelli et al.
[U.S. Patent Application # 20190189206] in view of 김환 [KR 102988122 B1 (‘122)].
Tortorelli et al. disclose a device comprising: a wordline decoder [120] configured to apply a voltage to a wordline [110]; and a controller [140] configured to select the program polarity. Tortorelli et al. establishes the foundational architecture of the device: a memory controller and a row (wordline) decoder operating a memory cell array. The Tortorelli et al. reference teaches that the controller determines the shape and polarity of programming pulses applied to a self-selecting memory cell based on a desired logic state. Additionally, Tortorelli et al. details using a polarity for its programming pulse. See par. 0031.
Tortorelli et al. discloses all the above mentioned but is silent about the fact that the polarity of the voltage is selectable based on a program polarity. Reference ‘122 bridges the gap regarding selectable polarity. It explicitly teaches a memory operation (specifically for a "self-selective memory cell array," matching Tortorelli et al.'s cell type) where the write/read circuit switches voltage polarities. It applies a read pulse having the opposite polarity to the write (programming) pulse. See 5th paragraph of the ”In Article 8” section.
Both Tortorelli et al. and reference ‘122 operate in the exact same technical field:
managing self-selecting / self-selective memory cells. Merging reference ‘122’s bi-polar operational scheme (opposite polarities for read/write) into Tortorelli et al.’s controller-driven architecture yields the predictable result of a memory device capable of switching voltage polarities based on the operational mode. A person of ordinary skill in the art designing a self-selecting memory device would look to methods of reading and writing to those specific cells. Since Tortorelli et al. already dictates that the controller shapes the pulse based on the desired logic state, implementing reference ‘122's technique yields the entirely predictable result of a memory device capable of bi-directional voltage signaling to optimize self-selecting memory cell readout.
With respect to claim 6, Tortorelli et al. disclose the wordline is used to sense a current
to determine a logic state of a memory cell “a memory cell 105 may be read, or sensed, by sense component 125 to determine the stored state of the memory cell 105. For example, a voltage may be applied to a memory cell 105 (using the corresponding word line 110 and bit line 115) and the presence of a resulting current may depend on the applied voltage and the threshold voltage of the memory cell 105.” – par. 0026.
Claims 2 and 3 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Tortorelli et al.
[U.S. Patent Application # 20190189206] in view of 김환 [KR 102988122 B1 (‘122)] and further in view of Shen et al. [CN 102024498 A].
Tortorelli et al. teaches the foundational device structure, including a memory controller (140) and a row/wordline decoder (120) configured to apply voltages to a wordline (110) to control self-selecting memory cells based on desired logic states. See par. 0031.
Reference ‘122 teaches that in self-selective memory arrays, circuits must apply pulses of
opposite polarities to the target memory cell depending on the operation mode (write vs. read) to optimize cell performance. See 5th paragraph of the ”In Article 8” section.
Shen et al. teaches a decoder configuration where a wordline selecting signal (signal XB)
dynamically switches polarities—applying a negative voltage (a second polarity) under a first mode (erasing) and a positive voltage (a first polarity) under a second mode (reading/programming). See par. 0069.
It would have been obvious to a person of ordinary skill in the art at the time the invention to incorporate the multi-polarity decoder system of Shen et al. into the memory architecture of Tortorelli et al. and reference ‘122 since there is a regular need to manipulate memory cells (like erasing, writing, and reading) using bi-direction voltage potentials. A person of ordinary skill in the art would look to Shen et al.’s teaching of utilizing positive and negative decoder signals (signal XB) to alternative the polarity applied to a selected wordline depending on the operational program mode. Doing so achieves predictable results: it enables the controller and decoder of Tortorelli et al. to execute the opposite-polarity write/read operations required by reference ‘122, and satisfies the claimed limitation of applying a second polarity voltage in a first mode and a first polarity voltage in a second mode.
With respect to claim 3, Shen et al. discloses the first and second program polarities are
opposite. See par. 0069.
Claims 7 and 8 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Tortorelli et al.
[U.S. Patent Application # 20190189206] in view of 김환 [KR 102988122 B1 (‘122)] and Castro [US Patent # 11,164,635].
The combination of Tortorelli et al. and reference ‘122 disclose a wordline decoder that applies selectable voltage polarities based on program polarity settings [see claim 1’s rejection above], but fails to explicitly recite utilizing cell snapback behavior to advance cell state ( the memory cell snaps after being accessed using the wordline during a read or write operation). Castro teaches a memory pulse programming method wherein each signal pulse causes memory cells to advance toward a desired state by inducing a characteristic "snap back" event. See col. 2, lines 35-65. It would have been obvious to a person having ordinary skill in the art at the time of the invention to modify the controller and decoder setup of the combination of Tortorelli et al. and reference ‘122 to utilize the pulse-induced snapback operation taught by Castro. One would be motivated to do so to achieve deterministic state transition verification and to optimize power delivery timing across both selected voltage polarities. The combination relies on predictable, known memory control techniques to achieve an expected outcome.
With respect to claim 8, Castro discloses that a current through the memory cell is
limited after the memory cell snaps. See col. 14, lines 15-30. In the cited section, Castro indicated that a current-setting transistor (682) “may be used to control (e.g., limit) the current flow in word line 610…in response to signals (e.g. voltages) from a line…when the word line voltage is low…”
Claims 9, 10 and 12-15 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Tortorelli et al. [U.S. Patent Application # 20190189206] in view of 김환 [KR 102988122 B1 (‘122)].
Tortorelli et al. discloses an apparatus [100 with 105 and 140]] comprising: a first voltage supply [Tortorelli et al. discloses that the memory controller (140) may "generate and control various voltages or currents used during the operation of memory device 100." -par. 0031]; a second voltage supply [par. 0031]; and a controller [140 – Tortorelli et al. teaches a controller determining/applying a programming pulse based on a desired logic state as well as disclosing that the controller generating row/column address signals to activate a desired word line (110) or digit line (115) (access lines), and applying the voltage pulses to the memory cells through these lines.– par. 0031].
Tortorelli et al. discloses all the above but is silent about the controller being configured to: select a polarity; and select, based on the polarity, the first or second voltage supply for coupling to an access line. Reference ‘122 shows (5th paragraph of the ”In Article 8” section): 1) generating pulses of opposite polarities: a "write pulse" and a "read pulse having opposite polarity to a write pulse."; 2) the circuit determines whether to apply a write pulse or a read pulse having an opposite polarity; and 3) applying either the write pulse or the opposite-polarity read pulse to the target memory cell. To generate voltages/pulses of opposite polarities (e.g., positive and negative, or a positive voltage and ground/reference), an electrical circuit inherently requires at least two distinct voltage potentials or supply lines (e.g., a first voltage supply line and a second voltage supply line/ground). Additionally, the circuit must actively select a polarity depending on whether it is performing a write operation (first polarity) or a read operation (second, opposite polarity). Therefore, it would have been obvious to a person of ordinary skill in the art that to apply pulses of opposite polarities to the same access line (as taught by reference ‘122), the controller must select, based on the chosen polarity, which voltage supply/potential (the first or second) to couple to the access line. Additionally, it would have been obvious to a person of ordinary skill in the art at the time of the invention to modify the memory controller of Tortorelli et al. to incorporate the opposite-polarity read/write biasing scheme of reference ‘122 since it would optimize the operation of the “self-selecting memory cells” mentioned in both references. Tortorelli et al. establishes that the controller operates self-selecting memory cells using pulses based on threshold voltages. Reference ‘122 provides a specific, compatible driving method for self-selecting memory cells (using an opposite polarity read pulse relative to the write pulse) to reliably read data without inadvertently disturbing the written state. Implementing reference ‘122’s bi-polar operational method into Tortorelli et al. controller yields the predictable result of a controller routing the appropriate voltage supply line to the access line based on the desired operation polarity.
With respect to claim 10, Tortorelli et al. disclose that the polarity is a program polarity. See par. 0029.
With respect to claim 12, Tortorelli et al. disclose that the access line is a word line. See par. 0029.
With respect to claim 13, Tortorelli et al. disclose that a wordline decoder [row] coupled to the first and second voltage supplies. See par. 0023.
With respect to claim 14, Tortorelli et al. disclose the wordline decoder is configured to select a wordline for accessing a memory cell. See par. 0023.
With respect to claim 15, Tortorelli et al. disclose a digit line decoder [column] used to access the memory cell.
Claim 11 is rejected under 35 U.S.C. § 103(a) as being unpatentable over Tortorelli et al.
[U.S. Patent Application # 20190189206] in view of 김환 [KR 102988122 B1 (‘122)] and further in view of Shen et al. [CN 102024498 A].
Tortorelli et al. teaches the foundational device structure, including a memory controller (140) and a row/wordline decoder (120) configured to apply voltages [voltage supplies] to a wordline (110 – access line) to control self-selecting memory cells based on desired logic states. See par. 0031.
Reference ‘122 teaches that in self-selective memory arrays, circuits must apply pulses of
opposite polarities to the target memory cell depending on the operation mode (write vs. read) to optimize cell performance. See 5th paragraph of the ”In Article 8” section.
Shen et al. teaches a decoder configuration where a wordline selecting signal (signal XB)
dynamically switches polarities—applying a negative voltage (a second polarity) under a first mode (erasing) and a positive voltage (a first polarity) under a second mode (reading/programming). See par. 0069.
It would have been obvious to a person of ordinary skill in the art at the time the invention to incorporate the multi-polarity decoder system of Shen et al. into the memory architecture of Tortorelli et al. and reference ‘122 since there is a regular need to manipulate memory cells (like erasing, writing, and reading) using bi-direction voltage potentials. A person of ordinary skill in the art would look to Shen et al.’s teaching of utilizing positive and negative decoder signals (signal XB) to alternative the polarity applied to a selected wordline depending on the operational program mode. Doing so achieves predictable results: it enables the controller and decoder of Tortorelli et al. to execute the opposite-polarity write/read operations required by reference ‘122, and satisfies the claimed limitation of applying a second polarity voltage in a first mode and a first polarity voltage in a second mode.
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 4: The device of claim 1, wherein the voltage is applied to access a memory cell, current passes through first circuitry when operating in a first program polarity, and the current passes through second circuitry when operating in a second program polarity.
-with respect to claim 16, The apparatus of claim 14, further comprising a digit line decoder is coupled to the first and second voltage supplies.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 October 11, 2026
