DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 8-9, and 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dykstra et al. (US 2017/0133989).
In regard to Claim 1:
Dykstra discloses, in Figure 4E1, a circuit (100c), comprising:
a first transistor (115) having a first terminal coupled to a first power supply terminal (115 source coupled to ground), a second terminal (115 drain), and a control terminal coupled to an input terminal (115 gate connected to RFin);
a second transistor (155) having a first terminal coupled to the second terminal of the first transistor (155 source connected to 115 drain via 120 and 120s), a second terminal coupled to an output terminal (155 drain connected to RFout), and a bias terminal coupled to a bias terminal (155 gate connected to 195); and
a current injection circuit (120, 134, 140, 144, 175) having an input coupled to the input terminal (RFin coupled to 134, 140 via 115, 120, and 120a), a first output (175) coupled to the second terminal of the second transistor (155 drain), and a second output (134, 140) coupled to the first terminal of the second transistor (155 source).
In regard to Claim 2:
Dykstra discloses, in Figure 4E1, the circuit of claim 1, further comprising: a load device (170) having a first terminal coupled to the second terminal of the second transistor (170 connected to 155 drain), and a second terminal coupled to a second power supply terminal of the circuit (170 connected to Vdd).
In regard to Claim 8:
Dykstra discloses, in Figure 4E1, a cascode amplifier, comprising:
an amplifier transistor (115) having a first terminal coupled to a first power supply terminal (115 source coupled to ground), a second terminal (115 drain), and a control terminal coupled to an input terminal (115 gate connected to RFin);
a cascode transistor (155) having a first terminal coupled to the second terminal of the amplifier transistor (155 source connected to 115 drain via 120 and 120s), a second terminal coupled to an output terminal (155 drain connected to RFout), and a bias terminal coupled to a bias terminal (155 gate connected to 195); and
a current injection circuit (120, 134, 140, 144, 175) having an input receiving the input signal (RFin coupled to 134, 140 via 115, 120, and 120a), and first and second outputs coupled to the first (175 connected to 155 drain via 170) and second (134, 140 connected to 155 source via 120) current terminals of the cascode transistor (155), respectively, the current injection circuit (120, 134, 140, 144, 175) configured to present out-of-phase currents from its first (175) and second (134, 140) outputs responsive to the input signal (RFin).
In regard to Claim 9:
Dykstra discloses, in Figure 4E1, the cascode amplifier of claim 8, further comprising: a load device (170) having a first terminal coupled to the second terminal of the cascode transistor (170 connected to 155 drain), and a second terminal coupled to a second power supply terminal of the circuit (170 connected to Vdd).
In regard to Claim 16:
Dykstra discloses, in Figure 4E1, a method, comprising:
receiving an input signal (RFin) at an amplifier transistor (115) in a cascode amplifier (100c), the cascode amplifier further including a cascode transistor (155) coupled to the input transistor (115),
responsive to the input signal (RFin), generating out-of-phase injection currents from first (175) and second (134, 140) outputs of a current injection circuit (120, 134, 140, 144, 175);
applying the out-of-phase injection currents to first (175 connected to 155 drain via 170) and second (134, 140 connected to 155 source via 120) current terminals of the cascode transistor (155); and
generating an output signal (RFout) from an output of the cascode amplifier (100c) responsive to the input signal (RFin).
In regard to Claim 17:
Dykstra discloses, in Figure 4E1, the method of claim 16, wherein the receiving of an input signal (RFin) at an amplifier transistor (115) comprises:
receiving the input signal (Rfin) at a gate terminal of a common-source transistor (115 gate) in the cascode amplifier (100c); and
wherein the generating of an output signal comprises: generating an output signal (RFout) at a drain terminal of the cascode transistor (155 drain).
Allowable Subject Matter
Claims 3-7, 10-15, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to Claim 3:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the current injection circuit comprises: a third transistor having a first terminal, a second current terminal coupled to the second terminal of the second transistor, and a control terminal coupled to the input terminal; a fourth transistor having a first terminal, a second terminal coupled to the first terminal of the second transistor, and a control terminal; a current source having a first terminal coupled to the first power supply terminal, and a second terminal coupled to the first terminals of the third and fourth transistors; and a first resistor having a first terminal coupled to the control terminal of the third transistor, and a second terminal coupled to the control terminal of the fourth transistor.
In regard to Claim 10:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the current injection circuit comprises: an amplifier having an input coupled to the input terminal, and having an output; and a differential amplifier, having first and second inputs coupled to the output of the amplifier to establish a differential voltage between the first and second inputs, and having first and second outputs coupled to the second and first terminals of the cascode transistor, respectively.
In regard to Claim 18:
None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
applying an output signal from the common-source amplifier as a differential voltage to gate terminals of first and second differential amplifier transistors; and wherein the applying of the opposing phase compensation current comprises: applying currents from drain terminals of the first and second differential amplifier transistors to a source terminal and the drain terminal, respectively, of the cascode transistor.
However Dykstra discloses, in Figure 4E1, wherein the generating of out-of-phase injection currents comprises: receiving the input signal (RFin) at a common-source amplifier (115).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al. (US 2015/0048889) discloses an ultra-wideband low-noise amplifier circuit with low power consumption includes a cascode amplifier circuit module and an output combining circuit module. The cascode amplifier circuit module receives an input signal, and outputs a first output signal and a second output signal.
Sutardja (US 7,388,436) discloses an amplifier circuit includes a first transistor having a control terminal that receives a first amplifier input, a first terminal, and a second. The amplifier circuit includes a transimpedance amplifier having an input that communicates with the first terminal of the first transistor, and an output.
Behzad (US 2005/0088242) discloses A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage signal and to produce an output current signal.
Yang (US 2003/0016086) discloses an active cascode amplifier circuit which includes an active cascode amplifier and an amplitude limiter. The active cascode amplifier includes an input stage, an output stage and an auxiliary amplifier and receives in a voltage input signal and outputs a voltage output signal wherein the cascode amplifier amplifies the input voltage signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
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