DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 and 14-17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nishimura (US PGPUB 2024/0106424).
Regarding claim 1, Figure 2B of Nishimura discloses an auxiliary circuit configured to estimate a Miller plateau of a power transistor in a power conversion system, the auxiliary circuit comprising:
a filtering circuit [Cfb and RFB] electrically connected to a switching node of the power conversion system and configured to filter a voltage of the switching node [SN]
a sensing circuit electrically connected to an output node of the filtering circuit and configured to detect whether the voltage of the switching node becomes equal to a predetermined voltage level based on a voltage of the output node of the filtering circuit [202B; paragraphs 37 and 38; paragraph 2]
Regarding claim 2, Figure 2B of Nishimura discloses wherein an output node of the sensing circuit is electrically connected to a gate driver for the power transistor [203B].
Regarding claim 3, Figure 2B of Nishimura discloses wherein the sensing circuit is further configured to detect a zero-crossing of the voltage of the switching node [paragraphs 37 and 38; paragraph 2; Figure 3].
Regarding claim 4, Figure 2B of Nishimura discloses wherein the sensing circuit is further configured to detect a zero-crossing of the voltage of the switching node from a negative direction to a positive direction [paragraphs 37 and 38; paragraph 2; Figure 3].
Regarding claim 5, Figure 2B of Nishimura discloses wherein the sensing circuit is further configured to output a low state output signal or a high state output signal based on a detection result, and wherein the sensing circuit is further configured to change the output signal from a low state to a high state based on the voltage of the switching node becoming equal to the predetermined voltage level [paragraphs 37 and 38; paragraph 2; Figure 3].
Regarding claim 14, Figure 2B of Nishimura discloses wherein the filtering circuit comprises a high pass filter configured to filter a voltage of the switching node [Cfb and RFB].
Regarding claim 15, Figure 2B of Nishimura discloses a driving circuit for a power conversion system, the driving circuit comprising:
an auxiliary circuit configured to estimate a Miller plateau of a power transistor [200B]
a gate driver electrically connected to the auxiliary circuit [203B]
wherein the auxiliary circuit comprises a filtering circuit [Cfb and RFB] electrically connected to a switching node of the power conversion system and configured to filter a voltage of the switching node [SN]
a sensing circuit electrically connected to an output node of the filtering circuit and configured to detect whether the voltage of the switching node becomes equal to a predetermined voltage level based on the voltage of the output node of the filtering circuit, and wherein the gate driver is configured to drive the power transistor based on a detection result of the sensing circuit [202B; paragraphs 37 and 38; paragraph 2]
Regarding claim 16, Figure 2B of Nishimura discloses wherein the sensing circuit is further configured to output a low state output signal or a high state output signal based on the detection result, and wherein the gate driver is further configured to drive the power transistor based on the output signal of the sensing circuit [paragraphs 37 and 38; paragraph 2; Figure 3].
Regarding claim 17, Figure 2B of Nishimura discloses wherein the gate driver is further configured to drive the power transistor to increase the gate voltage of the power transistor by a first increment amount based on the output signal of the sensing circuit being in the low state, and to drive the power transistor to increase the gate voltage of the power transistor by a second increment amount greater than the first increment amount based on the output signal of the sensing circuit changing from the low state to the high state [paragraphs 37 and 38; paragraph 2; Figure 3].
Allowable Subject Matter
Claims 6-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-20 are allowed.
Conclusion
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/TOMI SKIBINSKI/Primary Examiner, Art Unit 2842
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