DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO AMENDMENT
Claim rejections based on prior art
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/23/2026 has been entered.
Applicant’s arguments filed on 12/22/2026 with respect to claims 1-21 have been fully considered but are moot in view of new interpretation of the cited refence due to the most recent amendment.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CANEPA (US pub. # 2014/0281171), hereinafter, “CANEPA”.
At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references.
2. As per claims 1, 12 and 21, CANEPA discloses a system (system of figs. 1A and 1B) comprising: a host (host 102 of fig. 1B) in communication with a system memory (memory 120; see paragraph 0150, which discloses “host 102 includes various volatile and/or non-volatile memory resources, as illustrated by Memory 120, variously accessible via elements of 115 and/or instances of SSD 101”) and comprising a driver (driver 107) configured to create commands for writing and reading data (see paragraph 0158, which discloses “FIG. 2 illustrates selected details of various embodiments of system contexts using lock-free communication storage request reordering. Driver 201 (e.g. as embodied by Driver 107 of FIG. 1B) is enabled for communication with Controller 202 (e.g. as embodied by an instance of SSD Controller 100 of FIG. 1B). Communication of requests (e.g. read and/or write commands) from the Driver to the Controller is illustrated conceptually by dashed-arrow Requests 203. Communication of completions (of the Requests) from the Controller to the Driver is illustrated conceptually by dashed-arrow Completions 204”); and a memory device (SSD 101 of figs. 1A and 1B) in communication with the host (see fig. 1A), and configured to store data therein (see paragraph 0129, which discloses “SSD Controller 100 is further communicatively coupled via one or more Device Interfaces 190 to NVM 199 including one or more storage devices, such as one or more instances of Flash Device 192”), the memory device comprising: a memory array including a plurality of memory components (flash devices 192) for storing memory therein (see paragraph 0137, which discloses “Device Interface Logic 191 is enabled to send data to/from the instances of Flash Device 192 according to a protocol of Flash Device 192”), a device attached memory (queue control 144 of FIG. 1A, as discloses in paragraph 0164, having the combination of request queue 210, completion queue 230, and completion status table 250 of fig. 2) being disposed within the memory device [see paragraph 0164, which discloses “in various embodiments, all or any portions of any one or more of Request Queue 210, Completion Queue 230, and Completion Status Table 250 are implemented in hardware logic circuitry (e.g. as all or any portions of Queue Control 144 of FIG. 1A)”] and having a submission queue (request queue 210) and a completion queue (completion queue 230) disposed within the device attached memory (see fig. 2 and paragraph 0164), for receiving commands from the driver (see paragraphs 0158-0161), and a device controller (intermediate controller 103 of fig. 1B) configured to communicate with the device attached memory, the host, and the plurality of memory components (see figs. 1A, 1B and paragraphs 0133 and 0134), wherein the device controller (i) receives a plurality of commands being placed into the submission queue via an interface (external interface 110, as discloses in fig. 1B) or link from the driver, and (ii) automatically executes any pending commands therein for completion (see paragraphs 0158-0161).
3. As per claim 2, CANEPA discloses “The system of claim 1” [See rejection to claim 1 above], wherein the device attached memory is memory-mapped to the host (see paragraphs 0133 and 0138).
4. As per claim 3, CANEPA discloses wherein the driver includes a non-volatile storage protocol command configured to create storage access commands (see paragraph 0151).
5. As per claims 4 and 14, CANEPA discloses wherein the device controller comprises a hybrid interconnect storage protocol device controller, wherein the device controller is configured to determine a type of interconnect packet and storage protocol command wrapped inside the interconnect packet received via the interface or link from the driver (see paragraph 0149).
6. As per claim 5, CANEPA discloses wherein the memory device is a hybrid interconnect memory device and the plurality of memory components each comprise flash memory (see fig. 1A).
7. As per claim 6, CANEPA discloses wherein upon creation of the storage protocol commands via the driver, the host is configured to raise a doorbell by placing the storage protocol commands inside the submission queue at the device attached memory and the memory device consumes any pending commands automatically therein (see paragraphs 0158-0161).
8. As per claim 7, CANEPA discloses wherein once a respective storage protocol command is completed, the device controller is configured to (i) move the completed storage protocol command to be placed in the completion queue into the device attached memory, and (ii) instruct a buffer space utilized for the respective storage protocol command to be cleared once the respective storage protocol command is completed (see paragraphs 0158-0161).
9. As per claim 8, CANEPA discloses wherein when the storage protocol command comprises a write command, the device controller is configured to confirm if the packet received at the submission queue includes the write command and, and the device controller then starts to execute the write command automatically wherein associated data is written to a memory component of the plurality of memory components (see paragraphs 0158-0161).
10. As per claim 9, CANEPA discloses wherein when a status of completion of the write command is sent to the device controller, the device controller is configured to instruct the write command to be moved to the completion queue and the buffer space occupied is thereby cleared (see paragraphs 0158-0161).
11. As per claim 10, CANEPA discloses wherein when the storage protocol command is a read command, (i) the driver is configured to prepare the packet with the read command therein and to transfer the read command to the submission queue, (ii) the device controller is configured to identify the read command in the submission queue and poll a logical-to-physical mapping table to determine a location of the data to be read as stored a memory component of the plurality of memory components, and (iii) the device attached memory is configured to move the data corresponding to the read command into the device attached memory which can then be accessed by the host (see paragraphs 0138, 0158-0161).
12. As per claim 11, CANEPA wherein once the data is read, a status of the read command is retrieved by the device controller and the read command is then placed in the completion queue (see paragraphs 0158-0161).
13. As per claim 13, CANEPA discloses wherein the device attached memory is memory mapped to the host and the driver includes a storage protocol driver configured to create storage access commands (see paragraphs 0133 and 0151).
14. As per claim 15, CANEPA discloses wherein upon creation of the storage protocol commands via the driver, the method further comprises: raising a doorbell for the device controller via the driver at the host, by placing the storage protocol commands inside the submission queue at the device attached memory and consuming any pending commands automatically therein via the device controller (see paragraphs 0158-0161).
15. As per claim 16, CANEPA discloses wherein once a respective storage protocol command is completed, the method further comprises: moving, via the device controller the completed storage protocol command into a completion queue in the device attached memory, and then instructing a buffer space utilized for the respective storage protocol command to be cleared once the respective storage protocol command is completed (see paragraphs 0158-0161).
16. As per claim 17, CANEPA discloses wherein when the storage protocol command comprises a write command, the method further comprises: confirming, via the device controller if the packet received at the submission queue includes the write command; and executing the write command automatically wherein associated data is written to a memory component of the plurality of memory components (see paragraphs 0158-0161).
17. As per claim 18, CANEPA discloses wherein the method further comprises: sending a status of completion of the write command to the device controller; and instructing, via the device controller, the write command to be moved to a completion queue of the device attached memory and the buffer space occupied thereby to be cleared (see paragraphs 0158-0161).
18. As per claim 19, CANEPA discloses wherein when the storage protocol is a read command, and the method further comprises: preparing at the driver, the packet with the read command therein and transferring the read command to the submission queue; identifying via the device controller the read command in the submission queue and polling a logical-to-physical mapping table to determine a location of the data to be read as stored a memory component of the plurality of memory components; and moving the data corresponding to the read command into the device attached memory to be accessed by the host (see paragraphs 0138, 0158).
19. As per claim 20, CANEPA discloses wherein once the data is read, the method comprises: retrieving at the device controller, a status of the read command and placing the read command in a completion queue of the device attached memory (see paragraphs 0158-0161).
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-21 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov.
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/Ernest Unelus/
Primary Examiner
Art Unit 2181
Prosecution Insights