DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/11/2026 has been entered.
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1, 3-6, 10-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hidaka et al. (Pub. No. US2013/0086295) in view of Brown et al. (Pub. No. US20100165874) and further in view of Nair (Pub. No. US20160188513)
As per claim 1, Hidaka discloses a switch (fig.3, switching node 10) comprising:
one or more input ports (fig.6, a LAN interface (10 G MAC) 401 comprises ports as the LAN interfaces (1 G MAC) 101, 102, 103 are provided to receive the frame from the terminals 1 to 3, respectively as further cited in paragraph 80);
a forwarder (fig.6, the network switch forwarding engine 100) coupled to the one or more input ports;
a virtualizer (fig.6, frame conversion circuit 412) coupled to the forwarder (fig.6, the network switch forwarding engine 100); and
one or more output ports (fig.6, upward output of hardware system 410) coupled to the virtualizer, wherein the one or more input ports to receive at least one data packet (paragraph 103, the LAN interface is provided to receive the frame), the forwarder to forward the received at least one data packet to the virtualizer (fig.6, frame conversion circuit 412 forwards frames to frame conversion circuit unit 412), and the virtualizer to convert the received at least one data packet into PCIe transactions (paragraph 87, frame conversion circuit unit 412 includes function of a frame conversion circuit that the packet format is used, at transmission via the PCI express (PCI Express) or the LAN interface, the packet format is converted into the frame format.) and to transmit the PCIe transactions on the one or more output ports (fig.6, indication to the network driver 421 is provided to transmit/receive the frame via LAN interface 401.)
Hidaka discloses all the limitations as the above but does not explicitly disclose the virtualizer to implement a root complex function. However, Brown discloses this. (paragraph 41, virtualizing I/O of a PCI root complex using a virtualization layer. The system images communicate with the virtualized resources via the virtualization layer 340, PCIe root complex 350, and one or more PCIe switches 360, and/or other PCIe fabric elements.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Brown with the teaching of Hidaka so as to allow for improved I/O performance and flexibility by enabling multiple virtual machines (VMs) to directly access hardware, rather than going through the hypervisor and so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
Hidaka in view of Brown discloses all the limitations as the above but do not explicitly disclose the virtualizer to transmit the PCIe transactions on the one or more output ports. However, Nair discloses this. (figures 7-8, paragraph 28, Switch/bridge 220 routes packets/messages, Switch 220 is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. Device 225 includes any internal or external device or component to be coupled to an electronic system, such as input/output devices, device 225 may include a PCIe to PCI/PCI-X bridge to support legacy or other version PCI devices.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Nair with the teaching of Hidaka in view of Brown so as used to enable multiple virtual machines (VMs) or applications to share a single physical device while maintaining high performance, security, and dedicated resource management so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 3, Hidaka discloses the at least one data packet comprising an Ethernet packet (The LAN interface (10 G MAC) 401)
As per claim 4, Hidaka discloses the one or more input ports coupled to a physical layer (PHY) and a media access control (MAC) circuit. (paragraph 80, The LAN interfaces (1 G MAC) 101, 102, 103 are provided to receive the frame from the terminals 1 to 3, respectively.)
As per claim 5, Hidaka discloses the one or more output ports coupled to one or more control units. (paragraph 88, frame is outputted to the LAN interface 106. The destination recognition circuit unit 115 recognizes transfer from the CPU 400 to any destination.)
As per claim 6, Hidaka discloses a system (figure 1) comprising:
a switch (fig.3, switching node 10) comprising: one or more input ports (fig.6, a LAN interface (10 G MAC) 401 comprises ports);
a forwarder (fig.6, the network switch forwarding engine 100) coupled to the one or more input ports (fig.6, a LAN interface (10 G MAC) 401 comprises ports, paragraph 102, show when the frame is forwarded to the LAN interface, input port information and the like are added to the frame);
a virtualizer (fig.6, frame conversion circuit 412) coupled to the forwarder (fig.6, the network switch forwarding engine 100);
one or more output ports (fig.6, upward output of hardware system 410) coupled to the virtualizer(fig.6, frame conversion circuit 412); and
one or more control units (fig.6, hardware system 410) coupled to at least one of the one or more output ports (fig.6, upward output of hardware system 410) coupled; and
wherein the one or more input ports (fig.6, a LAN interface (10 G MAC) 401 comprises ports, paragraph 102, show when the frame is forwarded to the LAN interface, input port information and the like are added to the frame.)to receive at least one data packet(paragraph 103, receive the frame from the network switch forwarding engine 100), the forwarder (fig.6, the network switch forwarding engine 100) to forward the received at least one data packet to the virtualizer(fig.6, frame conversion circuit 412 forwards frames to frame conversion circuit unit 412), and the virtualizer to convert the received at least one data packet into one or more PCIe transactions (paragraph 87, frame conversion circuit unit 412 includes function of a frame conversion circuit that the packet format is used, at transmission via the PCI express (PCI Express) or the LAN interface, the packet format is converted into the frame format.) and to transmit the one or more PCIe transactions to the one or more control units over the one or more output ports. (fig.6, indication to the network driver 421 is provided to be transferred to network protocol unit 430 which comprise multiple control units like the cryptography processing unit 434.)
Hidaka discloses all the limitations as the above but does not explicitly disclose the virtualizer to implement a root complex function. However, Brown discloses this. (paragraph 41, virtualizing I/O of a PCI root complex using a virtualization layer. The system images communicate with the virtualized resources via the virtualization layer 340, PCIe root complex 350, and one or more PCIe switches 360, and/or other PCIe fabric elements.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Brown with the teaching of Hidaka so as to allow for improved I/O performance and flexibility by enabling multiple virtual machines (VMs) to directly access hardware, rather than going through the hypervisor and so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
Hidaka in view of Brown discloses all the limitations as the above but do not explicitly disclose the virtualizer to transmit the PCIe transactions on the one or more output ports. However, Nair discloses this. (figures 7-8, paragraph 28, Switch/bridge 220 routes packets/messages, Switch 220 is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. Device 225 includes any internal or external device or component to be coupled to an electronic system, such as input/output devices, device 225 may include a PCIe to PCI/PCI-X bridge to support legacy or other version PCI devices.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Nair with the teaching of Hidaka in view of Brown so as used to enable multiple virtual machines (VMs) or applications to share a single physical device while maintaining high performance, security, and dedicated resource management so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 10, Hidaka discloses the one or more control units comprising a single-root virtualization (SR-IOV) endpoint. (paragraph 26, line 2, network adapter may include single root I/O virtualization (SR-IOV) adapters)
As per claim 11, Hidaka discloses a method comprising:
receiving a data packet at an input port (fig.6, a LAN interface (10 G MAC) 401 comprises ports) of a switch (fig.3, switching node 10);
processing the received data packet at the switch (fig.6, a LAN interface (10 G MAC) 401 comprises ports, paragraph 102, show when the frame is forwarded to the LAN interface, input port information and the like are added to the frame);
generating, in a virtualizer (fig.6, the network switch forwarding engine 100) within the switch, a PCIe transaction based on the received data packet (paragraph 87, frame conversion circuit unit 412 includes function of a frame conversion circuit that the packet format is used, at transmission via the PCI express (PCI Express) or the LAN interface, the packet format is converted into the frame format); and
transmitting the PCIe transaction to the one or more control units (fig.6, indication to the network driver 421 is provided to be transferred to network protocol unit 430 which comprise multiple control units like the cryptography processing unit 434.)
Hidaka discloses all the limitations as the above but does not explicitly disclose implementing, in the virtualizer within the switch, a root complex function. However, Brown discloses this. (paragraph 41, virtualizing I/O of a PCI root complex using a virtualization layer. The system images communicate with the virtualized resources via the virtualization layer 340, PCIe root complex 350, and one or more PCIe switches 360, and/or other PCIe fabric elements.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Brown with the teaching of Hidaka so as to allow for improved I/O performance and flexibility by enabling multiple virtual machines (VMs) to directly access hardware, rather than going through the hypervisor and so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
Hidaka in view of Brown discloses all the limitations as the above but do not explicitly disclose the virtualizer to transmit the PCIe transactions on the one or more output ports. However, Nair discloses this. (figures 7-8, paragraph 28, Switch/bridge 220 routes packets/messages, Switch 220 is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. Device 225 includes any internal or external device or component to be coupled to an electronic system, such as input/output devices, device 225 may include a PCIe to PCI/PCI-X bridge to support legacy or other version PCI devices.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Nair with the teaching of Hidaka in view of Brown so as used to enable multiple virtual machines (VMs) or applications to share a single physical device while maintaining high performance, security, and dedicated resource management so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 14, Hidaka discloses the one or more control units comprising a single-root virtualization (SR-IOV) endpoint. (paragraph 26, line 2, network adapter may include single root I/O virtualization (SR-IOV) adapters)
4. Claims 8-9 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Hidaka et al. (Pub. No. US2013/0086295) in view of Brown et al. (Pub. No. US20100165874) and further in view of Nair (Pub. No. US20160188513) and further in view of Potlapally (Pub. No. US20220197683)
As per claims 8 and 12, Hidaka, Brown in view of Nair disclose all the limitations as the above but does not explicitly disclose at least one of the one or more control units comprising an automotive control unit. However, Potlapally discloses this (paragraph 220, “output device” is intended to include all possible types of devices and mechanisms for outputting information from computer system 1500 to a user or other computer. For example, user interface output devices may include automotive navigation systems.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Potlapally with the teaching of Hidaka, Brown in view of Brown so as to provide system with broader choices and flexibility as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claims 9 and 13, Potlapally discloses the one or more control units comprising an Automotive Customer Zonal Network (paragraph 230, line 5, automobile traffic monitoring).
5. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Fenkes et al. [Pub. No. US20150110122] discloses a fabric name to switching elements of a distributed switch configured to forward Fibre Channel over Ethernet (FCoE) frames.
Response to Amendment
6. Applicant's amendment filed on 2/11/2026 have been fully considered but are moot in view of the new ground(s) of rejection.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184