Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1-24 and 26-33 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHOI (US 20230189590 A1).
Regarding claim 1, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses a display apparatus, comprising:
a substrate (substrate SUB) including a display area (display area DA; [0097]) having a plurality of subpixels (subpixels SPX);
a first data line (data line DL1) disposed at the display area (display area DA) and extending in a column direction (direction DR2);
a first link line (data connection lines DCL2; [0129]-[0130]) disposed at the display area (display area DA), electrically connected to the first data line (data line DL1), and extending in a row direction (direction DR1);
a second link line (data connection lines DCL1; [0128]-[0129]) disposed at the display area (display area DA) and extending in the column direction (direction DR2);
a first metal pattern (e.g., Figs. 8-9; metal pattern HDP or metal pattern HPL2; [0258]) spaced apart from the first link line (data connection lines DCL2) and extending in the row direction (direction DR1); and
a second metal pattern (e.g., Figs. 8-9; metal pattern VDP; [0261]) spaced apart from the second link line (data connection lines DCL1) and extending in the column direction (direction DR2).
Regarding claim 2, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 1, wherein the first link line (data connection lines DCL2) and the first metal pattern (metal pattern HDP) are disposed in a first metal layer (metal layer DTL2; [0258]), and the second link line (data connection lines DCL1) and the second metal pattern (metal pattern VDP) are disposed in a second metal layer (metal layer DTL3; [0261]) different from the first metal layer (metal layer DTL2).
Regarding claim 3, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 2, wherein the second metal layer (e.g., Figs. 26-29; metal layer DTL3) is disposed further from the substrate (substrate SUB) than the first metal layer (e.g., Figs. 26-29; metal layer DTL2).
Regarding claim 4, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 1, further comprising a low power supply voltage line (Fig. 4; low power supply line PL; [0133] and [0166]) configured to supply a low power supply voltage to the plurality of subpixels (Fig. 4; subpixel SPX), wherein the low power supply voltage line (low power supply line PL or VPL) is electrically connected to at least one of the first metal pattern and the second metal pattern (metal patterns HDP and VDP; [0133], [0166], [0187], [0195], [0202], and [0263]).
Regarding claim 5, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 1, wherein each of the plurality of subpixels comprises a light emitting element (Figs. 5-6 and 26; light emitting element LEL) including a pixel electrode (pixel electrode 171; [0265]), an intermediate layer (light emitting layer 172; [0265]), and a common electrode (common electrode 173; [0265]), and wherein the first metal pattern and the second metal pattern (metal patterns HDP and VDP connected to low power supply voltage line; [0133], [0166], [0187], [0195], [0202], and [0263]) are electrically connected to the common electrode (common electrode 173; [0144] and [0161]).
Regarding claim 6, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 1, further comprising: a first open area between the first metal pattern and the first link line (Figs. 7-9; metal pattern HPL2 and data connection line DCL2 are spaced apart and form an open area in between); and a first shielding pattern overlapping with the first open area (Figs. 7-9; metal pattern VDP, metal pattern VPL1, or pixel electrode 171 overlapping the open area between the metal pattern HPL2 and the data connection line DCL2).
Regarding claim 7, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 6, wherein each of the plurality of subpixels comprises a light emitting element (Figs. 5-6 and 26; light emitting element LEL) including a pixel electrode (pixel electrode 171; [0265]), an intermediate layer (light emitting layer 172; [0265]), and a common electrode (common electrode 173; [0265]), and wherein the first shielding pattern is the pixel electrode or includes a same material as the pixel electrode (Figs. 7-9 and 24-26, pixel electrode 171 acting as a shielding pattern or metal pattern VDP or VPL1 including a same metal material as pixel electrode 171 and acting as a shielding pattern; [0185], [0261], and [0266]).
Regarding claim 8, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 6, wherein the first shielding pattern is a metal pattern (metal pattern VDP or VPL1) disposed in a metal layer in which the second link line (data connection lines DCL1) and the second metal pattern (metal pattern VDP) are disposed.
Regarding claim 9, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 6, wherein the first shielding pattern is disposed in a same metal layer as a vertical line extending in the column direction (metal pattern VDP or VPL1 is a line pattern in direction DR2).
Regarding claim 10, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 6, wherein the first open area is one of a plurality of first open areas disposed in a metal layer in which the first link line and the first metal pattern are disposed (Figs. 7-9; metal patterns HPL2 and data connection lines DCL2 are spaced apart and form a plurality of open areas), and wherein a plurality of first shielding patterns including the first shielding pattern overlap with the plurality of first open areas (Figs. 7-9; metal patterns VDP or metal patterns VPL1 overlapping the plurality of open areas between the metal pattern HPL2 and the data connection line DCL2), and the plurality of first shielding patterns are disposed at a pre-defined angle with respect to the column direction or the row direction (Figs. 7-9; metal patterns VDP or metal patterns VPL1 are arranged at 90° with respect to direction DR1).
Regarding claim 11, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 1, further comprising: a second open area (Figs. 8-12; opening SU1 or SU2) between the second metal pattern (e.g., Figs. 8-12; metal pattern VDP) and the second link line (Figs. 8-12; data connection lines DCL1); and a second shielding pattern overlapping with the second open area (Figs. 10 and 13-16, shielding pattern HPL2 or shielding pattern 171; [0185], [0258], and [0266]).
Regarding claim 12, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 11, wherein each of the plurality of subpixels comprises a light emitting element (Figs. 5-6 and 26; light emitting element LEL) including a pixel electrode (pixel electrode 171; [0265]), an intermediate layer (light emitting layer 172; [0265]), and a common electrode (common electrode 173; [0265]), and wherein the second shielding pattern is the pixel electrode or includes a same material as the pixel electrode (Figs. 13-16, pixel electrode 171 corresponding to a shielding pattern or metal pattern HPL2 including a same metal material as pixel electrode 171 and acting as a shielding pattern; [0185], [0258], and [0266]).
Regarding claim 13, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 11, wherein the second open area is one of a plurality of second open areas (Figs. 8-12; openings SU1 or SU2) disposed in a metal layer in which the second link line and the second metal pattern are disposed (e.g., Figs. 8-12; metal pattern VDP and data connection lines DCL1), and wherein a plurality of second shielding patterns including the second shielding pattern overlap with the plurality of second open areas (e.g., Fig. 10; shielding pattern HPL2 overlapping opening SU1), and the plurality of second shielding patterns are disposed at a pre-defined angle with respect to the column direction or the row direction (e.g., Fig. 10; 90° with respect to direction DR2).
Regarding claim 14, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 1, wherein the first data line (data line DL1) is disposed in a metal layer in which the second link line (data connection lines DCL1) and the second metal pattern (metal pattern VDP) are disposed (e.g., Figs. 7 and 19).
Regarding claim 15, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 1, wherein each of the plurality of subpixels includes a light emitting element and two or more transistors (Figs. 5-6 and 26; light emitting element LEL and transistors ST1-ST6 and DT), wherein the light emitting element includes a pixel electrode (pixel electrode 171), an intermediate layer (light emitting layer 172), and a common electrode (common electrode 173), and wherein respective source or drain electrodes in the two or more transistors includes a metal layer in which the first link line and the first metal pattern are disposed (Figs. 26-27; metal layer DTL2 including data connection lines DCL2, metal pattern HDP, and source or drain connection electrodes CE4 and CE5; [0258]).
Regarding claim 16, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 15, further comprising a connection electrode (connection electrode CE6) configured to electrically connect the pixel electrode (pixel electrode 171) with a source electrode or a drain electrode (drain connection electrode CE5) of a first transistor (transistor ST6) among the two or more transistors (transistors ST1-ST6 and DT), wherein the connection electrode includes a metal layer in which the second link line and the second metal pattern are disposed (Figs. 26-27; metal layer DTL3 including data connection lines DCL1, metal pattern VDP, and connection electrode CE6; [0261]).
Regarding claim 17, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 1, wherein the substrate comprises a non-display area (Figs. 2 and 4; non-display area NDA) outside of the display area, wherein the non-display area (non-display area NDA) includes a pad area having a pad (Figs. 2 and 4; pad area PA including a pad PD; [0114]), and wherein the second link line (data connection lines DCL1) electrically connects the first link line (data connection lines DCL2) to the pad (pad PD).
Regarding claim 18, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 1, wherein the display area comprises: a first area in which horizontal link lines extending in the row direction and vertical link lines extending in the column direction are not disposed (display area DA2 does not include data connection lines DCL2 and data connection lines DCL1); a second area including the horizontal link lines (data connection lines DCL2); and a third area including the vertical link lines (data connection lines DCL1), and wherein the horizontal link lines include the first link line (data connection lines DCL2), and the vertical link lines include the second link line (data connection lines DCL1).
Regarding claim 19, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 18, further comprising: a first open area (e.g., Figs. 7-9; open area SU3) between the first metal pattern (metal pattern HDP) and the first link line (data connection lines DCL2), wherein the first open area (open area SU3) is present at a boundary of the first area and the second area (e.g., Figs. 7-9).
Regarding claim 20, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 19, further comprising: a second open area (e.g., Figs. 7-9; open area SU1/SU2) between the second metal pattern (metal pattern VDP) and the second link line (data connection lines DCL1), wherein the first open area (open area SU3) and the second open area (open area SU1/SU2) are present at a boundary of the second area and the third area (e.g., Figs. 7-9).
Regarding claim 21, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 1, wherein the first metal pattern (e.g., Figs. 7-9; metal pattern HDP) is disposed in the same shape as the first link line (e.g., Figs. 7-9; data connection lines DCL2), and the second metal pattern (e.g., Figs. 7-9; metal pattern VDP) is disposed in the same shape as the second link line (e.g., Figs. 7-9; data connection lines DCL1).
Regarding claim 22, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 4, wherein the low power voltage line is configured in horizontal metal patterns including the first metal pattern (e.g., Figs. 7-9 and 17-23; metal pattern HDP) and vertical metal patterns including the second metal pattern (e.g., Figs. 7-9 and 17-23; metal pattern VDP).
Regarding claim 23, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 2, further comprising: a third link line (e.g., Figs. 7-9; third data connection line DCL2) disposed in the first metal layer (metal layer DTL2); a fourth link line (e.g., Figs. 7-9; fourth data connection line DCL1) disposed in the second metal layer (metal layer DTL3); a third metal pattern (e.g., Figs. 7-9; third metal pattern HDP) spaced apart from the third link line (third data connection line DCL2), extending in the row direction (direction DR1), and disposed in the same row as the third link line (third data connection line DCL2), and a fourth metal pattern (e.g., Figs. 7-9; fourth metal pattern VDP) spaced apart from the fourth link line (fourth data connection line DCL1), extending in the column direction (direction DR2), and disposed in the same column as the fourth link line (fourth data connection line DCL1).
Regarding claim 24, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses a display apparatus, comprising:
a substrate (substrate SUB);
a first signal line (data connection lines DCL2; [0129]-[0130]) disposed on the substrate (substrate SUB) and extending in a first direction (direction DR1);
a first power line including a same first metal as the first signal line (e.g., Figs. 8-9; first power line including metal pattern HDP or metal pattern HPL2; [0258]) and spaced apart from the first signal line (data connection lines DCL2);
a second signal line (data connection lines DCL1; [0128]-[0129]) disposed on the substrate (substrate SUB) and extending in a second direction (direction DR2) different from the first direction (direction DR1); and
a second power line including a same second metal as the second signal line (e.g., Figs. 8-9; second power line including metal pattern VDP; [0261]) and spaced apart from the second signal line (data connection lines DCL1).
Regarding claim 26, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 24, further comprising a first shielding pattern overlapping with a first open area in which the first signal line and the first power line are disconnected (Figs. 7-9; metal pattern VDP, metal pattern VPL1, or pixel electrode 171 overlapping an open area formed between the metal pattern HPL2 and the data connection line DCL2).
Regarding claim 27, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 24, further comprising a second shielding pattern overlapping with a second open area in which the second signal line and the second power line are disconnected (e.g., Figs. 8-12; metal pattern VDP and data connection lines DCL1 form opening SU1 or SU2; Figs. 10 and 13-16, shielding pattern HPL2 or shielding pattern 171 overlapping the opening; [0185], [0258], and [0266]).
Regarding claim 28, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 24, wherein the first signal line is disposed at a display area (display area DA) configured to display an image (data connection lines DCL2 configured to display an image), and all or some of the second signal line (data connection lines DCL1) is disposed at the display area (display area DA).
Regarding claim 29, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 24, wherein the first signal line (data connection lines DCL2) is electrically connected to the second signal line (data connection lines DCL1).
Regarding claim 30, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 24, wherein the first power line (e.g., Figs. 8-9; first power line including metal pattern HDP or metal pattern HPL2; [0258]) extends in the first direction (direction DR1), and the second power line (e.g., Figs. 8-9; second power line including metal pattern VDP; [0261]) extends in the second direction (direction DR2).
Regarding claim 31, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 24, wherein the first signal line (data connection lines DCL2) and the first power line (first power line including metal pattern HDP or metal pattern HPL2) are disposed in a first metal layer (metal layer DTL2; [0258]), and the second signal line (data connection lines DCL1) and the second power line (second power line including metal pattern VDP) are disposed in a second metal layer (metal layer DTL3) different from the first metal layer (metal layer DTL2).
Regarding claim 32, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 31, further comprising: a first shielding pattern overlapping with a first open area between the first signal line and the first power line (Figs. 7-9; metal pattern VDP or metal pattern VPL1 overlapping an open area formed between the metal pattern HPL2 and the data connection line DCL2), wherein the first shielding pattern is disposed in at least one of the second metal layer and a layer in which a pixel electrode is disposed (metal pattern VDP or metal pattern VPL1 disposed in the metal layer DTL3; [0261]).
Regarding claim 33, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 32, further comprising: a second shielding pattern overlapping with a second open area between the second signal line and the second power line, wherein the second shielding pattern is disposed in the layer in which the pixel electrode is disposed (e.g., Figs. 8-12; metal pattern VDP and data connection lines DCL1 form opening SU1 or SU2; Figs. 10 and 13-16, shielding pattern HPL2 or shielding pattern 171 overlapping the opening; [0185], [0258], and [0266]).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim 25 is rejected under 35 U.S.C. 103 as unpatentable over CHOI (US 20230189590 A1) in view of LEE (US 20170169764 A1).
Regarding claim 25, CHOI (e.g., Figs. 4, 7-9, 17-23, and 25-26) discloses the display apparatus of claim 24, wherein a signal, a voltage level of which is variable over time, is applied to the first signal line and the second signal line, and a power signal (Figs. 5-6; image signal is applied to the data connection lines DCL1 and the data connection lines DCL2), CHOI also disclose a signal, is applied to the first power line and the second power line (Figs. 5-6; a low voltage or common voltage is applied to common electrode or cathode of the light emitting element through to the first power line and the second power line). CHOI does not expressly disclose the low voltage or common voltage signal has a voltage level of which does not vary over time because it is well known in the art. As a reference, LEE discloses an OLED display device similar to that disclosed by CHOI, wherein the low voltage or common voltage signal has a voltage level of which does not vary over time (e.g., Fig. 4, 6, and 8 and [0060]; ground voltage). Therefore, it would have been obvious to one skilled in the art at the effective filing date of the claimed invention to incorporate the teaching from LEE to the display device of CHOI to provide a common voltage to the light emitting elements.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUZHEN SHEN whose telephone number is (571)272-1407. The examiner can normally be reached on 9:00-18:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUZHEN SHEN/Primary Examiner, Art Unit 2623
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