DETAILED ACTION
This action is in response to the 03/24/2026 amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 2, 7, 18 – 19 and 24 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US Pub. No. 2023/0412079; (hereinafter Parto).
Regarding claim 1, Parto [e.g. Fig. 26 - 29] discloses a system comprising: a series capacitor buck two-level power converter (SCB2L) comprising a plurality of switches [e.g. 314, 316, 318, 320, 350], a first power inductor [e.g. 310] electrically coupled to the plurality of switches, a second power inductor [e.g. 312] electrically coupled to the plurality of switches, and a flying capacitor [e.g. 322] electrically coupled to the plurality of switches, wherein the plurality of switches are controllable in a periodic manner [e.g. Fig. 28] among a plurality of switch configurations [e.g. Fig. 27A-27D] in order to generate an output voltage [e.g. Vout at 304] from an input voltage [e.g. Vin at 302] received by the SCB2L, wherein the plurality of switch configurations comprises: a first switch configuration [e.g. Fig. 27A] in which electrical charge on the flying capacitor is increased [e.g. paragraph 0187 recites “FIG. 27A shows a first state of operation, where the first switch 314 and the second switch 316 are on, and where the third switch 318, fourth switch 320, and fifth switch 350 are off. In the first state of operation (FIG. 27A), current I1 can flow from the input 304, through the first switch 314, to the capacitor 322. The voltage across the capacitor 322 can increase, thereby storing energy in the capacitor 322”]; and a second switch configuration [e.g. Fig. 27D] in which electrical charge on the flying capacitor is decreased [e.g. paragraph 0190 recites “During the fourth state of operation (FIG. 27D), the first inductor 310 can draw current through the fourth switch 320. The current through the first inductor 310 can decrease as the first inductor 310 outputs some of its stored energy. During the fourth state of operation (FIG. 27D), the first capacitor 322 can discharge energy, at least some of which can be received and stored by the second capacitor 352”]; and a control subsystem [e.g. Fig. 26; Driver 328] configured to selectively increase and decrease a difference in time between a first duration of the first switch configuration and a second duration of the second switch configuration within switching cycles of the SCB2L [e.g. paragraph 0193 recites “The duty cycles of FIG. 28 can produce a first output voltage. If their duty cycles were changed so that the first and/or third states have longer durations and so that the second and/or fourth states have shorter durations, then a second output voltage that is higher than the first output voltage can be produced. If the duty cycles were changed so that the first and/or third states have even shorter durations and so that the second and/or fourth states have even longer durations, then a third output voltage that is lower than the first output voltage can be produced.” Paragraph 0196 recites “By changing the duty cycle (e.g., to 40% or 80%), other output voltages can be achieved (e.g., about 1.2 volts or about 2.4 volts)”].
Regarding claim 2, Parto [e.g. Fig. 26 - 28] discloses wherein the control subsystem is further configured to selectively increase and decrease the difference in time in order to control a flying capacitor voltage across the flying capacitor [e.g. as stated with respect to paragraph 193 and 196 above. The voltage at the flying capacitor 322 is directly controlled by the duty cycle of the switches].
Regarding claim 7, Parto [e.g. Fig. 26 - 28] discloses wherein the control subsystem is further configured to selectively increase and decrease the difference in time [e.g. duty cycle; paragraph 193 and 196 above with respect to claim 1] in order to control a current difference between a first inductor current through the first power inductor and a second inductor current through the second power inductor [e.g. inductor currents differences (Figs. 27A-27D) are directly controlled by the duty cycle changes].
Regarding claim 18, Parto [e.g. Fig. 26 - 29] discloses a method, in a system having a series capacitor buck two-level power converter (SCB2L) comprising a plurality of switches [e.g. 314, 316, 318, 320, 350], a first power inductor [e.g. 310] electrically coupled to the plurality of switches, a second power inductor [e.g. 312] electrically coupled to the plurality of switches, and a flying capacitor [e.g. 322] electrically coupled to the plurality of switches, wherein the plurality of switches are controllable in a periodic manner [e.g. Fig. 28] among a plurality of switch configurations [e.g. Fig. 27A-27D] in order to generate an output voltage [e.g. Vout at 304] from an input voltage [e.g. Vin at 302] received by the SCB2L, wherein the method comprises: selectively increasing and decreasing, within switching cycles of the SCB2L, a difference in time [e.g. paragraph 0193 recites “The duty cycles of FIG. 28 can produce a first output voltage. If their duty cycles were changed so that the first and/or third states have longer durations and so that the second and/or fourth states have shorter durations, then a second output voltage that is higher than the first output voltage can be produced. If the duty cycles were changed so that the first and/or third states have even shorter durations and so that the second and/or fourth states have even longer durations, then a third output voltage that is lower than the first output voltage can be produced.” Paragraph 0196 recites “the duration of the first stage can be substantially the same as the duration of the third stage (e.g., about 10% each in FIG. 29). In some embodiments, the duration of the second stage can be substantially the same as the duration of the fourth stage (e.g., about 40% each in FIG. 29). FIG. 30 shows that an output of about 1.8 volts can be produced from an input voltage of about 6 volts by using the duty cycle of 60% of FIG. 29. By changing the duty cycle (e.g., to 40% or 80%), other output voltages can be achieved (e.g., about 1.2 volts or about 2.4 volts)”] between: a first duration of a first switch configuration [e.g. Fig. 27A] of the plurality of switch configurations [e.g. Fig. 27A-27D] in which electrical charge on the flying capacitor is increased [e.g. paragraph 0187 recites “FIG. 27A shows a first state of operation, where the first switch 314 and the second switch 316 are on, and where the third switch 318, fourth switch 320, and fifth switch 350 are off. In the first state of operation (FIG. 27A), current I1 can flow from the input 304, through the first switch 314, to the capacitor 322. The voltage across the capacitor 322 can increase, thereby storing energy in the capacitor 322”]; and a second duration of a second switch configuration [e.g. Fig. 27D] of the plurality of switch configurations in which electrical charge on the flying capacitor is decreased [e.g. paragraph 0190 recites “During the fourth state of operation (FIG. 27D), the first inductor 310 can draw current through the fourth switch 320. The current through the first inductor 310 can decrease as the first inductor 310 outputs some of its stored energy. During the fourth state of operation (FIG. 27D), the first capacitor 322 can discharge energy, at least some of which can be received and stored by the second capacitor 352”].
Regarding claim 19, Parto [e.g. Fig. 26 - 28] discloses further comprising selectively increasing and decreasing the difference in time in order to control a flying capacitor voltage across the flying capacitor [e.g. as stated with respect to paragraph 193 and 196 above in claim 18. The voltage at the flying capacitor 322 is directly controlled by the duty cycle of the switches].
Regarding claim 24, Parto [e.g. Fig. 26 - 28] discloses further comprising selectively increasing and decreasing the difference in time [e.g. duty cycle; paragraph 193 and 196 above with respect to claim 18] in order to control a current difference between a first inductor current through the first power inductor and a second inductor current through the second power inductor [e.g. inductor currents differences (Figs. 27A-27D) are directly controlled by the duty cycle changes].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claims 16 and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parto in view of US Pub. No. 2024/0055990; (hereinafter Kawano).
Regarding claim 16 and claim 33, Parto fails to disclose wherein the first power inductor and the second power inductor are integral to a coupled inductor.
Kawano [e.g. Fig. 1] teaches wherein the first power inductor [e.g. L1] and the second power inductor [e.g.L2] are integral to a coupled inductor [e.g. paragraph 054 recites “the coupled inductor 112 includes a first inductor L1 and a second inductor L2 that are magnetically coupled”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Parto by wherein the first power inductor and the second power inductor are integral to a coupled inductor as taught by Kawano in order of being able to provide superior power density, efficiency and transient response, as it is well known in the art.
Claims 17 and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parto in view of US Pub. No. 2025/0337324; (hereinafter Huang),
Regarding claim 17 and claim 34, Parto fails to disclose wherein the first power inductor and the second power inductor are integral to a trans-inductor voltage regulator.
Huang [e.g. Fig. 1A] teaches wherein the first power inductor [e.g. L1] and the second power inductor [e.g. L2] are integral to a trans-inductor voltage regulator [e.g. paragraph 07 recites “FIG. 1A illustrates a schematic diagram of a power electronics circuit that includes a trans-inductor voltage regulator (TLVR) inductor module”. Paragraph 020 recites “two TLVR inductors L1, L2 integrated in the TLVR inductor module 100”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Parto by wherein the first power inductor and the second power inductor are integral to a trans-inductor voltage regulator as taught by Huang in order of being able to provide superior transient response and reduced voltage droop, as it is well known in the art.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
Applicant's arguments filed 03/24/2026 have been fully considered but they are not persuasive.
Applicant(s) argue(s) with respect to claims 1 and 18 in pages 12:
“There is no teaching or suggestion anywhere in Parto that the driver 328 or any other component constitutes a "control subsystem configured to selectively increase and decrease a difference in time between a first duration of the first switch configuration and a second duration of the second switch configuration within switching cycles of the SCB2L," as recited in Claim 1. Applicant respectfully disagrees with the Examiner's mapping for at least the following reasons.
First, Parto teaches only conventional duty cycle control. As described in Paragraphs [0193] and [0196] thereof, Parto adjusts duty cycle to change output voltage. Such adjustment proportionally changes the durations of switching states. There is no disclosure of independently controlling the duration of one switch configuration relative to another.
In response, the Examiner submits that the claims does not invalidate the use of a duty cycle control. Parto teaches changing the increasing and decreasing the duty cycle of the first and third states and the second and fourth states. It is well known in the art that a switching duty cycle corresponds to a time a signal controlling the switches are active. The Non-Final Office Action 03/03/2026, states that the first switching configuration corresponds to Fig. 27A (Parto’s first state) and the second configuration corresponds to Fig. 27D (Parto’s fourth state). Therefore, Parto’s in paragraph 193, disclose that the first and third states are increased/decreased and the second and fourth states are respectively decreased/increased. Therefore, Parto does disclose selectively controlling a duration of one switch configuration relative to another.
Applicant(s) argue(s) with respect to claims 1 and 18 in pages 12 – 13:
Second, the claims require asymmetric timing control (α), not duty cycle (D). As described in the specification of the present application, the claimed "difference in time" corresponds to an offset parameter α that skews the relative durations of switch configurations (e.g., REF1 = D - α and REF2 = D + α). This offset is independent of duty cycle and enables control of flying capacitor voltage and inductor current imbalance.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., asymmetric timing control, offset parameter α that skews the relative durations of switch configurations (e.g., REF1 = D - α and REF2 = D + α)) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant(s) argue(s) with respect to claims 1 and 18 in pages 13:
Third, Parto lacks any teaching of such offset-based control. In Parto, switching state durations change uniformly with duty cycle. There is no teaching or suggestion of selectively increasing the duration of one configuration while decreasing another independently of duty cycle.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., selectively increasing the duration of one configuration while decreasing another independently of duty cycle) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Further, Parto’s in paragraph 193, does disclose that the first and third states are increased/decreased and the second and fourth states are respectively decreased/increased.
Applicant(s) argue(s) with respect to claims 1 and 18 in pages 13:
Fourth, the limitation is not inherent. Adjusting duty cycle does not inherently produce asymmetric timing between specific switch configurations, as required by the claims. Furthermore, Claim 1 recites a control subsystem that controls a particular parameter: the difference in time between the duration of the first switch configuration (in which the flying capacitor charges) and the duration of the second switch configuration (in which the flying capacitor discharges).
In contrast, Parto teaches only conventional duty cycle control for output voltage regulation. When Parto's duty cycle is changed, all state durations scale proportionally: States 1 and 3 (both the same charging configuration) change together, and States 2 and 4 change together. There is no teaching anywhere in Parto of independently or selectively controlling the difference between the duration of one specific switch configuration (charging) and the duration of another specific switch configuration (discharging).
Furthermore, anticipation under 35 U.S.C. § 102 requires that the reference teach every element of the claimed invention either explicitly or inherently. The Examiner has not established, nor could the Examiner establish, that Parto's duty cycle control for output voltage inherently discloses a control subsystem that selectively increases and decreases a difference in time between two specific switch configuration durations. The "difference in time" as claimed is a specific, independently controlled parameter, and not a mere byproduct of overall duty cycle adjustment.”
In response,
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Parto’s paragraph 0193 recite:
“The duty cycles of FIG. 28 can produce a first output voltage. If their duty cycles were changed so that the first and/or third states have longer durations and so that the second and/or fourth states have shorter durations, then a second output voltage that is higher than the first output voltage can be produced. If the duty cycles were changed so that the first and/or third states have even shorter durations and so that the second and/or fourth states have even longer durations, then a third output voltage that is lower than the first output voltage can be produced.”
By analyzing the statement of paragraph 0193 with respect to Fig. 28 above, when the time of the first state is increased with a longer duration (e.g. claimed “first duration of the first switch configuration”) so that the fourth state (e.g. claimed “second duration of the second switch configuration”) time is decrease with a shorter duration, the claim is met since a difference in time between state 1 (Fig. 28 above) will be changed with respect to the fourth state (Fig. 28 above). In the same way, when the time of the first state is decreased with a shorter duration so that the fourth state (e.g. claimed “second duration of the second switch configuration”) time is increased with a longer duration, the claim is met since a difference in time between state 1 will be changed with respect to the fourth state.
Therefore, the rejection is maintained.
Allowable Subject Matter
Claims 3 – 6, 8 – 15 and 20 – 23, 25 – 32 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 3 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the control subsystem is further configured to: determine an error signal between the flying capacitor voltage and a reference voltage; apply a filter to the error signal to generate an offset signal; and selectively increase and decrease the difference in time based on the offset signal”.
The primary reason for the indication of the allowability of claim 6 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the control subsystem is further configured to estimate the flying capacitor voltage from an observer that uses a mathematical model of the system and measured states of the system to form an estimate of the flying capacitor voltage”.
The primary reason for the indication of the allowability of claim 8 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the control subsystem is further configured to: determine an error signal between the current difference and a reference current difference; apply a filter to the error signal to generate an offset signal; and selectively increase and decrease the difference in time based on the offset signal”.
The primary reason for the indication of the allowability of claim 11 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the control subsystem is further configured to estimate the current difference from an observer that uses a mathematical model of the system and measured states of the system to form an estimate of the current difference”.
The primary reason for the indication of the allowability of claim 12 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the control subsystem is further configured to: determine a first error signal between the flying capacitor voltage and a reference voltage; apply a first filter to the first error signal to generate a first intermediate offset signal; determine a second error signal between: (a) a current difference between a first inductor current through the first power inductor and a second inductor current through the second power inductor and (b) a reference current difference; apply a second filter to the second error signal to generate a second intermediate offset signal; sum the first intermediate offset signal and the second intermediate offset signal to generate an offset signal; and selectively increase and decrease the difference in time based on the offset signal”.
The primary reason for the indication of the allowability of claim 20 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising: determining an error signal between the flying capacitor voltage and a reference voltage; applying a filter to the error signal to generate an offset signal; and selectively increasing and decreasing the difference in time based on the offset signal”.
The primary reason for the indication of the allowability of claim 23 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising estimating the flying capacitor voltage from an observer that uses a mathematical model of the system and measured states of the system to form an estimate of the flying capacitor voltage”.
The primary reason for the indication of the allowability of claim 25 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising: determining an error signal between the current difference and a reference current difference; applying a filter to the error signal to generate an offset signal; and selectively increasing and decreasing the difference in time based on the offset signal”.
The primary reason for the indication of the allowability of claim 28 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising estimating the current difference from an observer that uses a mathematical model of the system and measured states of the system to form an estimate of the current difference”.
The primary reason for the indication of the allowability of claim 29 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising: determining a first error signal between the flying capacitor voltage and a reference voltage; applying a first filter to the first error signal to generate a first intermediate offset signal; determining a second error signal between: (a) a current difference between a first inductor current through the first power inductor and a second inductor current through the second power inductor and (b) a reference current difference; applying a second filter to the second error signal to generate a second intermediate offset signal; summing the first intermediate offset signal and the second intermediate offset signal to generate an offset signal; and selectively increasing and decreasing the difference in time based on the offset signal”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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/ALEX TORRES-RIVERA/ Primary Examiner, Art Unit 2838
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