Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Okuno (WO 2021152945 A1) in further view of Ando (US 20180090591 A1).
Regarding Claim 1, Okuno teaches a semiconductor structure (shown Fig. 2) comprising:
a substrate (shown Fig. 2)) having a plurality of channel portions (defined between diffusion regions 204 and 304, shown Fig. 2);
a ferroelectric field effect transistor (FeFET) (20) on the substrate, the FeFET comprising:
a first channel portion (channel defined between diffusion regions 204) of the substrate;
a crystalline ferroelectric dielectric (213, a hafnium oxide ferroelectric film which is “crystallized by a process flow”) on the first channel portion; and
an upper electrode (214) on the crystalline ferroelectric dielectric; and
a ferroelectric capacitor (FeCAP) (capacitor C of 1T1C 30, shown Fig. 2) on the substrate comprising:
a second channel portion (defined between diffusion regions 304) of the substrate;
the crystalline ferroelectric dielectric (portion 313, which is a portion formed of the same crystalline ferroelectric film layer as shown in Fig. 10h) on and in contact with the second channel portion of the substrate (shown Fig. 2);
a lower electrode (317) on the crystalline ferroelectric dielectric; and
the upper electrode (portion 314 being the same electrode layer as 214, shown Fig. 10h) on the lower electrode.
Okuno further teaches an interfacial oxide (102, 402) being present in Figs. 2 and 9d, but removed from the FeFET portion of the semiconductor structure in Fig. 9e. Further, Okuno does not explicitly teach the lower electrode comprising a scavenging material.
Ando teaches semiconductor structure (100, shown Fig. 1) wherein an equivalent oxide thickness may be reduced by scavenging an interfacial oxide layer (see [0053] and [0003] further suggesting that this may apply to ferroelectric capacitors and ferroelectric transistors), wherein the device comprises an interfacial oxide (120) on a substrate (110), a hafnium oxide layer (130), a lower electrode (140), wherein the lower electrode comprises a scavenging material (144, see also Ando [0038]) disposed between two TiN layers (142 and 146, analogous to the material of the lower electrode of Okuno) and an upper electrode 150.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to adopt the scaled gate dielectric structure of Ando to the FeCAP and FeFET structures of Okuno as this would minimize an effective oxide thickness of the crystalline ferroelectric dielectric layer (see Ando: [0021-0022], [0059]), thus increasing device density and improving device performance (see Ando: [0002]).
Specifically, this modification would further teach an interfacial oxide being present between the crystalline ferroelectric dielectric layer of Okuno and the first channel portion of the FeFET and a scavenging material being present in the lower electrode layer as these modifications further minimize the effective oxide thickness of the crystalline ferroelectric dielectric.
Regarding Claim 2, Okuno as modified by Ando teaches the semiconductor structure of Claim 1, wherein the crystalline ferroelectric dielectric comprises crystalline hafnium oxide (Okuno describes the ferroelectric film being “a ferroelectric material composed of HfO2” that is “crystallized by a process flow”).
Regarding Claim 3, Okuno as modified by Ando teaches the semiconductor structure of Claim 1. Okuno further teaches that the crystalline ferroelectric dielectric is “preferably doped” with an element such as “Zr, Si, La, Nb, Al, or the like.”
Ando teaches that the crystalline ferroelectric dielectric is optionally doped.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement the hafnium oxide ferroelectric crystalline dielectric to be undoped as a matter of design choice as this would further influence a threshold voltage of the semiconductor structure (see further Ando: [0020], MPEP 2144.04 and In re Dailey, 357 F.2d 669, 149 USPQ 47).
Regarding Claim 4, Okuno as modified by Ando teaches the semiconductor structure of Claim 1, wherein the crystalline ferroelectric dielectric further comprises one or more doping elements (Okuno further teaches that the crystalline ferroelectric dielectric is “preferably doped” with an element such as “Zr, Si, La, Nb, Al, or the like.”)
Regarding Claim 5, Okuno as modified by Ando teaches the semiconductor structure of Claim 4, wherein the doping elements comprise Zr, Al, Ca, Ce, Dy, Er, Gd, Ge, La, N, Sc, Si, Sr, Sn or Y (Okuno further teaches that the crystalline ferroelectric dielectric is “preferably doped” with an element such as “Zr, Si, La, Nb, Al, or the like.”)
Regarding Claim 6, Okuno as modified by Ando teaches the semiconductor structure of Claim 1, wherein the lower electrode comprises titanium, nitrogen and an oxide of a scavenger material (as modified by Ando, see [0046-0048] which describes the lower electrode comprising a lower TiN layer 142, a scavenger metal 144 which scavenges impurity oxygen, and an upper TiN layer 146); and
wherein the scavenger material is one of Al, Be, Mg, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Dy, Lu, Er, Pr, Ce or mixtures thereof (see Ando: [0047]).
Regarding Claim 7, Okuno as modified by Ando teaches the semiconductor structure of Claim 6, wherein the lower electrode comprises:
a first titanium nitride layer (as modified by Ando: 142);
an oxide of a scavenger material on the first titanium nitride layer (see Ando: [0051] and [0076] which describes that the scavenger metal “captures oxygen atoms”, which is achieved through an “oxygen scavenging reaction”, thus forming an oxide of a scavenger material within the lower electrode);
and a second titanium nitride oxide of a scavenger material (see [0051]).
Regarding Claim 8, Okuno teaches a cross-bar array (shown Figs. 4-7) comprising:
a substrate (shown Fig. 2) having a first channel portion (channel region between diffusion regions 204) and a second channel portion (channel region between diffusion regions 304);
a weight storage device (20, a 1T FeRAM) on the substrate; and
a gradient accumulation device (30, a 1T1C FeRAM) the substrate;
wherein the weight storage device comprises:
a ferroelectric field effect transistor (FeFET) (shown Fig. 2) comprising:
a crystalline ferroelectric dielectric (213) on the first channel portion; and
an upper electrode (214) on the crystalline ferroelectric dielectric;
wherein the gradient accumulation device comprises:
a ferroelectric capacitor (FeCAP) (shown Fig. 2) comprising:
the crystalline ferroelectric dielectric (portion 313, formed of the same crystalline ferroelectric dielectric layer shown in Fig. 10h) on the second channel portion of the substrate;
a lower electrode (317) on the crystalline ferroelectric dielectric (shown Fig. 2); and
the upper electrode on the lower electrode (shown Fig. 2).
Okuno further teaches an interfacial oxide (102, 402) being present in Figs. 2 and 9d, but removed from the FeFET portion of the semiconductor structure in Fig. 9e. Further, Okuno does not explicitly teach the lower electrode comprising a scavenging material or being in contact with the second portion of the substrate.
Ando teaches semiconductor structure (100, shown Fig. 1) wherein an equivalent oxide thickness may be reduced by scavenging an interfacial oxide layer (see [0053] and [0003] further suggesting that this may apply to ferroelectric capacitors and ferroelectric transistors), wherein the device comprises an interfacial oxide (120) on a substrate (110), a hafnium oxide layer (130), a lower electrode (140), wherein the lower electrode comprises a scavenging material (144, see also Ando [0038]) disposed between two TiN layers (142 and 146, analogous to the material of the lower electrode of Okuno) and an upper electrode 150.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to adopt the scaled gate dielectric structure of Ando to the FeCAP and FeFET structures of Okuno as this would minimize an effective oxide thickness of the crystalline ferroelectric dielectric layer (see Ando: [0021-0022], [0059]), thus increasing device density and improving device performance (see Ando: [0002]).
Specifically, this modification would further teach an interfacial oxide being present between the crystalline ferroelectric dielectric layer of Okuno and the first channel portion of the FeFET, a scavenging material being present in the lower electrode layer of the FeCAP, and the crystalline ferroelectric dielectric layer being in contact with a second portion of the substrate as these modifications further minimize the effective oxide thickness of the crystalline ferroelectric dielectric.
Regarding Claim 9, Okuno as modified by Ando teaches the semiconductor structure of Claim 8, wherein the crystalline ferroelectric dielectric comprises crystalline hafnium oxide (Okuno describes the ferroelectric film being “a ferroelectric material composed of HfO2” that is “crystallized by a process flow”).
Regarding Claim 10, Okuno as modified by Ando teaches the semiconductor structure of Claim 8. Okuno further teaches that the crystalline ferroelectric dielectric is “preferably doped” with an element such as “Zr, Si, La, Nb, Al, or the like.”
Ando teaches that the crystalline ferroelectric dielectric is optionally doped.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement the hafnium oxide ferroelectric crystalline dielectric to be undoped as a matter of design choice as this would further influence a threshold voltage of the semiconductor structure (see further Ando: [0020], MPEP 2144.04 and In re Dailey, 357 F.2d 669, 149 USPQ 47).
Regarding Claim 11, Okuno as modified by Ando teaches the semiconductor structure of Claim 8, wherein the crystalline ferroelectric dielectric further comprises one or more doping elements (Okuno further teaches that the crystalline ferroelectric dielectric is “preferably doped” with an element such as “Zr, Si, La, Nb, Al, or the like.”)
Regarding Claim 12, Okuno as modified by Ando teaches the semiconductor structure of Claim 11, wherein the doping elements comprise Zr, Al, Ca, Ce, Dy, Er, Gd, Ge, La, N, Sc, Si, Sr, Sn or Y (Okuno further teaches that the crystalline ferroelectric dielectric is “preferably doped” with an element such as “Zr, Si, La, Nb, Al, or the like.”)
Regarding Claim 13, Okuno as modified by Ando teaches the semiconductor structure of Claim 11, wherein the lower electrode comprises titanium, nitrogen and an oxide of a scavenger material (as modified by Ando, see [0046-0048] which describes the lower electrode comprising a lower TiN layer 142, a scavenger metal 144 which scavenges impurity oxygen, and an upper TiN layer 146); and
wherein the scavenger material is one of Al, Be, Mg, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Dy, Lu, Er, Pr, Ce or mixtures thereof (see Ando: [0047]).
Regarding Claim 14, Okuno as modified by Ando teaches the semiconductor structure of Claim 13, wherein the lower electrode comprises:
a first titanium nitride layer (as modified by Ando: 142);
an oxide of a scavenger material on the first titanium nitride layer (see Ando: [0051] and [0076] which describes that the scavenger metal “captures oxygen atoms”, which is achieved through an “oxygen scavenging reaction”, thus forming an oxide of a scavenger material within the lower electrode);
and a second titanium nitride oxide of a scavenger material (see [0051]).
Regarding Claim 15, Okuno teaches a method of making a semiconductor structure (shown Fig. 2) comprising:
providing a substrate (shown Fig. 2) having a first area (10, 20) and a second area (30);
forming an oxide interfacial layer (102, 104) on the substrate;
forming a ferroelectric dielectric (213, 313) on the substrate;
annealing the substrate to form a crystallize ferroelectric dielectric in the first and the second areas (“a crystallization annealing step may be further provided after the step of forming the ferroelectric film”); and
forming an upper electrode (215 and 315, shown Fig. 2) in the first and second areas.
Okuno does not explicitly teach a scavenging material in the second area of the substrate and the anneal further being used to migrate the oxygen from the oxide interfacial layer to form an oxidized scavenger material in the second area thereby leaving the oxide interfacial layer in the first area of the substrate while removing the oxide interfacial layer in the second area of the substrate.
Ando teaches semiconductor structure (100, shown Fig. 1) wherein an equivalent oxide thickness may be reduced by scavenging an interfacial oxide layer (see [0053] and [0003] further suggesting that this may apply to ferroelectric capacitors and ferroelectric transistors), wherein the device comprises an interfacial oxide (120) on a substrate (110), a hafnium oxide layer (130), a lower electrode (140), wherein the lower electrode comprises a scavenging material (144, see also Ando [0038]) disposed between two TiN layers (142 and 146, analogous to the material of the lower electrode of Okuno) and an upper electrode 150, and wherein a “common annealing phase involves scavenging of the interfacial layer and crystallization into a ferroelectric crystalline phase of the hafnium oxide layer” (see also Ando: Claim 17).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to adopt the scaled gate dielectric structure of Ando to the FeCAP and FeFET structures of Okuno as this would minimize an effective oxide thickness of the crystalline ferroelectric dielectric layer (see Ando: [0021-0022], [0059]), thus increasing device density and improving device performance (see Ando: [0002]).
Specifically, this modification would further teach forming a scavenger material in the second area of the substrate (corresponding to a FeCAP region of Okuno) and the anneal step of Okuno further being used to migrate oxygen from an oxide interfacial layer in the second area of the substrate to form an oxidized scavenger material in the second area while removing the oxide interfacial layer in the second area of the substrate (removing a potion corresponding to the capacitor C in region 30 of Okuno), thereby leaving the oxide interfacial layer in the first area of the substrate (portion 102 in the first area of Okuno remaining).
Regarding Claim 16, Okuna as modified by Ando teaches the method of Claim 15, further comprising:
wherein forming the scavenger material comprises forming a tri-layer of titanium nitride/the scavenger material/titanium nitride (see Ando: 142, 144 and 146) on the ferroelectric dielectric in the second area of the substrate (as modified by Ando, see Fig. 1);
forming a blanket titanium nitride layer (See Okuno, Fig. 10h which shows layer 553) over the first and second areas of the substrate;
wherein the upper electrode is formed on the blanket titanium nitride layer (shown Fig. 10h);
patterning (shown Figs. 8-10) to form a first gate stack (shown Okuno: Fig. 2) on the substrate in the first area and a second gate stack (shown Fig. 2) on the substrate in the second area;
wherein the first gate stack comprises the oxide interfacial layer (as modified by Ando), ferroelectric dielectric (213), the blanket titanium nitride layer (remaining portion 214) and the upper electrode (shown Fig. 2); and
wherein the second gate stack comprises the oxide interfacial layer (as modified by Ando), the ferroelectric dielectric (313), the tri-layer (as modified by Ando, see stack of Fig. 1), the blanket titanium nitride layer and the upper electrode (see Figs. 2 and 10h of Okuno);
forming spacers (205, shown Okuno: Fig. 2) on either side of the first and second gate stacks;
forming source drain regions (204, 304, shown Okuno: Fig. 2) in the substrate on either side of the first and second gate stacks;
wherein after annealing, the second gate stack comprises the crystallized ferroelectric dielectric (313), the final tri-layer of titanium nitride/the oxidized scavenger material/titanium nitride (as modified by Ando, see also [0051]), the blanket titanium nitride layer (remaining portion 314 of Okuno) and the upper electrode (315).
Regarding Claim 17, Okuna as modified by Ando teaches the method of Claim 16, wherein an annealing temperature is greater than 600 C (see as modified by Ando: [0056]).
Regarding Claim 18, Okuna as modified by Ando teaches the method of Claim 15, further comprising:
forming a dummy gate (shown Fig. 8a) having spacers in each of the first and second areas of the substrate (shown Fig. 8a);
removing the dummy gate in each of the first and the second areas (shown Fig. 9e) to form a gate opening between the spacers which exposes a substrate surface (shown Fig. 9e);
wherein the oxide interfacial layer is formed on the substrate surface in the first and second areas of the substrate (as modified by Ando);
wherein the scavenger material is a metal doped titanium nitride layer (see as modified by Ando: [0052]);
forming an undoped titanium nitride layer (541, shown Fig. 9f) in the gate opening of the first area of the substrate;
wherein after annealing, the oxide interfacial layer on the substrate surface in the first area of the substrate remains while the oxide interfacial layer on the substrate surface in the second area of the substrate is removed (as modified by Ando); and
forming a workfunction material (553) and an upper electrode (554) in the gate opening of the first and the second areas of the substrate (shown Okuno: Fig. 10h).
Regarding Claim 19, Okuna as modified by Ando teaches the method of Claim 18, where an annealing temperature is between 300 C – 600 C (see Okuno which describes at least the ferroelectric crystallization annealing being done between 400-600 degrees and Ando: [0055] which further states that temperatures as low as 400° C. to 600° C. will facilitate effective IL scavenging).
Regarding Claim 20, Okuno as modified by Ando teaches the method of Claim 18.
Ando further teaches implementing a gate replacement process (shown Fig. 2, see steps 201, 202, 204, 205 and 207 and [0056]) which comprises:
prior to annealing, forming a dummy fill material (290) in a gate opening of the semiconductor structure; and
after annealing, removing the dummy fill material (shown step 204), the titanium nitride layer and the oxidized scavenger material (layer 260, see [0064]) to expose the crystallized ferroelectric dielectric in the gate opening;
wherein an annealing temperature is greater than 600 C (see Ando: [0056]).
Ando as applied to Okuno would further teach a dummy fill material being in gate openings of the first and second areas of the substrate and exposing the crystallized ferroelectric dielectric in the gate openings of the first and second areas of the substrate, and the annealing temperature being greater than 600° C when a first process flow described in paragraph [0056] of Ando is implemented.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Müller (US 20190130957 A1) teaches a device (200, shown Fig. 2H) which may be adapted to comprise FeFET stacks (see [0082] or FeCAPs (see [0123]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.P.B./ Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights