DETAILED ACTION
This office action is in response to the application filed on 5/30/24.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Inventorship
This application currently names joint inventors. In considering patentability of the claims under 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of 35 U.S.C. 103(c) and potential 35 U.S.C. 102(e), (f) or (g) prior art under 35 U.S.C. 103(a).
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1-10 and 17-20 are objected to because of the following informalities:
In regards to claim 1, it appears that “the slew rate” should be “a slew rate”.
In regards to claim 17, it appears that “the slew rate of the first transistor” should be “a slew rate of the first transistor”.
In regards to claim 17, it appears that “the slew rate of the second transistor” should be “a slew rate of the second transistor”.
Claims 2-10 and 18-20 are objected to, based on its dependency of an objected to claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsukiji et al. (US20120286752, hereinafter Tsukiji).
Regarding Claim 1, Tsukiji discloses an apparatus (fig. 2, 3), comprising: a first transistor (M1) having a control input (Vg to M1 gate); and a driver (20, 30) having an output coupled to the control input (Vg), the driver including an adaptive slew rate control circuit (30, 20) having an input coupled to a first terminal (ADJ), the adaptive slew rate control circuit configured to control the slew rate of the first transistor based on a resistor coupled to the first terminal (Radj, ¶86).
Regarding Claim 2, Tsukiji discloses (fig. 2, 3) the adaptive slew rate control circuit includes a bandgap voltage reference circuit (34), and the adaptive slew rate control circuit is configured to control the slew rate based on the resistor (Radj) and a voltage produced by the bandgap voltage reference circuit (Vbgr).
Claim 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Krishna (US20170012618).
Regarding Claim 17, Krishna discloses a power converter (fig. 2), comprising: a first transistor (101) having a control input (gate); a second transistor (102) coupled to the first transistor and having a control input (gate); a first driver (122a, 122b, 130, 135, 121a) having an output coupled to the control input of the first transistor (to gate), the first driver including a first adaptive slew rate control circuit (130, 122a) having an input coupled to a first terminal, the first adaptive slew rate control circuit configured to control the slew rate of the first transistor based on a first resistor coupled to the first terminal (¶19); and a second driver (122c, 122d, 130, 135, 122c) having an output coupled to the control input of the second transistor (to gate), the second driver including a second adaptive slew rate control circuit (130, 122c) having an input coupled to a second terminal, the second adaptive slew rate control circuit configured to control the slew rate of the second transistor based on a second resistor coupled to the second terminal (¶19).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103(a) as being unpatentable over Krishna in view of Tsukiji.
Regarding Claim 18, Krishna discloses (fig. 2) the first adaptive slew rate control circuit (130, 122a) and the second adaptive slew rate control circuit (130, 122c).
Krishna does not disclose the first adaptive slew rate control circuit includes a first bandgap voltage reference circuit, and the first adaptive slew rate control circuit is configured to control the slew rate of the first transistor based on the first resistor and a voltage produced by the first bandgap voltage reference circuit; and the second adaptive slew rate control circuit includes a second bandgap voltage reference circuit, and the second adaptive slew rate control circuit is configured to control the slew rate of the second transistor based on the second resistor and a voltage produced by the second bandgap voltage reference circuit.
Tsukiji discloses (fig. 2, 3) a first adaptive slew rate control circuit (30, 20) which includes a first bandgap voltage reference circuit (34), and the first adaptive slew rate control circuit is configured to control the slew rate of the first transistor based on the first resistor (Radj)and a voltage produced by the first bandgap voltage reference circuit (Vbgr)(¶86).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Krishna to include the adaptive slew rate control structure as disclosed in Tsukiji to provide stable slew rate control thus meeting design and efficiency demands.
Allowable Subject Matter
Claims 11-16 are allowed.
Claims 3-10, 19 and 20 would be allowable if rewritten or amended to overcome the objection(s) set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art fails to disclose: “...the driver includes an array of first transistors coupled in parallel and to the control input, and the adaptive slew rate control circuit includes a corresponding number of second transistors coupled in parallel.” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 10, the prior art fails to disclose: “...the adaptive slew rate control circuit is a first adaptive slew rate control circuit having outputs, and the driver includes: an array of first transistors coupled in parallel and to the control input, each of the first transistors having a control input coupled to a corresponding output of the first adaptive slew rate control circuit; a second adaptive slew rate control circuit having outputs; and an array of second transistors coupled in parallel and to the control input, each of the second transistors having a control input coupled to a corresponding output of the second adaptive slew rate control circuit.” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 11, the prior art fails to disclose: “...transistors having control inputs, first terminals, and second terminals, the first terminals coupled together and the second terminals coupled together; a bandgap voltage reference circuit having a first voltage terminal coupled to the first terminals and having a second voltage terminal; a comparator having a first comparator input, a second comparator input, and a comparator output, the first comparator input coupled to the second voltage terminal, and the second comparator input coupled to the second terminals; a current source circuit coupled to the second terminals; and a logic circuit having an input coupled to the comparator output and having outputs coupled to respective control inputs of the transistors.” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 19, the prior art fails to disclose: “...the first adaptive slew rate control circuit includes: a first array of transistors having first terminals coupled together and to the second bandgap voltage reference circuit and having second terminals coupled together; and a first comparator having a first comparator input coupled to the first bandgap voltage reference circuit and having a second comparator input coupled to the second terminals of the first array of transistors; and the second adaptive slew rate control circuit includes: a second array of transistors having first terminals coupled together and to the second bandgap voltage reference circuit and having second terminals coupled together; and a second comparator having a first comparator input coupled to the second bandgap voltage reference circuit and having a second comparator input coupled to the second terminals of the second array of transistors.” in combination with the additionally claimed features, as are claimed by the Applicant.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 11876450, Ueno; Takeshi discloses an electronic circuit for supplying current to switching device and electronic apparatus.
US 12028073, Nishimura; Naoaki discloses a Driver controlling slew rate and switching of a switching output stage.
US 9553510, Tsukiji; Nobukazu et al. discloses a Switching regulator control circuit, switching regulator, electronic appliance, switching power supply device, and television receiver.
US 9614517, Krishna; Kannan discloses an adaptive slew rate control for switching power devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE J MOODY whose telephone number is (571)272-5242. The examiner can normally be reached on M-F 10 AM - 4 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KYLE J MOODY/
Primary Examiner, Art Unit 2838
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