DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Feng et al (US Patent No. 9380688).
Regarding claim 1, Feng discloses an electrical overstress (EOS) monitor or protection device (i.e., such as ESD system 500; see for example fig. 5, Col. 10 lines 18+) comprising: a substrate (i.e., such as a lower substrate 504, an upper substrate 502; see for example fig. 5, Col. 10 lines 18+) having a horizontal main surface (i.e., such as B-axis of underfill layer 516; see for example fig. 5, Col. 10 lines 18+); and a first conductive layer (i.e., such as a plurality of upper metallic tips 506A, 506B; see for example fig. 5, Col. 10 lines 18+) and a second conductive layer (i.e., such as a plurality of lower metallic tips 507A, 507B; see for example fig. 5, Col. 10 lines 18+) each extending over (i.e., such as each of the plurality of upper metallic tips 506A, 506B also includes a first body that extends downward from the inner ceiling surface and a first point, and the plurality of lower metallic tips 507A, 507B also include a second body that extends upward from the inner floor surface and a second point; see for example fig. 5, Col. 10 lines 18+) the substrate (i.e., such as a lower substrate 504, an upper substrate 502; see for example fig. 5, Col. 10 lines 18+) and substantially parallel (i.e., such as B-axis is substantially parallel to upper substrate 502 and lower substrate 504; see for example fig. 5, Col. 10 lines 18+) to the horizontal main surface (i.e., such as B-axis of underfill layer 516; see for example fig. 5, Col. 10 lines 18+) while being separated (i.e., such as 506 and 507 are separated vertically/A-axis to create a gap or air chamber 514; see for example fig. 5, Col. 10 lines 18+) in a vertical direction (i.e., such as the A-axis; see for example fig. 5, Col. 10 lines 18+) crossing (i.e., such as the A-axis is perpendicular on the B-axis; see for example fig. 5, Col. 10 lines 18+) the horizontal main surface (i.e., such as B-axis of underfill layer 516; see for example fig. 5, Col. 10 lines 18+), wherein one of the first (i.e., such as a plurality of upper metallic tips 506A, 506B; see for example fig. 5, Col. 10 lines 18+) and second (i.e., such as a plurality of lower metallic tips 507A, 507B; see for example fig. 5, Col. 10 lines 18+) conductive layers (i.e., such as a plurality of upper metallic tips 506A, 506B; see for example fig. 5, Col. 10 lines 18+) (i.e., such as a plurality of lower metallic tips 507A, 507B; see for example fig. 5, Col. 10 lines 18+) is electrically connected (i.e., such as the conductive connection can also include a metallic pillar 512A that extends through the underfill layer 516 providing a conductive path between the upper substrate 502 and the lower substrate 504. A similar conductive connection and metallic pillar 512A connection arrangement can be provided for each of the plurality of upper and lower metallic tips 506A, 506B, 507A, 507B; see for example fig. 5, Col. 10 lines 18+) to a first voltage node (i.e., such as the lower structure of the upper substrate 502; see for example fig. 5, Col. 10 lines 18+) and the other of the first (i.e., such as a plurality of upper metallic tips 506A, 506B; see for example fig. 5, Col. 10 lines 18+) and second (i.e., such as a plurality of lower metallic tips 507A, 507B; see for example fig. 5, Col. 10 lines 18+) conductive layers (i.e., such as a plurality of upper metallic tips 506A, 506B; see for example fig. 5, Col. 10 lines 18+) (i.e., such as a plurality of lower metallic tips 507A, 507B; see for example fig. 5, Col. 10 lines 18+) is electrically connected (i.e., such as the conductive connection can also include a metallic pillar 512A that extends through the underfill layer 516 providing a conductive path between the upper substrate 502 and the lower substrate 504. A similar conductive connection and metallic pillar 512A connection arrangement can be provided for each of the plurality of upper and lower metallic tips 506A, 506B, 507A, 507B; see for example fig. 5, Col. 10 lines 18+) to a second voltage node (i.e., such as the upper structure of the lower substrate 504; see for example fig. 5, Col. 10 lines 18+), and wherein the first conductive layer (i.e., such as a plurality of upper metallic tips 506A, 506B; see for example fig. 5, Col. 10 lines 18+) and the second conductive layer (i.e., such as a plurality of lower metallic tips 507A, 507B; see for example fig. 5, Col. 10 lines 18+) serve (i.e., such as discharging arcs; see for example fig. 5, Col. 10 lines 18+) as one or more arcing electrode pairs (i.e., such as arcing tips in the air chambers 514A, 514B; see for example fig. 5, Col. 10 lines 18+) and have overlapping portions (i.e., such as the air gap metal tip structures have overlapping portions of two upper metallic tips 506A, 506B and two lower metallic tips 507A, 507B; see for example fig. 5, Col. 10 lines 18+) configured to generate one or more arc discharges (i.e., such as the air gap metal tip structure is configured such that it can handle and guide an arc caused by and ESD event from an upper tip to a lower tip through an air chamber that houses both tips; see for example fig. 5, Col. 10 lines 18+) extending generally (i.e., such as each of the plurality of upper metallic tips 506A, 506B also includes a first body that extends downward from the inner ceiling surface and a first point, and the plurality of lower metallic tips 507A, 507B also include a second body that extends upward from the inner floor surface and a second point; see for example fig. 5, Col. 10 lines 18+) in the vertical direction (i.e., such as the A-axis; see for example fig. 5, Col. 10 lines 18+) (i.e., such as 506 and 507 are separated vertically/A-axis to create a gap or air chamber 514; see for example fig. 5, Col. 10 lines 18+) in response to (i.e., such as to handle and guide the generated arc to the ground; see for example fig. 5, Col. 10 lines 18+) an EOS voltage signal (i.e., such as an arc caused by an ESD/EOS event; see for example fig. 5, Col. 10 lines 18+) received between the first (i.e., such as the lower structure of the upper substrate 502; see for example fig. 5, Col. 10 lines 18+) and second (i.e., such as the upper structure of the lower substrate 504; see for example fig. 5, Col. 10 lines 18+) voltage nodes (i.e., such as the lower structure of the upper substrate 502; see for example fig. 5, Col. 10 lines 18+) (i.e., such as the upper structure of the lower substrate 504; see for example fig. 5, Col. 10 lines 18+).
Regarding claim 7, Feng discloses the EOS monitor or protection device (i.e., such as ESD system 500; see for example fig. 5, Col. 10 lines 18+); wherein one or both of the first (i.e., such as a plurality of upper metallic tips 506A, 506B; see for example fig. 5, Col. 10 lines 18+) and second (i.e., such as a plurality of lower metallic tips 507A, 507B; see for example fig. 5, Col. 10 lines 18+) conductive layers (i.e., such as a plurality of upper metallic tips 506A, 506B; see for example fig. 5, Col. 10 lines 18+) (i.e., such as a plurality of lower metallic tips 507A, 507B; see for example fig. 5, Col. 10 lines 18+) comprise a circular ring or pad (i.e., 618; such as the ESD system 600 includes a plurality of hollow cylindrical metallic pillars 618. The ESD system 600 also includes a plurality of solid cylindrical metallic pillars 612 that can serve to help provide a connection path. The ESD system 600 also includes a plurality of metallic tip clusters 606 that are attached to an upper substrate 602 as shown; see for example fig. 6B, Col. 11 lines 40+).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al (US Patent No. 9380688) in view of Leary (US Patent No. 5357397).
Regarding claim 5, Feng discloses the EOS monitor or protection device (i.e., such as ESD system 500; see for example fig. 5, Col. 10 lines 18+).
Feng does not explicitly disclose wherein first and second conductive layers are separated by an intermetal dielectric layer formed between the overlapping portions to serve as an arcing medium.
Leary discloses an ESD protection of ICs (i.e., see for example fig. 2, Col. 5 lines 11+); wherein first (i.e., such as metal layer I/204; see for example fig. 2, Col. 5 lines 11+) and second (i.e., such as metal layer I/204; see for example fig. 2, Col. 5 lines 11+) conductive layers (i.e., such as metal layer I/204; see for example fig. 2, Col. 5 lines 11+) (i.e., such as metal layer I/204; see for example fig. 2, Col. 5 lines 11+) are separated by an intermetal dielectric layer (i.e., such as intermetal dielectric layer 210; see for example fig. 2, Col. 5 lines 11+) formed between the overlapping portions (i.e., such as structured between the overlapping portions; see for example fig. 2, Col. 5 lines 11+) to serve as an arcing medium (i.e., such as arc gap, also called spark gap, structures. While a soft vacuum may enhance the discharge, it is not required, since the discharge voltage will be below the ionization voltage of any gas left in the separation area 210, thus preventing arcing; see for example fig. 2, Col. 5 lines 11+).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the dielectric layer in Feng, as taught by Leary, as it provides the advantage of optimizing the circuit design towards controlling the thermionic emission during the ESD process.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al (US Patent No. 9380688) in view of Horvath (US Patent No. 6002569).
Regarding claim 6, Feng discloses the EOS monitor or protection device (i.e., such as ESD system 500; see for example fig. 5, Col. 10 lines 18+).
Feng does not explicitly disclose wherein one or both of the first and second conductive layers comprise a rectangular ring or pad.
Horvath discloses an ESD protection apparatus (i.e., see for example fig. 3, Col. 5 lines 11+); wherein one or both of the first (i.e., such as 38; see for example fig. 3, Col. 5 lines 11+) and second (i.e., such as 40; see for example fig. 3, Col. 5 lines 11+) conductive layers (i.e., such as implemented directly on the printed circuit board (PCB) 34, and includes a copper base 36 having a generally rectangular outer perimeter 38 and a circular opening 40. The base 36 is connected to ground 24; see for example fig. 3, Col. 5 lines 11+) comprise a rectangular ring or pad (i.e., such as a rectangular ring or pad; see for example fig. 3, Col. 5 lines 11+).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the square-ring ESD device in Feng, as taught by Horvath, as it provides the advantage of optimizing the circuit design towards efficiency and robustness in discharging arcs.
Allowable Subject Matter
Claims 2-4 and 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Feng teaches the invention set forth above. However, Feng does not particularly teach further comprising a third conductive layer formed above the first and second conductive layers and configured to serve as the first voltage node electrically connected to the first conductive layer.
Hence claim 2 will be deemed allowable if rewritten in an independent form.
Claims 3-4 depend on objected claim 2, consequently claims 3-4 will also be deemed allowable.
Regarding claim 8, Feng teaches the invention set forth above. However, Feng does not particularly teach wherein one of the first and second conductive layers comprise a corner region laterally extending over and overlapped by the other of the first and second conductive layers.
Hence claim 8 will be deemed allowable if rewritten in an independent form.
Regarding claim 9, Feng teaches the invention set forth above. However, Feng does not particularly teach wherein one of the first and second conductive layers comprise a rectangular region laterally extending over and overlapped by the other of the first and second conductive layers.
Hence claim 9 will be deemed allowable if rewritten in an independent form.
Claims 10-18 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 10, Feng et al (US Patent No. 9380688) substantially teaches the claim limitations as indicated in claim 1. However, Feng does not or suggest an electrical overstress (EOS) monitor or protection device comprising: a substrate having a horizontal main surface; a first conductive layer and a second conductive layer each extending over the substrate and laterally overlapping each other while being separated in a vertical direction crossing the horizontal main surface by an intermetal dielectric formed therebetween; and a third conductive layer formed above the first and second conductive layers and electrically connected to the first conductive layer by one or more conductive vias, wherein an EOS voltage between the third conductive layer and the second conductive layer generates an arc discharge extending generally in the vertical direction between overlapping portions of the first and second conductive layers.
Claims 11-14 are allowed, as they depend on allowed claim 10.
Regarding claim 15, Feng et al (US Patent No. 9380688) substantially teaches the claim limitations as indicated in claim 1. However, Feng does not or suggest an electrical overstress (EOS) monitor or protection device comprising: a substrate having a horizontal main surface; a first conductive layer and a second conductive layer each extending over the substrate and laterally overlapping each other while being separated in a vertical direction crossing the horizontal main surface by an intermetal dielectric formed therebetween; and a third conductive layer formed above the first and second conductive layers and configured to receive an EOS voltage signal relative to an electrical ground, wherein the first conductive layer is electrically connected to the third conductive layer and the second conductive layer is electrically connected to the electrical ground such that the EOS voltage signal causes arcing between the first and second conductive layers generally in the vertical direction between overlapping portions of the first and second conductive layers.
Claims 16-18 are allowed, as they depend on allowed claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700.
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838