DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-16 are pending for examination.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-16 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Claim 1 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1, Statutory Category: Yes, the claim 1 is a thread allocation method that recites a series of steps and therefore falls in the statutory category of a process.
Step 2A- Prong 1: Judicial Exception Recited: Yes, the claim recites: “generating a plurality of thread groups based on a number of active processing cores among a plurality of processing cores; determining a number of threads to be allocated to each thread group among a plurality of threads based on a computation capacity per each thread of the plurality of thread groups; allocating at least one thread to the respective thread groups based on a priority of each threads and the number of threads to be allocated to each thread group; and allocating each thread group to each active processing core” As drafted, the claim as a whole recites a method including steps that could be performed in the human mind, but for the recitation of generic computing components. The human mind can easily creating/generating/establishing a plurality of thread groups based on a number of active processing cores among a plurality of processing cores included in a computing device, evaluating/determining a number of threads to be allocated to each thread group among a plurality of threads to be executed in a current period based on a computation capacity per each thread of the plurality of thread groups, allocating/assigning at least one thread to the respective thread groups based on a priority of each threads and the number of threads to be allocated to each thread group; and allocating/assigning each thread group to each active processing core. Therefore, but for the recitation of generic computing components, these steps may be a Mental Processes that can be performed in the human mind (including an observation, evaluation, judgment, opinion).
Therefore, yes, the claims do recite judicial exceptions.
Step 2A- Prong 2: Integrated into a practical Application: No, this judicial exception is not integrated into a practical application. In particular, the claim recites an additional limitations that “a plurality of processing cores included in a computing device”, “thread group among a plurality of threads to be executed in a current period” which is directed to adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a generic computer as a tool to perform an abstract idea (see MPEP 2106.05(f)). Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they not impose any meaningful limits on practicing the abstract idea. Therefore, the claim is directed to the abstract idea.
Step 2B: Claim provides an Inventive Concept: No. The additional element “a plurality of processing cores included in a computing device”, “thread group among a plurality of threads to be executed in a current period” which is directed to adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a generic computer as a tool to perform an abstract idea (see MPEP 2106.05(f)). These additional elements and combination of the elements does not amount to significant more than the exception itself or provide an inventive concept in Step 2B.
For these reasons, there is no inventive concept in the claim, and thus the claim is ineligible.
Independent claims 11 and 16 are rejected for the same reason as claim 1 above. Claim 11 further recites “A thread allocation device comprising: a memory storing one or more instructions; and a processor executing the one or more instructions stored in the memory, wherein the instructions, when executed by the processor, cause the processor to”. Claim 16 further recites “A non-transitory computer readable storage medium storing computer executable instructions, wherein the instructions, when executed by a processor, cause the processor to perform a thread allocation method, the method comprising”. These additional elements are directed to generic computing components/functions merely applying the abstract idea (MPEP § 2106.05(f)).
With respect to the dependent claims 3, the claim 2 elaborates that wherein the determining of the number of threads includes: initializing the number of threads to be allocated to each of thread group, and increasing the number of threads to be allocated to each thread group in order of the computation capacity per each thread order being larger. The claim 3 elaborates that wherein the increasing of the number of threads is repeated until all threads are allocated to the respective thread groups. (“initializing the number of threads to be allocated”, “increasing the number of threads to be allocated” and “increasing” are being treated as part of abstract idea and is analogous to Mental processes, such that concept can be performed in the human mind. Further, the claim as a whole is a Mental Processes that can be performed in the human mind (including an observation, evaluation, judgment, opinion)).
With respect to the dependent claims 4-6, the claim 4 elaborates that wherein the allocating of at least one thread includes: calculating the computation capacity per each thread on the basis of the number of threads to be allocated to each thread group, sorting the plurality of thread groups based on the computation capacity per each thread, and allocating the at least one thread to each of the respective thread groups according to the sorted order. The claim 5 elaborates that wherein the allocating of the at least one thread includes determining a priority for each thread based on the at least one of a computing resource previously assigned to each thread and a thread ID. The claim 6 elaborates that wherein the priority is determined higher as the number of resources previously assigned decreases, and is determined higher as the value of the thread ID decreases. (“calculating” and “sorting”, “allocating”, “determining a priority” and “priority is determined higher as the number of resources previously assigned decreases, and is determined higher as the value of the thread ID decreases” are being treated as part of abstract idea and is analogous to Mental processes, such that concept can be performed in the human mind. Further, the claim as a whole is a Mental Processes that can be performed in the human mind (including an observation, evaluation, judgment, opinion)).
With respect to the dependent claims 7-8, the claim 7 elaborates that wherein the allocating of each thread group includes: selecting a thread group having the largest computation capacity per each thread among at least one unallocated thread group, calculating a migration cost of the selected thread group for each unallocated active processing core based on a processing core allocation record of at least one thread included in the selected thread group, and allocating the selected thread group to an active processing core having the lowest calculated migration cost. The claim 8 elaborates wherein the calculating of the migration cost includes calculating the migration cost based on a first cost for migration between different processors and a second cost for migration between different processing cores, and wherein a weight of the first cost is set greater than a weight of the second cost (“selecting”, “calculating”, “allocating” and “calculating the migration cost” are being treated as part of abstract idea and is analogous to Mental processes, such that concept can be performed in the human mind. Further, the claim as a whole is a Mental Processes that can be performed in the human mind (including an observation, evaluation, judgment, opinion)).
With respect to the dependent claims 9-10, the claim 9 elaborates that setting a scheduling period such that each thread group is allocated to each active processing core. The claim 10 elaborates that wherein the setting of the scheduling period includes: obtaining performance data for the plurality of threads, and adjusting the scheduling period on the basis of the performance data (“setting a scheduling period” and “adjusting the scheduling period” are being treated as part of abstract idea and is analogous to Mental processes, such that concept can be performed in the human mind. In addition, “obtaining performance data” which is insignificant pre-solution data gathering (see MPEP § 2106.05(g))) which are well understood, routine, conventional activity (see MPEP § 2106.05(d)). Courts have identified “receiving and transmitting data, storing and retrieving information”, et cetera as well understood, routine, conventional and mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f))).
Dependent claims 12, 13, 14 and 15 recite the same features as applied to claims 2, 4, 7 and 9 respectively above, therefore they are also rejected under the same rationale.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7-8 and 14 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
As per claim 7 and 14 (line# refers to claim 7)
In line 2, “the largest computation capacity” lacks antecedence basis.
As per claim 8:
It is a thread allocation method claim that depend from rejected claim and do not resolve the deficiencies thereof and are therefore rejected for the same reasons as above.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (US Pub. 2024/0152395 A1) in view of KANG et al. (US Pub. 2018/0046512 A1)
KANG was cited in the IDS filed on 01/08/2026.
As per claim 1, Zhu teaches the invention substantially as claimed including A thread allocation method comprising (Zhu, Abstract, lines 1-7, A resource scheduling method, applied to the field of high-performance computing, including: obtaining a binding relationship between a process group and a processor, where the binding relationship indicates a binding relationship between at least one slave thread of a first process group in at least one process group and a plurality of processor cores in the processor):
generating a plurality of thread groups based on active processing cores among a plurality of processing cores included in a computing device (Zhu, Fig. 4, process 1 and process 2 (as thread groups), processor cores; Fig. 7, 700 computing node; [0013] establish the first process group. If the first condition includes: the process configurations are the same, when the resource scheduling apparatus establishes a binding relationship between the first process group and the processor core, a quantity of the selected processor cores is the same as the process configurations of the first process and the second process in the first process group, so that each selected processor core is responsible for running a slave thread of one first process and a slave thread of one second process, the utilization of each processor core can be improved; [0062] a process in which the resource scheduling apparatus 123 establishes the first process group may be: selecting a first process and a second process whose process configurations meet a first condition to establish the first process group, where the first condition includes: the process configurations are the same or a difference between the process configurations is less than a first threshold, the process configuration may be a quantity of threads included in the process, and the difference between the process configurations may be a difference between quantities of threads included in the first process and the second process. The first threshold may be an empirical value or a statistical value determined based on statistical data, or may be set based on a relationship between a process and a thread, to ensure that a quantity of process groups and a quantity of threads in each process group are more balanced, or a quantity of threads in the process group is determined with reference to a computing capacity of a processor core to which the process group is to be bound);
determining a number of threads to be allocated to each thread group among a plurality of threads to be executed in a current period based on a computation capacity per each thread of the plurality of thread groups (Zhu, [0062] a process in which the resource scheduling apparatus 123 establishes the first process group may be: selecting a first process and a second process whose process configurations meet a first condition to establish the first process group, where the first condition includes: the process configurations are the same or a difference between the process configurations is less than a first threshold, the process configuration may be a quantity of threads included in the process, and the difference between the process configurations may be a difference between quantities of threads included in the first process and the second process. The first threshold may be an empirical value or a statistical value determined based on statistical data, or may be set based on a relationship between a process and a thread, to ensure that a quantity of process groups and a quantity of threads in each process group are more balanced, or a quantity of threads in the process group is determined with reference to a computing capacity of a processor core to which the process group is to be bound; [0083] first processor core is executing one slave thread of the slave threads that have the binding relationship);
allocating at least one thread to the respective thread groups based on the number of threads to be allocated to each thread group (Zhu, Fig. 4, threads are allocated within each processes 1 and 2; [0062] a process in which the resource scheduling apparatus 123 establishes the first process group may be: selecting a first process and a second process whose process configurations meet a first condition to establish the first process group, where the first condition includes: the process configurations are the same or a difference between the process configurations is less than a first threshold, the process configuration may be a quantity of threads included in the process, and the difference between the process configurations may be a difference between quantities of threads included in the first process and the second process. The first threshold may be an empirical value or a statistical value determined based on statistical data, or may be set based on a relationship between a process and a thread, to ensure that a quantity of process groups and a quantity of threads in each process group are more balanced, or a quantity of threads in the process group is determined with reference to a computing capacity of a processor core to which the process group is to be bound); and
allocating each thread group to each active processing core (Zhu, Fig. 4, binding relationship between each thread group to each processing cores (i.e., the processing core that is selected as active processing core); [0068] The binding relationship indicates a binding relationship between at least one slave thread of the first process group in the at least one process group and a plurality of processor cores in the processor. The second rule is used to establish the binding relationship between the slave thread and the processor core. For example, the binding relationship is established according to a time division multiplexing policy. The time division multiplexing policy indicates that which slave processes in the first process group can use a same processor core in the processor in a time division multiplexing manner. Similar to the first rule, the second rule may also be a rule pre-configured based on a service requirement or a user requirement. It can be learned from the foregoing description of the process and the thread that slave threads belonging to a same process need to simultaneously perform processing tasks at a same moment, and slave threads belonging to different processes do not need to simultaneously perform the processing tasks at the same moment; [0073] the resource scheduling apparatus 123 may select, from the plurality of processor cores in the processor based on a quantity of slave threads selected from the first process group, a processor core whose computing capacity matches the quantity of the selected slave threads as the first processor core).
Zhu fails to explicitly teach when generating a plurality of thread groups, it is based on a number of active processing cores, and when allocating at least one thread to the respective thread groups, it is based on a priority of each threads.
However, KANG teaches when generating a plurality of thread groups, it is based on a number of active processing cores (KANG, [0039] A task 411 is associated with one thread group 422 selected from the thread pool 420 that is scheduled to be performed by a specific CPU core 431. The size of thread group 422 can be one. In that case, only one thread 421 can run in each core 431. The single-sized thread group 422 and the association with the single-sized thread group 422 to a single CPU core 431 can minimize CPU contention; [0040] Tasks: Thread Group=s:1; [0041] Thread Group: CPU Group=1:1; [0061] computing a number of CPU cores allocated for the I/O tasks and the compute tasks; and adjusting a number of the thread groups and affinity of the thread groups to the CPU groups based on the number of CPU cores allocated for the I/O tasks and the compute tasks); and
when allocating at least one thread to the respective thread groups, it is based on a priority of each threads (KANG, [0056] The present disclosure describes a dynamic mapping scheme that can dynamically balance CPU resources between I/O tasks and compute tasks in a data processing system based on the current system resource usage. The present dynamic mapping can adjust the mapping between physical CPU cores and threads, adjust the mappings between application tasks and threads. The present dynamic mapping scheme can adjust the priority of the background I/O threads and tune the number of threads for each different type of tasks for better data processing throughput. The present dynamic mapping scheme for mapping tasks to thread groups and thread groups to CPU groups can be applied to any server applications where there are multiple concurrent tasks with different priorities or dependencies such as I/O and computation; also see [0034] The CPU scheduler in a host OS can prioritize threads based on a variety of parameters and conditions. For example, a priority of each thread is calculated by its own design goals, for example, maximizing fairness or throughput. When CPU contention occurs, it is difficult to identify and resolve a performance bottleneck because the CPU scheduler does not know how many I/O threads would be needed to saturate the device, thus cannot control the creation or destruction of the I/O threads. As will be discussed below, the present resource management scheme can alleviate CPU contention by dynamically adjusting the number of threads and the mapping between the threads and CPU cores based on the performance characteristics of compute and I/O tasks).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Zhu with KANG because KANG’s teaching of generating the thread groups based on ratio of one to one to the processor core and mapping the thread groups to processing core based on the priority and performance characteristic would have provided Zhu’s system with the advantage and capability to allow the system to reduce CPU contention between input/output (I/O) and compute tasks that resulting in a longer latency which improving the system performance and efficiency (see KANG, [0004], [0047]).
As per claim 11, it is a thread allocation device claim of claim 1 above. Therefore, it is rejected for the same reason as claim 1 above. In addition, Zhu further teaches a memory storing one or more instructions; and a processor executing the one or more instructions stored in the memory, wherein the instructions, when executed by the processor, cause the processor to (Zhu, Claim 9, A computing node, comprising: a memory storing instructions; and at least one processor in communication with the memory, the at least one processor configured, upon execution of the instructions, to perform the following steps).
As per claim 16, it is a non-transitory computer readable storage medium claim of claim 1 above. Therefore, it is rejected for the same reason as claim 1 above.
Claims 2-3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu and KANG, as applied to claims 1 and 11 respectively above, and further in view of ZHU (US Pub. 2014/0089480 A1; hereafter ZHU’480).
As per claim 2, Zhu and KANG teach the invention according to claim 1 above. Zhu teaches wherein the determining of the number of threads includes: initializing the number of threads to be allocated to each of thread group, and increasing the number of threads to be allocated to each thread group ((Zhu, [0062] a process in which the resource scheduling apparatus 123 establishes the first process group may be: selecting a first process and a second process whose process configurations meet a first condition to establish the first process group, where the first condition includes: the process configurations are the same or a difference between the process configurations is less than a first threshold, the process configuration may be a quantity of threads included in the process, and the difference between the process configurations may be a difference between quantities of threads included in the first process and the second process. The first threshold may be an empirical value or a statistical value determined based on statistical data, or may be set based on a relationship between a process and a thread, to ensure that a quantity of process groups and a quantity of threads in each process group are more balanced, or a quantity of threads in the process group is determined with reference to a computing capacity of a processor core to which the process group is to be bound (as including increasing the number of threads to be allocated for load balancing and computing capacity)).
Zhu and KANG fail to specifically teach when increasing the number of thread to be allocated, it is in order of the computation capacity per each thread order being larger.
However, ZHU’480 teaches when increasing the number of thread to be allocated, it is in order of the computation capacity per each thread order being larger (ZHU’480, Fig. 2, 204 it has ranked order for entities from high capacity to low capacity, and it is placed into groups/bins in order to the computation capacity being larger (see right side, 0.5 is placed to second bin, then 0.4, 0.3 and 0.2); [0057] Returning to the aforementioned notion of a target server resource constraint, such a constraints can come in the form of a capacity (e.g., CPU instruction/cycle usage), which capacity is intended to be completely or partially filled by some demand for such capacity (e.g., application A demands at least X instructions per second at peak demand). Such a capacity and demand (e.g., for CPU cycles) can come on the form of a scalar value such as "85% of the processor capacity" or such as "2.3 giga-cycles per second", or can come in other forms that express a time variance such as "85% of the processor capacity during business hours and 15% of the processor capacity during off hours". Other forms of modeling time-variant aspects of capacity and demand (as well as associated constraints) are discussed in detail hereunder).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Zhu and KANG with ZHU’480 because ZHU’480’s teaching of increasing the entities to be allocated to each group in order of the computation capacity would have provided Zhu and KANG’s system with the advantage and capability to allow the system to improving the overall resource utilization in order to improving the system performance and efficiency.
As per claim 3, Zhu, KANG and ZHU’480 teach the invention according to claim 2 above. ZHU’480 further teaches wherein the increasing of the number of threads is repeated until all threads are allocated to the respective thread groups (ZHU’480, Fig. 2, 204 all of the entities are allocated to the 208 groups).
As per claim 12, it is a thread allocation device claim of claim 2 above. Therefore, it is rejected for the same reason as claim 2 above. In addition, ZHU’480 further teaches increase the number of threads to be allocated to each thread group in order of largest to smallest computation capacity per each thread (ZHU’480, Fig. 2, 204 it has ranked order for entities from high capacity to low capacity, and it is placed into groups/bins in order to the computation capacity being larger (see right side, 0.5 is placed to second bin, then 0.4, 0.3 and 0.2); [0057] Returning to the aforementioned notion of a target server resource constraint, such a constraints can come in the form of a capacity (e.g., CPU instruction/cycle usage), which capacity is intended to be completely or partially filled by some demand for such capacity (e.g., application A demands at least X instructions per second at peak demand). Such a capacity and demand (e.g., for CPU cycles) can come on the form of a scalar value such as "85% of the processor capacity" or such as "2.3 giga-cycles per second", or can come in other forms that express a time variance such as "85% of the processor capacity during business hours and 15% of the processor capacity during off hours". Other forms of modeling time-variant aspects of capacity and demand (as well as associated constraints) are discussed in detail hereunder).
Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu and KANG, as applied to claims 1 and 11 respectively above, and further in view of MENG (US Pub. 2023/0207087 A1) and ZHU (US Pub. 2014/0089480; hereafter ZHU’480).
As per claim 4, Zhu and KANG teach the invention according to claim 1 above. Zhu teaches allocating of at least one thread includes: calculating the computation capacity per each thread on the basis of the number of threads to be allocated to each thread group (ZHU, [0062] a process in which the resource scheduling apparatus 123 establishes the first process group may be: selecting a first process and a second process whose process configurations meet a first condition to establish the first process group, where the first condition includes: the process configurations are the same or a difference between the process configurations is less than a first threshold, the process configuration may be a quantity of threads included in the process, and the difference between the process configurations may be a difference between quantities of threads included in the first process and the second process. The first threshold may be an empirical value or a statistical value determined based on statistical data, or may be set based on a relationship between a process and a thread, to ensure that a quantity of process groups and a quantity of threads in each process group are more balanced, or a quantity of threads in the process group is determined with reference to a computing capacity of a processor core to which the process group is to be bound [Examiner noted: the capacity of each thread must be determined in order to ensuring the balancing of the process groups]).
Zhu and KANG fail to specifically teach sorting the plurality of thread groups based on the computation capacity per each thread, and allocating the at least one thread to each of the respective thread groups according to the sorted order.
However, MENG teaches sorting the plurality of thread groups based on the computation capacity per each thread, (MENG, [0015] information indicating whether a pharmacist group is idle and a current processing capacity value of the pharmacist group, and determining a pharmacist group to review the prescription order according to the busyness degree information comprises: determining an idle pharmacist group as the pharmacist group to review the prescription order in case that there is currently an idle pharmacist group; and determining a pharmacist group with a greatest current processing capacity value; [0052] pharmacists are grouped according to their processing capabilities: pharmacists are sorted according to their processing capabilities).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Zhu and KANG with MENG because MENG’s teaching of determining the processing capacity of each group and sorting according to processing capabilities would have provided Zhu and KANG’s system with the advantage and capability to allow the system to easily identifying the different processing capability in terms from high to low which improving the resource utilization and system performance.
Zhu, KANG and MENG fail to specifically teach allocating the at least one thread to each of the respective thread groups according to the sorted order.
However, ZHU’480 teaches allocating the at least one thread to each of the respective thread groups according to the sorted order (ZHU’480, Fig. 2, 204 it has ranked order for entities from high capacity to low capacity, and it is placed into groups/bins in order to the computation capacity being larger (see 0.8 is placed to first bin, then 0.5 is placed into second bin); [0057] Returning to the aforementioned notion of a target server resource constraint, such a constraints can come in the form of a capacity (e.g., CPU instruction/cycle usage), which capacity is intended to be completely or partially filled by some demand for such capacity (e.g., application A demands at least X instructions per second at peak demand). Such a capacity and demand (e.g., for CPU cycles) can come on the form of a scalar value such as "85% of the processor capacity" or such as "2.3 giga-cycles per second", or can come in other forms that express a time variance such as "85% of the processor capacity during business hours and 15% of the processor capacity during off hours". Other forms of modeling time-variant aspects of capacity and demand (as well as associated constraints) are discussed in detail hereunder).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Zhu, KANG and MENG with ZHU’480 because ZHU’480’s teaching of increasing the entities to be allocated to each group in order of the computation capacity would have provided Zhu, KANG and MENG’s system with the advantage and capability to allow the system to improving the overall resource utilization in order to improving the system performance and efficiency.
As per claim 13, it is a thread allocation device claim of claim 4 above. Therefore, it is rejected for the same reason as claim 4 above.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu, KANG, MENG and ZHU’480, as applied to claim 4 above, and further in view of Makljenovic et al. (US Pub. 2012/0254882 A1).
As per claim 5, Zhu, KANG, MENG and ZHU’480 teach the invention according to claim 4 above. KANG teaches wherein the allocating of the at least one thread includes determining a priority for each thread (KANG, [0056] The present disclosure describes a dynamic mapping scheme that can dynamically balance CPU resources between I/O tasks and compute tasks in a data processing system based on the current system resource usage. The present dynamic mapping can adjust the mapping between physical CPU cores and threads, adjust the mappings between application tasks and threads. The present dynamic mapping scheme can adjust the priority of the background I/O threads and tune the number of threads for each different type of tasks for better data processing throughput. The present dynamic mapping scheme for mapping tasks to thread groups and thread groups to CPU groups can be applied to any server applications where there are multiple concurrent tasks with different priorities or dependencies such as I/O and computation; also see [0034] The CPU scheduler in a host OS can prioritize threads based on a variety of parameters and conditions. For example, a priority of each thread is calculated by its own design goals, for example, maximizing fairness or throughput. When CPU contention occurs, it is difficult to identify and resolve a performance bottleneck because the CPU scheduler does not know how many I/O threads would be needed to saturate the device, thus cannot control the creation or destruction of the I/O threads. As will be discussed below, the present resource management scheme can alleviate CPU contention by dynamically adjusting the number of threads and the mapping between the threads and CPU cores based on the performance characteristics of compute and I/O tasks).
Zhu, KANG, MENG and ZHU’480 fail to specifically teach determining a priority for each thread based on the at least one of a computing resource previously assigned to each thread and a thread ID.
However, Makljenovic teaches determining a priority for each thread based on the at least one of a computing resource previously assigned to each thread and a thread ID (Makljenovic, [0057] Each pending thread may be associated with various parameters defining properties of that thread. In the example of FIG. 1, the threads are assigned a thread ID (thread) identifying the thread, a priority tag (p), and one or more resource availability flags (r). The priority tag p and resource availability flags r will be described below. Other kinds of information may also be provided for each thread; [0065] If there is a cache storage location which has been allocated to a thread with a lower priority than the thread currently within the cache requesting stage 12-0, 12-1, then data or instructions within the previously allocated storage location can be evicted and, if necessary written back to memory 30. The storage location is re-allocated to the higher priority thread currently in the cache requesting stage 12-0, 12-1, and a memory access request for the required instruction or data is then triggered to memory 30.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Zhu, KANG, MENG and ZHU’480 with Makljenovic because Makljenovic’s teaching of using the thread information which including the resources and the ID would have provided Zhu, KANG, MENG and ZHU’480’s system with the advantage and capability to allow the system to easily performing the resource re-allocation based on the determined priority of thread which improving the system performance and efficiency.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu, KANG, MENG, ZHU’480 and Makljenovic, as applied to claim 5 above, and further in view of ITO et al. (US Pub. 2021/0004255 A1) and HAN et al. (US Pub. 2014/0036704 A1).
As per claim 6, Zhu, KANG, MENG, ZHU’480 and Makljenovic teach the invention according to claim 5 above. Zhu, KANG, MENG, ZHU’480 and Makljenovic fail to specifically teach wherein the priority is determined higher as the number of resources previously assigned decreases, and is determined higher as the value of the thread ID decreases.
However, ITO teaches wherein the priority is determined higher as the number of resources previously assigned decreases (ITO, Claim 1, set a different number of VMs capable of sharing physical resources for each of the plurality of groups so that a priority group having a higher priority is set as the number of VMs capable of sharing physical resources decreases, and store priority group setting information containing a correspondence relationship between each of the priority groups and the VM operated on physical resources of the priority group, a resource use amount collecting unit, including one or more processors, configured to collect a resource use amount during operation of each of the plurality of VMs, and transmit the resource use amount collected to the controller).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Zhu, KANG, MENG, ZHU’480 and Makljenovic with ITO because ITO’s teaching of a priority group having a higher priority is set as the number of VMs capable of sharing physical resources decreases would have provided Zhu, KANG, MENG, ZHU’480 and Makljenovic’s system with the advantage and capability to allow the system to easily determining the priority based on the resources changes which improving the resource utilization and system performance (see ITO, Abstract).
Zhu, KANG, MENG, ZHU’480, Makljenovic and ITO fail to specifically teach the priority is determined higher as the value of the thread ID decreases.
However, HAN teaches the priority is determined higher as the value of the thread ID decreases (HAN, [0063] a priority of a CSI process ID decreases as the corresponding CSI process ID increases, thus a lower CSI process ID can have a higher priority. Using a second rule, the priority of the can be CSI process configured by RRC signaling).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Zhu, KANG, MENG, ZHU’480, Makljenovic and ITO with HAN because HAN’s teaching of a lower CSI process ID can have a higher priority would have provided Zhu, KANG, MENG, ZHU’480, Makljenovic and ITO’s system with the advantage and capability to allow the system to easily determining the priority associated with processes based on their ID which improving the system performance and efficiency.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu and KANG, as applied to claims 1 and 11 respectively above, and further in view of Aberg et al. (US Pub. 2024/0184631 A1) and Abrams et al. (US Pub. 2009/0164660 A1).
As per claim 7, Zhu and KANG teach the invention according to claim 1 above. Zhu and KANG fail to specifically teach wherein the allocating of each thread group includes: selecting a thread group having the largest computation capacity per each thread among at least one unallocated thread group, calculating a migration cost of the selected thread group for each unallocated active processing core based on a processing core allocation record of at least one thread included in the selected thread group, and allocating the selected thread group to an active processing core having the lowest calculated migration cost.
However, Aberg teaches wherein the allocating of each thread group includes: selecting a thread group having the largest computation capacity per each thread among at least one unallocated thread group, calculating a migration cost of the selected thread group based on at least one thread included in the selected thread group, (Aberg, Fig. 4, 430 select best ranked combination, 440, 445, 450; [0058] In some embodiments the ranking may be based on which cache is to be assigned, as possibly some caches (with clusters of processor cores) may provide different rankings based on performance criteria (such as cache access speed, cache size, number of processors and/or type of processors). The ranking for threads AB in cache C1 may thus differ from the ranking for threads AB in cache C2, i.e. R(AB, C1)=/=R(AB,C2). In such embodiments, the rankings are also determined based on which cache the thread group is in; [0060] The combination of threads that gives the best ranking (the lowest or the highest depending on what criteria is being used to determine the task relationships and the migration cost) is selected and the task to be scheduled is scheduled accordingly and any migrations that are to be done are also executed. The task relationships before the scheduling and any migrant cost(s) are noted in the database storage for future reference; [0078] As a combination may involve one or more migrations, it is determined 440 whether any migration is to be effected. If so, the migrations are performed 445 and the cost for the migration is determined and stored/updated as appropriately 450; [0098] migration cost for a thread (group)).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Zhu and KANG with Aberg because Aberg’s teaching of determining the migration cost for selected thread group would have provided Zhu and KANG’s system with the advantage and capability to allow the system to identifying the migration cost for the thread group in order to allow the system to easily determining whether to migrating the thread groups based on the cost.
Zhu, KANG and Aberg fail to specifically teach selected thread group for each unallocated active processing core based on a processing core allocation record of at least one thread, and allocating the selected thread group to an active processing core having the lowest calculated migration cost.
However, Abrams teaches selected thread group for each unallocated active processing core based on a processing core allocation record of at least one thread, and allocating the selected thread group to an active processing core having the lowest calculated migration cost (Abrams, [0019] the datacenter broker (130) matches the LPAR hosting costs and the server operating capabilities for a server providing hosting services with LPARs having particular LPAR customer requirements using an LPAR table (136) and a datacenter table (146). Each record of the LPAR table (136) associates an identifier (142) for a LPAR with a particular set of LPAR customer requirements (144) for that LPAR. Each record of the datacenter table (146) associates an identifier (148) for a datacenter, an identifier (152) for a server in the datacenter, the LPAR hosting costs (154), and the server operating capabilities (164) for the server. As mentioned above, each datacenters (104) of FIG. 1 may register with the datacenter broker (130) to advertise the operating capabilities and the hosting costs for the servers in that datacenter; [0039] the LPAR customer requirements specify customer criteria for operating the LPAR (108). As mentioned above, customer criteria may specify acceptable LPAR hosting costs and server operating capabilities for servers that support the particular LPAR. For example, LPAR customer requirements may specify that the only servers acceptable for hosting a particular LPAR is a server that provides an IBM.RTM. POWER6.TM. architecture with 16 Megabytes of RAM, provides storage space at less than $3 per Gigabyte per month, and provides at least 50 Gigibits per second (Gbit/s) of network bandwidth at less than $50 per month. LPAR's or other software components on behalf of the LPARs may register each LPAR's customer requirements with the datacenter broker (130). Customer criteria may also specify rules that narrow a list of servers down to a single server to which to migrate the LPAR (108) when more than one server is capable of providing acceptable server operating capabilities and LPAR hosting costs. For example, if more than one server is capable of providing acceptable server operating capabilities and LPAR hosting costs, then LPAR customer requirements may dictate that the server selected for migration is the server having the lowest monetary cost per hour or the server having the closest geographic proximity to the LPAR owner's location; please note: processor cores are taught by Zhu).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Zhu, KANG and Aberg with Abrams because Abrams’s teaching of migrating based on the lowest migration cost would have provided Zhu, KANG and Aberg’s system with the advantage and capability to allow the system to ensuring the cost efficiency in order to improving the resource utilization and system performance.
As per claim 14, it is a thread allocation device claim of claim 7 above. Therefore, it is rejected for the same reason as claim 7 above.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu, KANG, Aberg and Abrams, as applied to claim 7 above, and further in view of Jula et al. (US Patent. 8,635,626 B1).
As per claim 8, Zhu, KANG, Aberg and Abrams teach the invention according to claim 7 above. Zhu, KANG, Aberg and Abrams fail to specifically teach wherein the calculating of the migration cost includes calculating the migration cost based on a first cost for migration between different processors and a second cost for migration between different processing cores, and wherein a weight of the first cost is set greater than a weight of the second cost.
However, Jula teaches wherein the calculating of the migration cost includes calculating the migration cost based on a first cost for migration between different processors and a second cost for migration between different processing cores, and wherein a weight of the first cost is set greater than a weight of the second cost (Jula, Fig. 1; 104, 108 cores; Col 15, lines 45-59, Pseudocode 1 and related algorithms favor selection of the closest cores, thus avoiding selecting from farther cores. The rationale as described in detail herein in the simplified examples of FIGS. 1 and 2, is at least twofold. First, distant transfers are more expensive than closer ones (e.g., polling the remote core's private queue requires more QPI links). Second, tasks from farther cores are generally more expensive to run, e.g., bringing in the working set memory of the reallocated task and warming up the related cache may require an expensive remote transfer through QPI, as well as additional cache coherence traffic to invalidate the original (source) cache. Thus, the pseudocode and related algorithms improve data locality for load balancing processes in a multithreaded application; Col 16, lines 1-14, there may be five attempts to select cores from the same socket before an attempt to select a core located 1-hop QPI link away. Similarly, there could be five attempts to select sockets located 1-hop QPI link away before an attempt to select a socket located 2-hop QPI links away. In this example, cores located in one hierarchical level are favored five times more than cores located in the next hierarchical level. However, as described herein, this number may vary, and may be derived or determined, e.g., from latency ratios of the memory hierarchy. For example, Table 1 illustrates some potential memory latencies for various memory level hierarchies, expressed in numbers of processing cycles; Col 16, lines 32-55, With 8 cores per sockets, this modified version of selection order assumes that selecting closer cores is 8 times more beneficial selecting farther cores. This number is provided merely as an example, with the understanding that this number can be set for each machine based on the relevant memory hierarchy latencies. For example, the latencies for six memory levels, L1, L2, L3, local memory, 1-hop memory, and 2-hop memory, for the 8-core Nehalem EX Intel processor are shown above in Table 1. As may be observed, the cost for cores located on the same processor is 40 cycles if data is present in cache, while accessing cores at 2-hop links away takes 300 cycles or 7.5 times slower. Assuming a latency of 70 cycles for cores located on the same socket with a 50% chance that data is in L3 and 50% chance that it is in memory, then checking local cores is two times faster than checking cores on 1-hop sockets, which in turn is two times faster than checking 1-hop sockets. Taking only the selection costs as such into consideration and ignoring the thread migration costs, the example illustrates that it is beneficial to inspect two closer cores before inspecting a farther one. In this case, the stealing order for core 0 in a three socket configuration might be: 1, 2, 8, 3, 4, 9, 5, 6, 17, 7, 8, 10, 1, 2, 11, 3, 4, 18, and so on. In this example the latency ratios are 2:2:2, but this can be adapted for each machine architecture).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Zhu, KANG, Aberg, Abrams with Jula because Jula’s teaching of determining the migration cost between cores within the same socket and cores with different socket would have provided Zhu, KANG, Aberg, Abrams’s system with the advantage and capability to allow the system to ensuring the lowest migration cost can be selected based on the latency between same socket (as between different cores) and different socket (as between different processors) in order to improving the system performance and resource utilization.
Claims 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu and KANG, as applied to claims 1 and 11 respectively above, and further in view of Suzuki (US Pub. 2015/0082314 A1).
As per claim 9, Zhu and KANG teach the invention according to claim 1 above. Zhu and KANG fail to specifically teach setting a scheduling period such that each thread group is allocated to each active processing core.
However, Suzuki teaches setting a scheduling period such that each thread group is allocated to each active processing core (Suzuki, [0028] performing first task placement processing for detecting a scheduling foreseeable period within which the scheduling of the tasks on the at least a processor core after a start of execution of the task set is foreseeable in advance, and determining a core allocation in view of scheduling based on the task-set parameters with respect to each of at least a first task which is among the tasks included in the task set and which becomes ready for execution within the scheduling foreseeable period).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Zhu and KANG with Suzuki because Suzuki’s teaching of detecting a scheduling foreseeable period for core allocation with task set would have provided Zhu and KANG’s system with the advantage and capability to allow the system to easily scheduling and executing the task set based on the scheduling period in order to improving the processing efficiency and performance.
As per claim 15, it is a thread allocation device claim of claim 9 above. Therefore, it is rejected for the same reason as claim 9 above.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu, KANG and Suzuki, as applied to claim 9 above, and further in view of CAPANO et al. (US Pub. 2025/0348399 A1).
As per claim 10, Zhu, KANG and Suzuki teach the invention according to claim 9 above. Zhu, KANG and Suzuki fail to specifically teach wherein the setting of the scheduling period includes: obtaining performance data for the plurality of threads, and adjusting the scheduling period on the basis of the performance data.
However, CAPANO teaches wherein the setting of the scheduling period includes: obtaining performance data for the plurality of threads, and adjusting the scheduling period on the basis of the performance data (CAPANO, [0223] The system identifies anomalous usage during off-hours and responds by modifying the execution time of batch jobs or scheduled tasks, shifting them to a non-peak window).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Zhu, KANG and Suzuki with CAPANO because CAPANO’s teaching of shifting the execution time to non-peak window would have provided Zhu, KANG and Suzuki’s system with the advantage and capability to allow the system to identifying a non-peak time for executing the tasks based on the obtained usage which improving the resource utilization and preventing performance degradation (see CAPANO [0220]).
Conclusion
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/ZUJIA XU/Examiner, Art Unit 2195
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