DETAILED ACTION
Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Examiner’s Notes
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Specification
The use of the term BLUETOOTH, which is a trade name or a mark used in commerce, has been noted in this application. The term should be accompanied by the generic terminology; furthermore the term should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “primary” in claims 8 and 17 is a relative term which render the claims indefinite. The term “primary” is not defined by the claims, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. More specifically, neither the claims nor the specification describe particular types and/or characteristics of computing resources in order to determine if a given computing resource is a “primary” resource or a secondary/optional resource for a computing system.
For the following analysis, the Examiner will consider any computing resource that is used during a “memory dump process” as being a “primary” resource.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gerphagnon (US 2024/0037014 A1; from IDS filed on 07/08/2025; hereinafter “Gerphagnon”) in view of Roberts (US 2024/0281331 A1).
With respect to claim 1, Gerphagnon teaches: A method comprising:
receiving a prediction indicating that a failure within a computing system is predicted to occur at an anticipated time (see e.g. Gerphagnon, paragraph 47: “determining a date of failure of the application 12”; and paragraph 48: “date of failure of the application 12 is computed from a prediction”);
assessing one or more existing processes over a time window to identify data for preservation (see e.g. Gerphagnon, paragraph 60: “a step of programming the checkpoint”; and paragraph 5: “In order to avoid the loss of data and computations carried out before the failure, backup mechanisms, called “checkpoints”, exist and make it possible to save, on a local or remote storage solution, all the data necessary for the application at a precise time instant in its execution, for each of the nodes”), wherein the time window begins at the reception of the prediction and extends to the anticipated time of the failure (see e.g. Gerphagnon, paragraph 60: “The checkpoint is programmed to be triggered at a time instant that depends on a saving date, preferably before the date of failure. In particular, by way of at least one embodiment, the trigger time instant of the checkpoint can be a time instant preceding the date of failure. For example, in one or more embodiments, the time instant preceding the date of failure precedes the date of failure by at least a predetermined duration”);
quiescing one or more workloads of the computing system (see e.g. Gerphagnon, paragraph 77: “halt of the Ethernet port prevents the execution of computations but the computation data and the state of the processor are retained”) based on the assessment (see e.g. Gerphagnon, paragraph 76: “frequency-based checkpoints are programmed so that they are triggered successively, respecting a trigger interval”; and paragraph 77: “this duration can be adapted to the application 12 being executed and/or to the confidence index and/or to the resource identifier…in the case of an application 12 executing on a processor from data received via an Ethernet port and stored on a random-access memory, if the identifier indicates that the resource anomaly relates to the Ethernet port then it is not a critical resource and the duration can be long, for example greater than 30 minutes; indeed, the halt of the Ethernet port prevents the execution of computations but the computation data and the state of the processor are retained”);
initiating a memory dump process to save data in memory of the computing system (see e.g. Gerphagnon, paragraph 5: “save, on a local or remote storage solution, all the data necessary for the application at a precise time instant in its execution, for each of the nodes. In other words, the checkpoint can be interpreted as taking an image of the state of the application at a given time instant”; paragraph 63: “By “full checkpoint”, it is meant a checkpoint used to save, to a remote or local dedicated memory, all the data which are used by the application 12 at the trigger time instant and which is stored in a volatile and/or non-volatile memory of the node 11”; and paragraph 64: “By “partial checkpoint”, it is meant a checkpoint used to save only a part of the data which are used by the application 12 at the trigger time instant and which is stored in a volatile and/or non-volatile memory of the node 11”); and
Gerphagnon does not but Roberts teaches:
searching backup resources (see e.g. Roberts, paragraph 18: “utilize in-memory versioning to save known-good snapshots of application state directly at the memory system. Upon restart from a failure, in addition to the standby application instance on a different processor resource using the memory allocated to the primary application, the system may rollback data in the memory to the last versions that were checkpointed”; and paragraph 20: “to implement in-memory versioning, the memory device allocates or assigns two or more memory locations within the memory device to a single corresponding memory request address. One memory location stores the known-good value of the request address as of the time of a most recent or last commit operation. The other memory location stores the working copy—that is, it stores the updated value, which reflects to the checkpoint value, since the last commit or rollback operation. Whether a particular read or write to a particular request address is serviced using the first or second memory locations depends on the state of metadata and the in-memory versioning mode”) to expedite the memory dump process (see e.g. Roberts, paragraph 18: “Because the checkpointing is done directly in memory, this allows for fast restore of a last-known good state of the application”; and paragraph 19: “by using in-memory versioning, the technical problems of using potentially corrupted memory values are solved with the technical solution of using in-memory versioning which allows for fast checkpointing and restore”).
Gerphagnon and Roberts are analogous art because they are in the same field of endeavor: handling program failures by utilizing a checkpointing mechanism. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Gerphagnon with the teachings of Roberts. The motivation/suggestion would be to improve the speed and the efficiency of the checkpointing and restoration mechanisms (see e.g. Roberts, paragraph 19).
With respect to claim 2, Gerphagnon as modified teaches: The method of claim 1, further comprising:
Gerphagnon does not but Roberts teaches:
disabling paging of the one or more existing processes (see e.g. Roberts, paragraph 52: “To reassign the address space, the memory routing table overwrites the information describing the owner of the memory allocation from operation 510 with information about the second instance of the application”); and
allowing paging of one or more new processes that are initiated (see e.g. Roberts, paragraph 52: “memory routing table was updated to indicate that a particular address is allocated to a process identifier of the first instance of the application executing on a particular processing resource, when that memory address is reassigned at operation 525, the routing table is updated to indicate that the particular address is allocated to a process identifier of the second instance of the application executing on a same or different processing resource”) after the reception of the prediction (see e.g. Roberts, paragraph 50: “identify an error in the application… a failure of the application to respond to a heartbeat or keep alive message, a failure of the application to respond to a status message”).
Gerphagnon and Roberts are analogous art because they are in the same field of endeavor: handling program failures by utilizing a checkpointing mechanism. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Gerphagnon with the teachings of Roberts. The motivation/suggestion would be to improve the speed and the efficiency of the checkpointing and restoration mechanisms (see e.g. Roberts, paragraph 19).
With respect to claim 3, Gerphagnon as modified teaches: The method of claim 1, wherein the failure within the computing system comprises at least one of a system crash, an outage (see e.g. Gerphagnon, paragraph 77: “halt of the Ethernet port”), or a performance degradation (see e.g. Gerphagnon, paragraph 4: “errors, called failures, due to a resource anomaly”).
With respect to claim 4, Gerphagnon as modified teaches: The method of claim 1, wherein the data saved during the memory dump process captures a state of the one or more existing processes at the anticipated time (see e.g. Gerphagnon, paragraph 5: “In order to avoid the loss of data and computations carried out before the failure, backup mechanisms, called “checkpoints”, exist and make it possible to save, on a local or remote storage solution, all the data necessary for the application at a precise time instant in its execution, for each of the nodes”; and paragraph 63: “By “full checkpoint”, it is meant a checkpoint used to save, to a remote or local dedicated memory, all the data which are used by the application 12 at the trigger time instant and which is stored in a volatile and/or non-volatile memory of the node 11”).
With respect to claim 5, Gerphagnon as modified teaches: The method of claim 1, further comprising organizing the data saved during the memory dump process into structured documentation for debug analysis (see e.g. Gerphagnon, paragraph 51: “Resource data collection by means of the probes, in one or more embodiments, is performed during the execution of the application 12 and/or before the execution of the application 12, for example during the execution of other applications 12. The interest of collecting resource data before the execution of the application 12 is to collect resource data during abnormal operation phases. These data are thus associated with resource anomalies and is thus analyzed to determine trends of occurrences of the resource anomaly. The collection can also relate to one or more event logs and/or performance indices such as Reliability, Availability and Serviceability (RAS) indices. The collection can be implemented by means of a collection program such as Prometheus™ or Elasticsearch™”).
With respect to claim 6, Gerphagnon as modified teaches: The method of claim 1, wherein
Gerphagnon does not but Roberts teaches:
searching the backup resources comprises performing a system topology scan of the computing system to identify the backup resources (see e.g. Roberts, paragraph 46: “Application memory assignment component 420 assigns one or more memory resources to one or more applications and/or processing resources in a disaggregated memory architecture…Application memory assignment component 420 may track the total amount of memory in the disaggregated memory system”).
Gerphagnon and Roberts are analogous art because they are in the same field of endeavor: handling program failures by utilizing a checkpointing mechanism. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Gerphagnon with the teachings of Roberts. The motivation/suggestion would be to improve the speed and the efficiency of the checkpointing and restoration mechanisms (see e.g. Roberts, paragraph 19).
With respect to claim 7, Gerphagnon as modified teaches: The method of claim 1,
Gerphagnon does not but Roberts teaches:
wherein searching the backup resources comprises examining a defined policy that specifies the backup resources to be used in response to the failure (see e.g. Roberts, paragraph 46: “Application memory assignment component 420 may track the total amount of memory in the disaggregated memory system, and may allocate free memory. A memory allocation may reserve the memory for a particular application and may map an application-specific or processing resource-specific memory address space to specific physical resources which may be disaggregated from the processing resources. This mapping may be stored in a table of memory switch 122 and is used to route memory requests from processing resources to the appropriate memory subsystems”; and paragraph 47: “In-memory versioning coordinator 425 may track which memory systems support in-memory versioning. In some examples, the application and/or operating system may request memory allocations from application memory assignment component 420 which are capable of in-memory versioning”).
Gerphagnon and Roberts are analogous art because they are in the same field of endeavor: handling program failures by utilizing a checkpointing mechanism. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Gerphagnon with the teachings of Roberts. The motivation/suggestion would be to improve the speed and the efficiency of the checkpointing and restoration mechanisms (see e.g. Roberts, paragraph 19).
With respect to claim 8, Gerphagnon as modified teaches: The method of claim 1, further comprising:
conducting the memory dump process on primary resources of the computing system (see e.g. Gerphagnon, paragraph 5: “save, on a local or remote storage solution, all the data necessary for the application at a precise time instant in its execution, for each of the nodes. In other words, the checkpoint can be interpreted as taking an image of the state of the application at a given time instant”; paragraphs 63-64).
Gerphagnon does not but Roberts teaches:
upon determining that the backup resources are available for use, provisioning the backup resources to maintain normal operations of the computing system (see e.g. Roberts, paragraph 46: “Application memory assignment component 420 may track the total amount of memory in the disaggregated memory system, and may allocate free memory. A memory allocation may reserve the memory for a particular application and may map an application-specific or processing resource-specific memory address space to specific physical resources which may be disaggregated from the processing resources”; and paragraph 13: “Applications may save checkpoint data in non-volatile storage in case of a hardware and/or software failure. Upon a failure, in some examples, the execution of the application is switched to a redundant or standby hardware and/or application. This process is called “failover.””); and
Gerphagnon and Roberts are analogous art because they are in the same field of endeavor: handling program failures by utilizing a checkpointing mechanism. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Gerphagnon with the teachings of Roberts. The motivation/suggestion would be to improve the speed and the efficiency of the checkpointing and restoration mechanisms (see e.g. Roberts, paragraph 19).
With respect to claim 9, Gerphagnon as modified teaches: The method of claim 1, further comprising,
Gerphagnon does not but Roberts teaches:
upon determining that unused memory within the backup resources is available for use, allocating the unused memory from the backup resources for one or more new processes that are initiated after the reception of the prediction (see e.g. Roberts, paragraph 46: “Application memory assignment component 420 may track the total amount of memory in the disaggregated memory system, and may allocate free memory. A memory allocation may reserve the memory for a particular application and may map an application-specific or processing resource-specific memory address space to specific physical resources which may be disaggregated from the processing resources”; and paragraph 13).
Gerphagnon and Roberts are analogous art because they are in the same field of endeavor: handling program failures by utilizing a checkpointing mechanism. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Gerphagnon with the teachings of Roberts. The motivation/suggestion would be to improve the speed and the efficiency of the checkpointing and restoration mechanisms (see e.g. Roberts, paragraph 19).
With respect to claim 10, Gerphagnon as modified teaches: The method of claim 1, further comprising:
conducting the memory dump process upon completion of the failover (see e.g. Gerphagnon, paragraph 5: “save, on a local or remote storage solution, all the data necessary for the application at a precise time instant in its execution, for each of the nodes. In other words, the checkpoint can be interpreted as taking an image of the state of the application at a given time instant”; paragraphs 63-64; and paragraph 76: “frequency-based checkpoints are programmed so that they are triggered successively, respecting a trigger interval”).
Gerphagnon does not but Roberts teaches:
upon determining that the backup resources have already been provisioned, performing a failover operation that moves normal operations of the computing system to a disaster recovery site (see e.g. Roberts, paragraph 13: “Applications may save checkpoint data in non-volatile storage in case of a hardware and/or software failure. Upon a failure, in some examples, the execution of the application is switched to a redundant or standby hardware and/or application. This process is called “failover.””; and paragraph 18: “Upon restart from a failure, in addition to the standby application instance on a different processor resource using the memory allocated to the primary application, the system may rollback data in the memory to the last versions that were checkpointed”); and
Gerphagnon and Roberts are analogous art because they are in the same field of endeavor: handling program failures by utilizing a checkpointing mechanism. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Gerphagnon with the teachings of Roberts. The motivation/suggestion would be to improve the speed and the efficiency of the checkpointing and restoration mechanisms (see e.g. Roberts, paragraph 19).
With respect to claims 11-19: Claims 11-19 are directed to a system comprising one or more computer processors and one or more memories containing one or more programs to perform operations corresponding the method disclosed in claims 1-6 and 8-10, respectively; please see the rejections directed to claims 1-6 and 8-10 above which also cover the limitations recited in claims 11-19. Note that, Gerphagnon also discloses a system 10 comprising one or more processors 11a and one or more memories 11b with instructions to perform operations corresponding to the method disclosed in claims 1-6 and 8-10 (see Gerphagnon, paragraph 45; Fig. 2).
With respect to claim 20: Claim 20 is directed to one or more non-transitory computer-readable media containing program code to perform operations corresponding the method disclosed in claim 1; please see the rejection directed to claim 1 above which also covers the limitations recited in claim 20. Note that, Gerphagnon also discloses a computer-readable recording medium comprising instructions to perform operations corresponding to the method disclosed in claim 1 (see Gerphagnon, paragraph 37).
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ashmore et al. (US 2006/0015683 A1) discloses a failover mechanism that enables a memory controller to quickly and efficiently flush data from a cache memory to a non-volatile memory (see paragraph 26).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Umut Onat whose telephone number is (571)270-1735. The examiner can normally be reached M-Th 9:00-7:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kevin L Young can be reached at (571) 270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/UMUT ONAT/Primary Examiner, Art Unit 2194
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