DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-5 and 8-18 are pending in this application.
Response to Amendment
Claims 1 and 8-18 are amended. Claims 6 and 7 are canceled.
Response to Arguments
Applicant's arguments filed 04/28/2026 have been fully considered but they are not persuasive. Applicant argues “Baluja fails to expressly or inherently disclose, among other features, ‘a parallel resistor, a negative temperature coefficient resistor (R-NTC) connected in parallel with the parallel resistor, and a series resistor connected in series with a parallel combination of the parallel resistor and the R-NTC.’ Therefore, Baluja fails to anticipate each and every feature presently recited in independent claim 1. In addition, claims 2-9 are also patentable over Baluja in view of their respective dependencies on claim 1.” However, the features “a parallel resistor, a negative temperature coefficient resistor (R-NTC) connected in parallel with the parallel resistor, and a series resistor connected in series with a parallel combination of the parallel resistor and the R-NTC” are limitations from now canceled claims 6 and 7 which have been added to currently amended claim 1. Currently amended claim 1 has identical limitations to the previous claim 7 which is now canceled and was rejected in the Non-Final Rejection mailed 01/30/2026. As such, Baluja has already been shown to teach “a parallel resistor, a negative temperature coefficient resistor (R-NTC) connected in parallel with the parallel resistor, and a series resistor connected in series with a parallel combination of the parallel resistor and the R-NTC” and Applicant does not give any reasons why the rejection of claim 7 in the Non-Final Rejection mailed on 01/30/2026 is improper. Baluja teaches a parallel resistor (i.e. sensing resistor 115)(fig.2); a negative temperature coefficient resistor (R-NTC) (i.e. NTC thermistor 116)(fig.2) connected in parallel with the parallel resistor (implicit); and a series resistor (i.e. resistor 119)(fig.2) connected in series with a parallel combination of the parallel resistor and the R-NTC (implicit)(refer to fig.2). Therefore this is not persuasive. Applicant further argues “Rogers is relied upon as allegedly describing a protection component as a temperature compensation circuit. Rogers, however, does not disclose ‘a parallel resistor, a negative temperature coefficient resistor (R-NTC) connected in parallel with the parallel resistor, and a series resistor connected in series with a parallel combination of the parallel resistor and the R- NTC.’ The alleged AAPA does not compensate for the features missing from Rogers. Therefore, the combination of alleged AAPA and Rogers fails to teach, show, suggest, or render obvious each and every feature presently recited in independent claim 1. In addition, claims 2-18 are also patentable over the combination of alleged AAPA and Rogers in view of their respective dependencies on claim 1.” However, the features “a parallel resistor, a negative temperature coefficient resistor (R-NTC) connected in parallel with the parallel resistor, and a series resistor connected in series with a parallel combination of the parallel resistor and the R-NTC” are limitations from now canceled claims 6 and 7 which have been added to currently amended claim 1. Currently amended claim 1 has identical limitations to the previous claim 7 which is now canceled and was rejected in the Non-Final Rejection mailed 01/30/2026. As such, The combination of AAPA and Rogers has already been shown to teach “a parallel resistor, a negative temperature coefficient resistor (R-NTC) connected in parallel with the parallel resistor, and a series resistor connected in series with a parallel combination of the parallel resistor and the R-NTC” and Applicant does not give any reasons why the rejection of claim 7 in the Non-Final Rejection mailed on 01/30/2026 is improper. AAPA and Rogers teach a parallel resistor (i.e. Rogers resistor 32)(fig.1); a negative temperature coefficient resistor (R-NTC) (i.e. Rogers thermistor 33)(fig.1A)(refer also to Rogers col. 4 lines 16-39)(described function of the temperature compensation circuit requires thermistor 33 to be an NTC thermistor) connected in parallel with the parallel resistor (implicit); and a series resistor (i.e. Rogers resistor 31)(fig.1) connected in series with a parallel combination of the parallel resistor and the R-NTC (implicit)(refer to Rogers fig.1). Therefore this is not persuasive.
Claim Objections
Claim 9 is objected to because of the following informalities: Claim 9 recites the limitation “claim 6” in line 1 of the claim. This appears to mean “claim 8”. Appropriate correction is required.
Claim 10 is objected to because of the following informalities: Claim 9 recites the limitation “claim 7” in line 1 of the claim. This appears to mean “claim 9”. Appropriate correction is required.
Claim 11 is objected to because of the following informalities: Claim 9 recites the limitation “claim 8” in line 1 of the claim. This appears to mean “claim 10”. Appropriate correction is required.
Claim 12 is objected to because of the following informalities: Claim 9 recites the limitation “claim 9” in line 1 of the claim. This appears to mean “claim 11”. Appropriate correction is required.
Claim 13 is objected to because of the following informalities: Claim 9 recites the limitation “claim 10” in line 1 of the claim. This appears to mean “claim 12”. Appropriate correction is required.
Claim 14 is objected to because of the following informalities: Claim 9 recites the limitation “claim 11” in line 1 of the claim. This appears to mean “claim 13”. Appropriate correction is required.
Claim 15 is objected to because of the following informalities: Claim 9 recites the limitation “claim 12” in line 1 of the claim. This appears to mean “claim 14”. Appropriate correction is required.
Claim 16 is objected to because of the following informalities: Claim 9 recites the limitation “claim 13” in line 1 of the claim. This appears to mean “claim 15”. Appropriate correction is required.
Claim 17 is objected to because of the following informalities: Claim 9 recites the limitation “claim 14” in line 1 of the claim. This appears to mean “claim 16”. Appropriate correction is required.
Claim 18 is objected to because of the following informalities: Claim 9 recites the limitation “claim 15” in line 1 of the claim. This appears to mean “claim 17”. Appropriate correction is required.
Claims 10-15 are objected to because of the following informalities: Claim 10 recites the limitation “the second biasing resistor” in line 3 of the claim. There is insufficient antecedent basis for this limitation. Furthermore, there is no “first biasing resistor” claimed and it is unclear if one or two biasing resistors are being claimed. Claim 16 recites “a first biasing resistor” and “a second biasing resistor”. It appears that claims 10-15 should depend on claim 16 to obviate the above issues with the dependency of claim 16 being changed to claim 9. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baluja U.S. Patent Application 2023/0041997 (hereinafter “Baluja”).
Regarding claim 1, Baluja teaches a sensor excitation circuit (i.e. intrinsically safe circuit 100)(fig.2) comprising: a voltage driver circuit (i.e. transistor 114 and resistor 113)(fig.2) configured to selectively conduct electrical current via a driver output (i.e. output terminal 121)(fig.2) in response to a first operating voltage exceeding a driver voltage threshold (V1be) (implicit)(refer to [0041 and [0042]); and a short-circuit protection circuit (i.e. transistor 118, sensing resistor 115, NTC thermistor 116 transient suppressor 117, and resistor 119)(fig.2) connected to the voltage driver circuit (implicit), the short-circuit protection circuit comprising: a protection semiconductor switching device (i.e. transistor 118)(fig.2) configured to limit the electrical current through the voltage driver circuit (refer to [0042]) in response to switching on when a second operating voltage exceeds a protection voltage threshold (V2be)(refer to [0042]); and a temperature compensation circuit (i.e. sensing resistor 115, NTC thermistor 116, and resistor 119)(fig.2) connected to the protection semiconductor switching device (implicit), wherein the temperature compensation circuit comprises: a parallel resistor (i.e. sensing resistor 115)(fig.2); a negative temperature coefficient resistor (R-NTC) (i.e. NTC thermistor 116)(fig.2) connected in parallel with the parallel resistor (implicit); and a series resistor (i.e. resistor 119)(fig.2) connected in series with a parallel combination of the parallel resistor and the R-NTC (implicit)(refer to fig.2), wherein the temperature compensation circuit is configured to limit a variation of the protection threshold voltage (V2be) in response to exposing the protection semiconductor switching device to different temperatures (refer to [0043]).
Regarding claim 2, Baluja teaches the sensor excitation circuit of claim 1, wherein the protection semiconductor switching device includes a protection transistor (i.e. transistor 118)(fig.2).
Regarding claim 3, Baluja teaches the sensor excitation circuit of claim 2, wherein the voltage driver circuit comprises: a biasing circuit (i.e. resistor 113)(fig.2); and a driver semiconductor switching device (i.e. transistor 114)(fig.2) including a driver control terminal (i.e. base B1 in the figure below)(fig.2) connected to the biasing circuit (implicit) and a driver output terminal (i.e. emitter E1 in the figure below)(fig.2) configure to conduct the electrical current to a load (implicit).
PNG
media_image1.png
259
550
media_image1.png
Greyscale
Regarding claim 4, Baluja teaches the sensor excitation circuit of claim 3, wherein the driver semiconductor switching device includes a driver transistor (i.e. transistor 114)(fig.2) having a collector (i.e. collector C1 in the figure above)(fig.2) configured to receive a supply voltage (refer to positive input terminal 101)(fig.2), a base (i.e. base B1 in the figure above)(fig.2) serving as the driver control terminal (implicit), and an emitter (i.e. emitter E1 in the figure above)(fig.2) serving as the driver output (implicit).
Regarding claim 5, Baluja teaches the sensor excitation circuit of claim 4, wherein the protection transistor comprises: a collector (i.e. collector C2 in the figure above)(fig.2) connected to the base of the driver transistor (implicit)(refer to fig.2); a base (i.e. base B2 in the figure above)(fig.2) connected to the temperature compensation circuit (implicit)(refer to fig.2) and the emitter of the driver transistor (implicit)(refer to fig.2); and an emitter (i.e. emitter E2 in the figure above)(fig.2) connected to a ground reference point (implicit)(refer to load 122 and OUT-)(fig.2).
Regarding claim 8, Baluja teaches the sensor excitation circuit of claim 7, wherein the parallel resistor has a resistance value configured to control a current limit of the electrical current conducted through the driver transistor in response to switching on the protection transistor (implicit)(refer to [0043]).
Regarding claim 9, Baluja teaches the sensor excitation circuit of claim 8, wherein the R-NTC has a changing resistance that decreases with increasing temperature (implicit)(refer to [0043]) and which varies a resistance of the combination of the parallel resistor and the R-NTC in response to the changing resistance (implicit)(refer to [0043]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5 and 8-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art (AAPA), and further in view of Rogers U.S. Patent No. 3,723,774 (hereinafter “Rogers”).
Regarding claim 1, AAPA teaches a sensor excitation circuit (refer to fig.1A) comprising: a voltage driver circuit (i.e. drive transistor Q1 and resistors R1 and R2)(fig.1A) configured to selectively conduct electrical current via a driver output (implicit)(fig.1A) in response to a first operating voltage exceeding a driver voltage threshold (V1be) (implicit)(refer to [0030]); and a short-circuit protection circuit (i.e. short circuit protection circuit 12)(fig.1A) connected to the voltage driver circuit (implicit), the short-circuit protection circuit comprising: a protection semiconductor switching device (i.e. protection transistor Q2)(fig.1A) configured to limit the electrical current through the voltage driver circuit (refer to [0030]) in response to switching on when a second operating voltage exceeds a protection voltage threshold (V2be)(refer to [0030]); and a protection component (i.e. protection resistor R3)(fig.1A) connected to the protection semiconductor switching device (implicit); however, AAPA does not teach the protection component being a temperature compensation circuit; wherein the temperature compensation circuit comprises: a parallel resistor; a negative temperature coefficient resistor (R-NTC) connected in parallel with the parallel resistor; and a series resistor connected in series with a parallel combination of the parallel resistor and the R-NTC, wherein the temperature compensation circuit is configured to limit a variation of the protection threshold voltage (V2be) in response to exposing the protection semiconductor switching device to different temperatures. However, Rogers teaches the protection component being a temperature compensation circuit (i.e. resistors 31 and 32 and thermistor 33)(fig.1); wherein the temperature compensation circuit comprises: a parallel resistor (i.e. Rogers resistor 32)(fig.1); a negative temperature coefficient resistor (R-NTC) (i.e. Rogers thermistor 33)(fig.1A)(refer also to Rogers col. 4 lines 16-39)(described function of the temperature compensation circuit requires thermistor 33 to be an NTC thermistor) connected in parallel with the parallel resistor (implicit); and a series resistor (i.e. Rogers resistor 31)(fig.1) connected in series with a parallel combination of the parallel resistor and the R-NTC (implicit)(refer to Rogers fig.1), wherein the temperature compensation circuit is configured to limit a variation of the protection threshold voltage (V2be) in response to exposing the protection semiconductor switching device to different temperatures (refer to col. 4 lines 16-39). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the sensor excitation circuit of AAPA to include the temperature compensation circuit of Rogers to provide the advantage of maintaining a constant current limit despite varying temperatures in order to prevent damage to the circuit while limiting nuisance operation of the limiting circuit (refer to Rogers col. 4 lines 16-39 and abstract).
Regarding claim 2, AAPA and Rogers teach the sensor excitation circuit of claim 1, wherein the protection semiconductor switching device includes a protection transistor (i.e. AAPA protection transistor Q2)(fig.1A).
Regarding claim 3, AAPA and Rogers teach the sensor excitation circuit of claim 2, wherein the voltage driver circuit comprises: a biasing circuit (i.e. AAPA resistors R1 and R2)(fig.1A); and a driver semiconductor switching device (i.e. AAPA transistor Q1)(fig.1A) including a driver control terminal (i.e. AAPA base of transistor Q1)(fig.1A) connected to the biasing circuit (implicit) and a driver output terminal (i.e. AAPA emitter of transistor Q1)(fig.1A) configure to conduct the electrical current to a load (i.e. AAPA Load)(fig.1A).
Regarding claim 4, AAPA and Rogers teach the sensor excitation circuit of claim 3, wherein the driver semiconductor switching device includes a driver transistor (i.e. AAPA transistor Q1)(fig.1A) having a collector (i.e. AAPA collector of transistor Q1)(fig.1A) configured to receive a supply voltage (refer to AAPA P15V)(fig.1A), a base (i.e. AAPA base of transistor Q1)(fig.1A) serving as the driver control terminal (implicit), and an emitter (i.e. AAPA emitter of transistor Q1)(fig.1A) serving as the driver output (implicit).
Regarding claim 5, AAPA and Rogers teach the sensor excitation circuit of claim 4, wherein the protection transistor comprises: a collector (i.e. AAPA collector c of transistor Q2)(fig.1A) connected to the base of the driver transistor (implicit)(refer to AAPA fig.1A); a base (i.e. AAPA base b of transistor Q2)(fig.1A) connected to the temperature compensation circuit (implicit)(refer to AAPA fig.1A) and the emitter of the driver transistor (implicit)(refer to AAPA fig.1A); and an emitter (i.e. AAPA emitter e of transistor Q2)(fig.1A) connected to a ground reference point (implicit)(refer to AAPA fig.1A).
Regarding claim 8, AAPA and Rogers teach the sensor excitation circuit of claim 7, wherein the parallel resistor has a resistance value configured to control a current limit of the electrical current conducted through the driver transistor in response to switching on the protection transistor (implicit)(refer to Rogers col. 4 lines 16-39).
Regarding claim 9, AAPA and Rogers teach the sensor excitation circuit of claim 8, wherein the R-NTC has a changing resistance that decreases with increasing temperature (implicit)(refer to Rogers col. 4 lines 16-39) and which varies a resistance of the combination of the parallel resistor and the R-NTC in response to the changing resistance (implicit)(refer to Rogers col. 4 lines 16-39).
Regarding claim 10, AAPA and Rogers teach the sensor excitation circuit of claim 9; however, they do not teach wherein the parallel resistor has a first terminal connected in common with the base of the protection transistor, the second terminal of the second biasing resistor, the emitter of the driver transistor and a first terminal of the R-NTC, and has an opposing second terminal connected to a second terminal of the R-NTC and a first terminal of the series resistor. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to reverse the connections of the thermal compensation circuit of Rogers so that the base of transistor 38 is connected to resistor 32 and thermistor 33 and the emitter of transistor 38 is connected to resistor 31 to provide the advantage of using an equivalent connection of the resistors and thermistor since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Therefore, AAPA and Rogers teach wherein the parallel resistor has a first terminal connected in common with the base of the protection transistor, the second terminal of the second biasing resistor (refer to AAPA resistor R2)(fig.1A), the emitter of the driver transistor and a first terminal of the R-NTC (refer to Rogers resistor 32)(fig.1), and has an opposing second terminal connected to a second terminal of the R-NTC and a first terminal of the series resistor (refer to Rogers resistors 31 and 32 and thermistor 33)(fig.1).
Regarding claim 11, AAPA and Rogers teach the sensor excitation circuit of claim 10, wherein the R-NTC has a first terminal connected in common with a first terminal of the parallel resistor, the base of the protection transistor, the second terminal of the second biasing resistor (refer to AAPA resistor R2)(fig.1A), and the emitter of the driver transistor (implicit)(refer to Rogers resistor 32 and thermistor 33)(fig.1), and has a second terminal connected in common with a second terminal of the parallel resistor and a first terminal of the series resistor (refer to Rogers resistors 31 and 32 and thermistor 33)(fig.1).
Regarding claim 12, AAPA and Rogers teach the sensor excitation circuit of claim 11, wherein the series resistor has an opposing second terminal connected to the emitter of the protection transistor (refer to Rogers resistor 31)(fig.1), the series resistor configured to further limit the electrical current through the driver transistor to a target current level (implicit).
Regarding claim 13, AAPA and Rogers teach the sensor excitation circuit of claim 12, wherein the parallel resistor is connected across the base and the emitter of the protection transistor to set a short-circuit trip point of the protection transistor (implicit).
Regarding claim 14, AAPA and Rogers teach the sensor excitation circuit of claim 13, wherein a short-circuit current limit on the driver output is set by the protection voltage threshold (V2be) of the protection transistor and the resistance of the parallel resistor (implicit).
Regarding claim 15, AAPA and Rogers teach the sensor excitation circuit of claim 14, wherein the biasing circuit is configured to set an operating point of the driver semiconductor switching device (implicit).
Regarding claim 16, AAPA and Rogers teach the sensor excitation circuit of claim 15, wherein the biasing circuit includes a first biasing resistor (i.e. AAPA resistor R1)(fig.1A) and a second biasing resistor (i.e. AAPA resistor R2)(fig.1A).
Regarding claim 17, AAPA and Rogers teach the sensor excitation circuit of claim 16, wherein the first biasing resistor includes a first terminal connected to a first terminal of the second biasing resistor (implicit)(refer to AAPA fig.1A) and includes an opposing second terminal connected to the base of the driver transistor (implicit)(refer to AAPA fig.1A).
Regarding claim 18, AAPA and Rogers teach the sensor excitation circuit of claim 17, wherein the base of the driver transistor is connected to the second terminal of the first biasing resistor (implicit)(refer to AAPA fig.1A), and the emitter of the driver transistor is connected to a second terminal of the second biasing resistor (implicit)(refer to AAPA fig.1A).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN J COMBER whose telephone number is (571)272-6133. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEVIN J COMBER/Primary Examiner, Art Unit 2838
Prosecution Insights