DETAILED ACTION
This Notice is responsive to communication filed on 08/16/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I invention, in the reply filed on 08/16/2026 is acknowledged.
Claims 11-20 are cancelled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 0.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/31/2024 and 06/13/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claims 1-8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Okuno (US 20260173398), and further in view of Yamazaki et al. (US 20230389332).
Regarding claim 1, Okuno discloses a semiconductor structure, comprising:
a semiconductor substrate Fig. 2: 2 (para. 0068);
an underlayer Fig. 2: 22 covering the semiconductor substrate Fig. 2: 2;
a ferroelectric material layer Fig. 2: 23 (para. 0026) covering the underlayer Fig. 2: 22,
wherein the underlayer Fig. 2: 22 has a surface (i.e. outer surface) facing the ferroelectric material layer Fig. 2: 23, and
the surface has a root mean square roughness of less than 1 nm; and
a conductive layer Fig. 2: 24 covering the ferroelectric material layer Fig. 2: 23.
Yamazaki discloses the following claim limitation not explicitly disclosed by Okuno:
the surface has a root mean square roughness of less than 1 nm.
Yamazaki discloses a conductive layer 110 of similar material as the clamed invention (para. 0125, i.e. titanium, molybdenum, an alloy, and the like), having a top surface with a roughness root mean square less than 1nm (para. 0127).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Okuno with Yamazaki in order to allow the underlayer (i.e. conductive layer) have high planarity, enhancing the crystallinity and the ferroelectricity of the ferroelectric material layer (i.e. insulator) (para. 0127).
Regarding claim 2, Yamazaki discloses the following claim limitations not explicitly disclosed by Okuno: the semiconductor structure of claim 1, further comprising
an insulating layer disposed between the underlayer Fig. 1B: 110 and the ferroelectric material layer Fig. 1B: 130.
Yamazaki discloses a layer enhancing crystallinity of the insulator 130 (i.e. ferroelectric material layer) provided between the insulator 130 and the conductor 110, and also discloses this layer made from material including hafnium oxide, zirconium oxide, and the like (para. 0129).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Okuno with Yamazaki in order to enhance the crystallinity of the insulator (para. 0129).
Regarding claim 3, Yamazaki discloses the following claim limitations not explicitly disclosed by Okuno: the semiconductor structure of claim 1, further comprising
an insulating layer disposed between the ferroelectric material layer Fig. 1B: 130 and the conductive layer Fig. 1B: 120.
Yamazaki discloses a layer enhancing crystallinity of the insulator 130 (i.e. ferroelectric material layer) provided between the insulator 130 and the conductor 120, and also discloses this layer made from material including hafnium oxide, zirconium oxide, and the like (para. 0129).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Okuno with Yamazaki in order to enhance the crystallinity of the insulator (para. 0129).
Regarding claim 4, Yamazaki discloses the following claim limitations not explicitly disclosed by Okuno: the semiconductor structure of claim 1, further comprising
a first insulating layer and a second insulating layer (para. 0129),
wherein the first insulating layer is disposed between the underlayer Fig. 1B: 110 and the ferroelectric material layer Fig. 1B: 130, and
the second insulating layer is disposed between the ferroelectric material layer Fig. 1B: 130 and the conductive layer Fig. 1B: 120.
Yamazaki discloses a layer enhancing crystallinity of the insulator 130 (i.e. ferroelectric material layer) provided between the insulator 130 and the conductors 110 and 120, and also discloses this layer made from material including hafnium oxide, zirconium oxide, and the like (para. 0129).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Okuno with Yamazaki in order to enhance the crystallinity of the insulator (para. 0129).
Regarding claim 5, Okuno discloses the semiconductor structure of claim 1, wherein the semiconductor substrate Fig. 2: 21 is columnar, the underlayer Fig. 2: 22 surrounds the semiconductor substrate Fig. 2: 21, the ferroelectric material layer Fig. 2: 23 surrounds the underlayer Fig. 2: 22, and the conductive layer Fig. 2: 24 surrounds the ferroelectric material layer Fig. 2: 23 (para. 0068 discloses columnar, cylindrical shape of the conductive pillar, and subsequent layers).
Regarding claim 6, Yamazaki discloses the following claim limitations not explicitly disclosed by Okuno: the semiconductor structure of claim 5, further comprising
an insulating layer disposed between the underlayer Fig. 1B: 110 and the ferroelectric material layer Fig. 1B: 130.
Yamazaki discloses a layer enhancing crystallinity of the insulator 130 (i.e. ferroelectric material layer) provided between the insulator 130 and the conductor 110, and also discloses this layer made from material including hafnium oxide, zirconium oxide, and the like (para. 0129).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Okuno with Yamazaki in order to enhance the crystallinity of the insulator (para. 0129).
Regarding claim 7, Yamazaki discloses the following claim limitations not explicitly disclosed by Okuno: the semiconductor structure of claim 5, further comprising
an insulating layer disposed between the ferroelectric material layer Fig. 1B: 130 and the conductive layer Fig. 1B: 120.
Yamazaki discloses a layer enhancing crystallinity of the insulator 130 (i.e. ferroelectric material layer) provided between the insulator 130 and the conductor 120, and also discloses this layer made from material including hafnium oxide, zirconium oxide, and the like (para. 0129).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Okuno with Yamazaki in order to enhance the crystallinity of the insulator (para. 0129).
Regarding claim 8, Yamazaki discloses the following claim limitations not explicitly disclosed by Okuno: the semiconductor structure of claim 5, further comprising
a first insulating layer and a second insulating layer (para. 0129),
wherein the first insulating layer is disposed between the underlayer Fig. 1B: 110 and the ferroelectric material layer Fig. 1B: 130, and
the second insulating layer is disposed between the ferroelectric material layer Fig. 1B: 130 and the conductive layer Fig. 1B: 120.
Yamazaki discloses a layer enhancing crystallinity of the insulator 130 (i.e. ferroelectric material layer) provided between the insulator 130 and the conductors 110 and 120, and also discloses this layer made from material including hafnium oxide, zirconium oxide, and the like (para. 0129).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Okuno with Yamazaki in order to enhance the crystallinity of the insulator (para. 0129).
Regarding claim 10, Okuno discloses the semiconductor structure of claim 1, wherein the underlayer Fig. 2: 22 comprises titanium, titanium nitride, titanium aluminum alloy, titanium aluminum nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, ruthenium, ruthenium dioxide, molybdenum, molybdenum dioxide, molybdenum trioxide, silicon, germanium, silicon germanium, or combinations thereof (para. 0068 teaches titanium, titanium nitride, ruthenium).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Okuno (US 20260173398) and Yamazaki et al. (US 20230389332) as applied to claim 1 above, and further in view of Dokania et al. (US 12,740,066 ).
Regarding claim 9, Dokania discloses the following claim limitations not disclosed by Okuno: the semiconductor structure of claim 1,
wherein the underlayer Fig. 3A: 312a has a thickness of 0.5 nm to 50 nm (col. 8, lines 17-18; teaches 1-30 nm range).
Dokania discloses a conductive oxide layer including a material the same as material disclosed in the present application, having a thickness including the range claimed in claim 9.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Okuno with Dokania to have a conductive oxide with the claimed thickness. Furthermore, per MPEP 2144.05 (I), “in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists.” In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976);
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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