Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I and II in the reply filed on May 1, 2026 is acknowledged. The traversal is on the ground(s) that Species II (FIG. 5B) includes the circuit of Species I (FIG. 5A), namely attenuator 410/400, main gain stage 430, and comparator 450, and simply adds auxiliary gain stage 440. This is found to be persuasive and the restriction is withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 4, 2024 and January 13, 2026 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first load device and second load device must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Paragraph 0047 (line 6) - reference 514L is listed as both an NMOS transistor and a resistor; it appears reference 512L should be listed as the NMOS transistor.
Paragraph 0047 (line 7) - it appears reference 522J should be 522L..
Appropriate correction is required.
Claim Objections
Claims 1, 3-6, 8-10, 12, 15-18, and 20-21 are objected to because of the following informalities:
Claim 1 (line 1) – recites "Receiver circuitry, comprising". It appears the "A" is missing to introduce the receiver circuitry, so to be written as, "A receiver circuitry, comprising".
Claim 1 (lines 9; 11; 13; 16) – recites "a second transistor"; "a third transistor"; "a second resistor"; "a third resistor". It appears the comma is missing after each phrase.
Claim 3 (lines 2; 4; 6) – recites "a fourth resistor"; "a fifth resistor"; "a sixth resistor". It appears the comma is missing after each phrase.
Claim 4 (lines 2; 4) – recites "a first load device"; "a second load device". It appears the comma is missing after each phrase.
Claim 5 (lines 20; 23) – recites "a ninth transistor"; "a tenth transistor". It appears the comma is missing after each phrase.
Claim 6 (lines 4; 7) – recites "an eleventh transistor"; "a twelfth transistor". It appears the comma is missing after each phrase.
Claim 8 (line 2) – recites "wake-up monitor logic". It appears the "a" is missing to introduce the wake-up monitor logic, so to be written as, "a wake-up monitor logic".
Claim 9 (line 2) – recites "logic circuitry". It appears the comma is missing after the phrase.
Claim 9 (line 2) – recites "logic circuitry". It appears the "a" is missing to introduce the logic circuitry, so to be written as, "a logic circuitry".
Claim 10 (line 2) – recites "a tenth resistor". It appears the comma is missing after the phrase.
Claim 12 (line 1) – recites "Receiver circuitry, comprising". It appears the "A" is missing to introduce the receiver circuitry, so to be written as, "A receiver circuitry, comprising".
Claim 12 (line 8) – recites "logic circuitry". It appears the comma is missing after the phrase.
Claim 12 (line 8) – recites "logic circuitry". It appears the "a" is missing to introduce the logic circuitry, so to be written as, "a logic circuitry".
Claim 12 (line 21) – recites "wake-up monitor logic". It appears the "a" is missing to introduce the wake-up monitor logic, so to be written as, "a wake-up monitor logic".
Claim 15 (lines 7; 9; 11; 14) – recites "a third transistor"; "a fourth transistor"; "a fifth resistor"; "a sixth resistor". It appears the comma is missing after each phrase.
Claim 16 (lines 2; 4; 10; 13; 16; 19; 22) – recites "a seventh transistor"; "an eighth transistor"; "a ninth transistor"; "a tenth transistor"; "an eleventh transistor"; "a twelfth transistor"; "a thirteenth transistor". From the review of claims 12-15, it appears the fifth and sixth transistors were not introduced. It appears it should start with "a fifth transistor" and end with "an eleventh transistor".
Claim 16 (lines 16; 19) – recites "an eleventh transistor"; "a twelfth transistor". It appears the comma is missing after each phrase.
Claim 17 (lines 15; 17; 19; 21; 23; 25; 30) – recites "a second transistor"; "a second resistor"; "a third transistor"; "a third resistor"; "a fourth resistor"; "a fifth resistor"; "a pulse filter". It appears the comma is missing after each phrase.
Claim 17 (line 32) – recites "wake-up monitor logic". It appears the "a" is missing to introduce the wake-up monitor logic, so to be written as, "a wake-up monitor logic".
Claim 18 (line 2) – recites "logic circuitry". It appears the comma is missing after the phrase.
Claim 18 (line 2) – recites "logic circuitry". It appears the "a" is missing to introduce the logic circuitry, so to be written as, "a logic circuitry".
Claim 20 (lines 2; 4; 6) – recites "a ninth resistor"; "a tenth resistor"; "an eleventh resistor". It appears the comma is missing after each phrase.
Claim 21 (line 2) – recites "a twelfth resistor". It appears the comma is missing after the phrase.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 4 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Lines 2 and 4-5 of claim 4 recites "first load device" and "second load device". There is a lack of written description of this device. Thus, the specification fails to provide a demonstration of possession of such a device. For compact prosecution, the examiner interprets the load devices to be resistors 514H/514L.
Claim Rejections - 35 USC § 102
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, and 8 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Gupta et al. (US 20200267018 A1); hereinafter Gupta.
Regarding Claim 1, Gupta discloses a receiver circuitry [200], comprising: a first circuit [212] comprising: a first transistor [M2], having first and second terminals and a control terminal, the second terminal coupled to the control terminal [indirectly coupled through M1]; a first resistor [R6], having a first terminal coupled to the second terminal of the first transistor [indirectly coupled through R7/M1], and having a second terminal; a first current source [216], coupled to the second terminal of the first resistor [indirectly coupled through D1/R5]; a second circuit [222] comprising: a second transistor [M3] having first and second terminals, and having a control terminal coupled to the second terminal of the first resistor [indirectly coupled through R5]; a third transistor [M6] having first and second terminals, and having a control terminal coupled to the first terminal of the first resistor [indirectly coupled through R7]; a second resistor [R3] having a first terminal coupled to a first input [203, indirectly coupled through R1] and to the first terminal of the second transistor [indirectly coupled through M4], and having a second terminal coupled to the first terminal of the first transistor [indirectly coupled through R4/M6 to M2]; a third resistor [R4] having a first terminal coupled to a second input [205, indirectly coupled through R2] and to the first terminal of the third transistor [directly coupled to M6], and having a second terminal coupled to the first terminal of the first transistor [indirectly coupled through R3 to M2] and to the second terminal of the second resistor [directly coupled to R3]; and a first comparator [232], having a first input [VOP] coupled to the second terminal of the second transistor [directly through 224 to M3], and having a second input [VOM] coupled to the second terminal of the third transistor [indirectly through 226/M5 to M6].
Regarding Claim 2, Gupta discloses the circuitry of claim 1, further comprising: an attenuator [202] coupled to the first and second inputs, and having outputs coupled to the first terminals of the second and third resistors.
Regarding Claim 4, as best understood, Gupta discloses the circuitry of claim 1, wherein the second circuit further comprises: a first load device [R8] having a first terminal coupled to the second terminal of the second transistor [directly coupled through 224 to M3], and having a second terminal; and a second load device [R9] having a first terminal coupled to the second terminal of the third transistor [indirectly coupled through 226/M5 to M6], and having a second terminal coupled to the second terminal of the first load device [directly coupled to R8].
Regarding Claim 8, Gupta discloses the circuitry of claim 1, further comprising: a pulse filter [240], having an input coupled to an output of the first comparator, and having an output; and a wake-up monitor logic [paragraph 0021-0023; "The wake-up circuit 112 detects the logic levels of the pulses to confirm characteristics ..."], having an input coupled to the output of the pulse filter [filter and detection within 240].
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mori et al. (US 20120051241 A1), in view of Gupta; hereinafter Mori, in view of Gupta.
Regarding Claim 17, Mori discloses a controller area network (CAN) transceiver [Fig. 3A], comprising: a transmitter [15], having first and second outputs [TR1/TR2] coupled to first and second bus terminals [CANH/CANL], respectively; a receiver [16], having first and second inputs coupled to the first and second bus terminals, respectively; and a wake-up receiver [18]. Mori does not explicitly disclose the wake-up circuit comprising: an attenuator, having first and second inputs coupled to the first and second bus terminals, respectively, and first and second outputs; a gain stage, comprising: a first transistor, having first and second terminals and a control terminal, the second terminal coupled to the control terminal; a first resistor, having a first terminal coupled to the second terminal of the first transistor, and having a second terminal; a first current source, coupled to the second terminal of the first resistor; a second transistor having first and second terminals, and having a control terminal coupled to the second terminal of the first resistor; a second resistor having a first terminal coupled to the second terminal of the second transistor, and having a second terminal coupled to a power supply terminal; a third transistor having first and second terminals, and having a control terminal coupled to the first terminal of the first resistor; a third resistor having a first terminal coupled to the second terminal of the third transistor, and having a second terminal; a fourth resistor having a first terminal coupled to the first output of the attenuator and to the first terminal of the second transistor, and having a second terminal; and a fifth resistor having a first terminal coupled to the second output of the attenuator and to the first terminal of the third transistor, and having a second terminal coupled to the first terminal of the first transistor and to the second terminal of the fourth resistor; a first comparator, having a first and second inputs coupled to the second terminals of the second and third transistors, respectively, and having an output; a pulse filter having an input and an output, the input coupled to the output of the first comparator; and a wake-up monitor logic, having an input coupled to the output of the pulse filter.
However, Gupta discloses a wake-up receiver [112/200] comprising: an attenuator [114/202], having first and second inputs coupled to the first and second bus terminals [203/205], respectively, and first and second outputs [204/206]; a gain stage [116/118 and 212/222], comprising: a first transistor [M2], having first and second terminals and a control terminal, the second terminal coupled to the control terminal [indirectly coupled through M1]; a first resistor [R6], having a first terminal coupled to the second terminal of the first transistor [indirectly coupled through R7/M1], and having a second terminal; a first current source [216], coupled to the second terminal of the first resistor [indirectly coupled through D1/R5]; a second transistor [M3], having first and second terminals, and having a control terminal coupled to the second terminal of the first resistor [indirectly coupled through R5]; a second resistor [R8], having a first terminal coupled to the second terminal of the second transistor [directly through 224], and having a second terminal coupled to a power supply terminal [VDD indirectly coupled through D2]; a third transistor [M6], having first and second terminals, and having a control terminal coupled to the first terminal of the first resistor [indirectly coupled through R7]; a third resistor [M9], having a first terminal coupled to the second terminal of the third transistor [indirectly coupled through M5], and having a second terminal; a fourth resistor [R7], having a first terminal coupled to the first output of the attenuator [indirectly coupled through M1/M2 to 204] and to the first terminal of the second transistor [indirectly coupled through M1/M2/M4 to M3], and having a second terminal; and a fifth resistor [R5], having a first terminal coupled to the second output of the attenuator [indirectly coupled through M5/M6 to 206] and to the first terminal of the third transistor [indirectly coupled through M5], and having a second terminal coupled to the first terminal of the first transistor [indirectly coupled through M3/M4 to M2] and to the second terminal of the fourth resistor [indirectly coupled through M3/M4 to R7]; a first comparator [232], having a first and second inputs coupled to the second terminals of the second and third transistors [VOP directly coupled to M3; VOM indirectly coupled through M5 to M6], respectively, and having an output [224]; a pulse filter [240] having an input [224] and an output [241], the input coupled to the output of the first comparator [WUP_OUT]; and a wake-up monitor logic [paragraph 0021-0023; "The wake-up circuit 112 detects the logic levels of the pulses to confirm characteristics ..."], having an input coupled to the output of the pulse filter [filter and detection within 240]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Gupta in the invention of Mori, with the expected benefit of detecting when a valid wake-up pattern is received from the CAN bus and providing a wake-up signal in response to detecting a valid wake-up pattern [paragraph 0021]. This method of improving Mori using Gupta was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Gupta. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mori and Gupta to obtain the invention: incorporating the wake-up receiver, pulse filter, and wake-up monitor logic within the CAN transceiver.
Regarding Claim 20, Mori, in view of Gupta, discloses the transceiver of claim 17, wherein the attenuator comprises: a ninth resistor [Gupta, R1] having a first terminal coupled to the first input [Gupta, directly coupled to 203], and a second terminal coupled to the first terminal of the fourth resistor [Gupta, indirectly coupled through M2/M1 to R7]; a tenth resistor [Gupta, R2] having a first terminal coupled to the second input [Gupta, directly coupled to 205], and a second terminal coupled to the first terminal of the fifth resistor [Gupta, indirectly coupled through M6/M5 to R5]; and an eleventh resistor [Gupta, R3] having a first terminal coupled to the second terminal of the ninth resistor [Gupta, directly coupled to R1], and having a second terminal coupled to the second terminal of the tenth resistor [Gupta, indirectly coupled through R4 to R2].
Allowable Subject Matter
Claims 3, 5-7, 9-11, 18-19, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12-16 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 3, Gupta discloses the circuitry of claim 2, wherein the attenuator comprises: a fourth resistor [R1] having a first terminal coupled to the first input, and having a second terminal coupled to the first terminal of the second resistor; and a fifth resistor [R2] having a first terminal coupled to the second input, and having a second terminal coupled to the first terminal of the third resistor. The prior art of record does not disclose nor render obvious wherein a sixth resistor having a first terminal coupled to the second terminal of the fourth resistor, and having a second terminal coupled to the second terminal of the fifth resistor, as cited with the rest of the claimed limitation.
Regarding Claim 5, Gupta discloses the circuitry of claim 1, further comprising a third circuit [112], the third circuit comprising: a fourth circuit [500], comprising: a fourth transistor [M21], and having a second terminal and a control terminal; a fifth transistor [M23], having a first terminal coupled to the second terminal of the fourth transistor [directly coupled], and having a second terminal and a control terminal; a seventh resistor [R15], having a first terminal coupled to the second terminal of the fifth transistor [directly coupled], and having a second terminal; a second current source [518], having a first terminal coupled to the second terminal of the seventh resistor [directly coupled]. The prior art of record does not disclose nor render obvious wherein the fourth transistor, having a first terminal coupled to the second terminals of the second and third resistors; the second current source having a first terminal coupled to the control terminal of the fifth transistor; a fifth circuit, comprising: a sixth transistor, having a first terminal coupled to the first input and to the first terminal of the second resistor, and having a second terminal and a control terminal; a seventh transistor, having a first terminal coupled to the second input and to the first terminal of the third resistor, having a second terminal, and having a control terminal coupled to the control terminal of the sixth transistor; an eighth transistor, having a first terminal, having a second terminal, and having a control terminal coupled to its second terminal; a ninth transistor having a first terminal coupled to the second terminal of the sixth transistor, having a second terminal coupled to the second terminal of the eighth transistor, and having a control terminal coupled to the first terminal of the seventh resistor; and a tenth transistor having a first terminal coupled to the second terminal of the seventh transistor, having a second terminal coupled to the second terminal of the eighth transistor, and having a control terminal coupled to the second terminal of the seventh resistor; and a differential amplifier, having first and second inputs coupled to the second terminals of the ninth and tenth transistors, respectively, and having first and second outputs coupled to the first and second inputs of the first comparator, as cited with the rest of the claimed limitation. Dependent claims 6-7 are allowed.
Regarding Claim 9, the prior art of record does not disclose nor render obvious wherein the pulse filter comprises: a logic circuitry, having a first input coupled to the output of the first comparator; a thirteenth transistor, having a first terminal, having a second terminal, and having a control terminal coupled to an output of the logic circuitry; a second comparator, having an output coupled to a second input of the logic circuitry and to an input of the wake-up monitor logic; an eighth resistor, having a first terminal coupled to the second terminal of the thirteenth transistor, and having a second terminal; a first capacitor, having a first terminal coupled to the second terminal of the eighth resistor and to a first input of the second comparator, and having a second terminal; a ninth resistor, having a first terminal coupled to the second terminal of the thirteenth transistor, and having a second terminal; and a second capacitor, having a first terminal coupled to the second terminal of the ninth resistor and to a second input of the second comparator, and having a second terminal, as cited with the rest of the claimed limitation. Dependent claims 10-11 are allowed.
Regarding Claim 18, the prior art of record does not disclose nor render obvious wherein the pulse filter comprises: a logic circuitry having a first input coupled to the output of the first comparator; a fourth transistor, having a first terminal, a second terminal, and a control terminal coupled to an output of the logic circuitry; a second comparator, having first and second inputs, and an output coupled to a second input of the logic circuitry; a sixth resistor, having a first terminal coupled to the second terminal of the fourth transistor, and a second terminal; a first capacitor, having a first terminal coupled to the second terminal of the sixth resistor and to the first input of the second comparator, and a second terminal; a seventh resistor, having a first terminal coupled to the second terminal of the fourth transistor, and a second terminal; and a second capacitor, having a first terminal coupled to the second terminal of .the seventh resistor and to the second input of the second comparator, and a second terminal, as cited with the rest of the claimed limitation. Dependent claim 21 is allowed.
Regarding Claim 19, Mori, in view of Gupta, discloses the transceiver of claim 17, wherein the gain stage further comprises: a fifth transistor [Gupta, M5], having a first terminal coupled to the second terminals of the fourth and fifth resistors, and having a second terminal and a control terminal; a sixth transistor [Gupta, M1], having a first terminal coupled to the second terminal of the fifth transistor, and having a second terminal and a control terminal; and a seventh transistor [Gupta, M4], having a first terminal coupled to the first output of the attenuator and to the first terminal of the fourth resistor, and having a second terminal and a control terminal. The prior art of record does not disclose nor render obvious wherein the gain stage further comprises: an eighth resistor, having a first terminal coupled to the second terminal of the sixth transistor, and having a second terminal; a second current source, having a first terminal coupled to the second terminal of the eighth resistor; an eighth transistor, having a first terminal coupled to the second output of the attenuator and to the first terminal of the fifth resistor, having a second terminal, and having a control terminal coupled to the control terminal of the seventh transistor; a ninth transistor, having a first terminal coupled to the second terminal of the seventh transistor, having a second terminal, and having a control terminal coupled to the first terminal of the eighth resistor; a tenth transistor, having a first terminal coupled to the second terminal of the eighth transistor, having a second terminal, and having a control terminal coupled to the second terminal of the eighth resistor; an eleventh transistor, having a first terminal, having a second terminal coupled to the second terminals of the ninth and tenth transistors, and having a control terminal coupled to its second terminal; and a differential amplifier, having first and second inputs coupled to the second terminals of the tenth and eleventh transistors, respectively, and having first and second outputs coupled to the first and second inputs of the first comparator, as cited with the rest of the claimed limitation.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Aarey et al (US 20180351765 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Amit R Bhatia/Examiner, Art Unit 2836
/REGIS J BETSCH/SPE, Art Unit 2836
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