DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to RCE filed on 07/21/2026. Claims 1-20 have been examined and are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/21/2026 has been entered.
Response to Arguments
Applicant’s arguments, filed 06/19/2026, with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
A new reference NPL Pourshirazi et al. “Refree: A Refresh-Free Hybrid DRAM/PCM Main Memory System” 2016 IEEE International Parallel and Distributed Processing Symposium, 2016, pp. 566-575, is cited in this Office Action necessitated by the amendment.
An interview was held on 07/31/2026 between the Examiner and the Applicant’s representative. During the interview, it was agreed that the 35 U.S.C. 112(b), pre-AIA second paragraph, rejection of claims 1-20 would be withdrawn. The Examiner withdraws the rejection.
In view of the new reference, independent claims 1, 13, and 14 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 12-14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Meier et al. US 2022/0148645 (“Meier”) in view of NPL Pourshirazi et al. “Refree: A Refresh-Free Hybrid DRAM/PCM Main Memory System” 2016 IEEE International Parallel and Distributed Processing Symposium, 2016, pp. 566-575 (“Pourshirazi”).
As per independent claim 1, Meier teaches A memory device (“the apparatus 100 can include a memory device or system,” para 0019 and FIG. 1A), comprising:
a memory array comprising memory rows (“The apparatus 100 may include an array of memory cells, such as memory array 150.” Para 0022 and FIGS. 1B), wherein each of the memory rows comprises memory cells coupled to one word line (“The memory array 150 may include a plurality of banks … and each bank may include a plurality of word lines (WL),” para 0022 and FIG. 1B);
a peripheral circuit coupled to the memory array (“The apparatus 100 can include a refresh control circuit 180 configured to control refreshing of the information of the corresponding memory cell MC.” Para 0033 and FIG. 1B) and configured to:
perform a read operation of a first memory row of the memory rows in response to a read command (“Read data can be read from memory cells in the memory array 150 designated by row address (e.g., address provided with an active command) and column address (e.g., address provided with the read). The read command may be received by the command decoder 115,” para 0026);
determine, in response to the read command (“read command may be received by the command decoder 115,” para 0026 and FIG. 1B), whether address information same as first address information of the first memory row corresponding to the read command exists in a refresh table (“The tracking circuit 252 can track/store addresses (e.g., RXADD and/or the HitXADD [FIG. 2A and para 0044]) that have been identified internally … for future or upcoming disturb mitigation and service. The tracking circuit 252 can remove the addresses once the corresponding location is serviced/refreshed.” Para 0048. The claimed “refresh table” is being interpreted as storage locations storing “memory refresh addresses” which is equivalent to the tracking circuit 252 storing refresh addresses including, for example, RXADD and HitXADD. The claimed “determine” whether the address exists in the refresh table is implicitly taught because the tracking circuit 252 removes the address from the storage when the corresponding location is serviced/refreshed),
wherein the refresh table stores pieces of address information (“The tracking circuit 252 can track/store addresses (e.g., RXADD and/or the HitXADD [FIG. 2A and para 0044]) that have been identified internally … for future or upcoming disturb mitigation and service.” Para 0048), and each piece of the address information corresponds to one of the memory rows (“the refresh control circuit 180 can receive the decoded row address signal (XADD) from the address decoder 110,” para 0033 and FIG. 1B);
delete the address information same as the first address information from the refresh table in response to the address information same as the first address information existing in the refresh table (“The tracking circuit 252 can track/store addresses (e.g., RXADD and/or the HitXADD [FIG. 2A and para 0044]) that have been identified internally … for future or upcoming disturb mitigation and service. The tracking circuit 252 can remove the addresses once the corresponding location is serviced/refreshed.” Para 0048).
Meier does not explicitly teach “and without performing a refresh of the first memory row after performing the read operation”. However, it is well-known in the art that a read operation of a DRAM performs refresh of the memory cell of the DRAM that is being read. In fact, paragraph [0063] of the instant filed specification admits that a refresh operation is not performed following a read operation “to avoid repetitive refresh of the memory row”. Hence, Meier inherently teaches that a refresh operation is not performed following a read operation of a memory cell. Nevertheless, in the interest of advancing prosecution, the new reference with explicit teaching is cited in this Office Action.
Pourshirazi teaches and without performing a refresh of the first memory row after performing the read operation (“a recently accessed row has already been ‘refreshed’ by the access and does not need to be refreshed” page 567 col 1 lines 12-14).
Given the teaching of Pourshirazi, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Meier with “and without performing a refresh of the first memory row after performing the read operation”. The motivation would be that refresh operations add significant power and performance overheads to a system, page 567, col 2 lines 29-30 of Pourshirazi, and avoiding a refresh operation would save power and improve performance.
As per dependent claim 3, Meier in combination with Pourshirazi discloses the device of claim 1. Meier teaches wherein the peripheral circuit is further configured to: determine whether address information of a memory row adjacent to the first memory row exists in the refresh table (“the row address (RXADD) can be a victim address, such as for the word line (WL) adjacent to or within a predetermined distance from the word line (WL) accessed by the aggressor address.” Para 0044. “The tracking circuit 252 can track/store addresses (e.g., RXADD and/or the HitXADD) that have been identified internally … for future or upcoming disturb mitigation and service. The tracking circuit 252 can remove the addresses once the corresponding location is serviced/refreshed.” Para 0048);
insert the address information of the memory row adjacent to the first memory row into the refresh table in response to the address information of the memory row adjacent to the first memory row not existing in the refresh table (“the tracking circuit 252 can generate the tracking output 262 as a flag that indicates whether new addresses have been logged for upcoming disturb mitigation. … the flag can be used to indicate whether a refresh management operation is needed (e.g., when new addresses are stored) or not (e.g., when no new addresses have been stored) according to the tracked addresses.” Para 0048).
Meier is silent about “priority” of refresh addresses. Hence, Meier does not explicitly teach “adjust priority of the address information of the memory row adjacent to the first memory row in the refresh table in response to the address information of the memory row adjacent to the first memory row existing in the refresh table”.
However, Meier teaches “adjust schedules of upcoming internally-initiated disturb mitigation operations,”. Para 0037. Note that priority of refresh addresses determines when a refresh operation of an address is scheduled to execute (for example, see dependent claim 2). Thus, when Meier adjusts schedules of disturb mitigation operations, Meier is essentially adjusting when the disturb mitigation operation (i.e., refresh operation) is going to take place and hence Meier is adjusting the priority.
Hence, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Meier with “adjust priority of the address information of the memory row adjacent to the first memory row in the refresh table in response to the address information of the memory row adjacent to the first memory row existing in the refresh table”. The motivation would be that the invention compensates for charge loss on word lines that are adjacent to an heavily activated word line, para 0014 of Meier.
As per dependent claim 12, Meier in combination with Pourshirazi discloses the device of claim 1. Meier teaches wherein the peripheral circuit comprises: a control logic (“row disturb detection circuit 200 (e.g., a portion of the refresh control circuit 180 of FIG. 1B)” para 0038 and FIG. 2A);
a comparison circuit coupled to the control logic (“comparator circuits XOR_1 to XOR_n,” para 0042 and FIG. 2A) and configured to:
acquire, in response to the read command, individual pieces of address information in the refresh table (“The row addresses (XADD) latched by the flip-flop circuits FF_1 to FF_n” para 0042 and FIG. 2A), and compare the first address information with the individual pieces of address information one by one to generate a comparison result (“The match signal (Match)” para 0043 and FIG. 2A);
send the comparison result to the control logic (“The match signal (Match) and the first sampling signal (S1) can be supplied to an AND 208.” Para 0043 and FIG. 2A);
the control logic is configured to: determine, according to the comparison result, whether the address information same as the first address information exists in the refresh table (“The latch circuit 210 can output the latched result to a control circuit 220 as a row address (HitXADD) that corresponds to the word line WL having a high access frequency (e.g., the RH event).” Para 0044 and FIG. 2A);
delete the first address information from the refresh table in response to the address information same as the first address information existing in the refresh table (“The tracking circuit 252 can remove the addresses once the corresponding location is serviced/refreshed.” Para 0048).
As per independent claim 13, this claim is rejected based on arguments provided above for similar rejected independent claim 1. “The apparatus 100 can be electrically coupled to an apparatus controller 102 (e.g., a memory controller,” para 0020 and FIG. 1A of Meier.
As per independent claim 14, this claim is rejected based on arguments provided above for similar rejected independent claim 1.
As per dependent claim 16, this claim is rejected based on arguments provided above for similar rejected dependent claim 3.
Claims 2 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Meier in view of Pourshirazi and in further view of Kang et al. US 2022/0270662 (“Kang”).
As per dependent claim 2, Meier in combination with Pourshirazi discloses the device of claim 1. Meier teaches and delete the address information with the highest priority from the refresh table after the refresh operation (“The tracking circuit 252 can remove the addresses once the corresponding location is serviced/refreshed.” Para 0048).
Meier may not explicitly disclose, but in an analogous art in the same field of endeavor, Kang teaches wherein the pieces of address information are sorted by priority, and the peripheral circuit is further configured to: perform a refresh operation on a corresponding memory row according to address information with a highest priority in the refresh table (“the refresh address ADD2 may be any one word line address having a highest refresh priority” para 0065).
Given the teaching of Kang, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Meier and Pourshirazi with “wherein the pieces of address information are sorted by priority, and the peripheral circuit is further configured to: perform a refresh operation on a corresponding memory row according to address information with a highest priority in the refresh table”. The motivation would be that the invention improves product performance by simultaneously performing an activation operation and a refresh operation, para 0007 of Kang.
As per dependent claim 15, this claim is rejected based on arguments provided above for similar rejected dependent claim 2.
Claims 4-11 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Meier in view of Pourshirazi and in further view of Park et al. US 2014/0112086 (“Park”).
As per dependent claim 4, Meier in combination with Pourshirazi discloses the device of claim 3. Meier and Pourshirazi do not explicitly teach “wherein the refresh table comprises a first sub-table and a second sub-table, and priority of address information in the first sub-table is higher than priority of address information in the second sub-table”.
However, in an analogous art in the same field of endeavor, Park teaches wherein the refresh table comprises a first sub-table and a second sub-table (“The first sub-array may include a first refresh address table 332d, and the second sub-array may include a second refresh address table 334d.” Para 0123 and FIG. 14).
Given the teaching of Park, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Meier and Pourshirazi with “wherein the refresh table comprises a first sub-table and a second sub-table”. The motivation would be that the invention adaptively performs refresh operation according to a data retention characteristic of each memory cell, para 0006, thereby preventing any data loss.
Park does not explicitly teach “priority of address information” and hence does not teach “and priority of address information in the first sub-table is higher than priority of address information in the second sub-table”.
However, Park teaches “the table-based refresh for each of the memory rows 290 may be performed once per tREF, … the table-based refresh for each of the memory cell rows 270 may be performed twice per tREF.” Para 0044 and FIG. 3. That is, refresh addresses associated with rows 270 have a higher priority (must be done twice as often) than refresh addresses associated with rows 290.
Hence, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Park with “and priority of address information in the first sub-table is higher than priority of address information in the second sub-table”. The motivation would be that the invention adaptively performs refresh operation according to a data retention characteristic of each memory cell, para 0006, thereby preventing any data loss.
As per dependent claim 5, Meier in combination with Pourshirazi and Park discloses the device of claim 4. Meier teaches wherein the peripheral circuit is further configured to: insert the address information of the memory row adjacent to the first memory row into the second sub-table in response to the address information of the memory row adjacent to the first memory row not existing in the refresh table (“the row address (RXADD) can be a victim address, such as for the word line (WL) adjacent to or within a predetermined distance from the word line (WL) accessed by the aggressor address.” Para 0044. Park teaches a plurality of refresh address sub-tables, para 0123 and FIG. 14).
Meier and Pourshirazi may not explicitly disclose, but Park teaches wherein priority of the address information of the memory row adjacent to the first memory row is a highest priority in the second sub-table (“the table-based refresh for each of the memory rows 290 may be performed once per tREF, … the table-based refresh for each of the memory cell rows 270 may be performed twice per tREF.” Para 0044 and FIG. 3. That is, refresh addresses associated with rows 270 have a higher priority (must be done twice as often) than refresh addresses associated with rows 290).
The same motivation that was utilized for combining Meier and Park as set forth in claim 4 is equally applicable to claim 5.
As per dependent claim 6, Meier in combination with Pourshirazi and Park discloses the device of claim 5. Meier teaches wherein the memory row adjacent to the first memory row comprises a second memory row and a third memory row, and the peripheral circuit is further configured to: insert second address information corresponding to the second memory row and third address information corresponding to the third memory row into the second sub-table in response to address information same as the second address information and address information same as the third address information not existing in the refresh table (“victim rows adjacent to the accessed row” para 0076).
Meier and Pourshirazi may not explicitly disclose, but Park teaches wherein priority of the second address information is the highest priority in the second sub-table, and priority of the third address information is a second highest priority in the second sub-table (“the table-based refresh for each of the memory rows 290 may be performed once per tREF, … the table-based refresh for each of the memory cell rows 270 may be performed twice per tREF.” Para 0044 and FIG. 3. That is, refresh addresses associated with rows 270 have a higher priority (must be done twice as often) than refresh addresses associated with rows 290); or
priority of the second address information is the second highest priority in the second sub-table, and priority of the third address information is the highest priority in the second sub-table (“the table-based refresh for each of the memory rows 290 may be performed once per tREF, … the table-based refresh for each of the memory cell rows 270 may be performed twice per tREF.” Para 0044 and FIG. 3. That is, refresh addresses associated with rows 270 have a higher priority (must be done twice as often) than refresh addresses associated with rows 290).
The same motivation that was utilized for combining Meier and Park as set forth in claim 5 is equally applicable to claim 6.
As per dependent claim 7, Meier in combination with Pourshirazi and Park discloses the device of claim 4. Meier and Pourshirazi may not explicitly disclose, but Park teaches wherein the peripheral circuit is further configured to: adjust priority of the address information of the memory row adjacent to the first memory row to a highest priority in the first sub-table in response to the address information of the memory row adjacent to the first memory row existing in the first sub-table (“the table-based refresh for each of the memory rows 290 may be performed once per tREF, … the table-based refresh for each of the memory cell rows 270 may be performed twice per tREF.” Para 0044 and FIG. 3. That is, refresh addresses associated with rows 270 have a higher priority (must be done twice as often) than refresh addresses associated with rows 290).
The same motivation that was utilized for combining Meier and Park as set forth in claim 4 is equally applicable to claim 7.
As per dependent claim 8, Meier in combination with Pourshirazi and Park discloses the device of claim 4. Meier and Pourshirazi may not explicitly disclose, but Park teaches wherein the peripheral circuit is further configured to: move the address information of the memory row adjacent to the first memory row into the first sub-table in response to the address information of the memory row adjacent to the first memory row existing in the second sub-table (“the table-based refresh for each of the memory rows 290 may be performed once per tREF, … the table-based refresh for each of the memory cell rows 270 may be performed twice per tREF.” Para 0044 and FIG. 3. That is, refresh addresses associated with rows 270 have a higher priority (must be done twice as often) than refresh addresses associated with rows 290).
The same motivation that was utilized for combining Meier and Park as set forth in claim 4 is equally applicable to claim 8.
As per dependent claim 9, Meier in combination with Pourshirazi and Park discloses the device of claim 8. Meier and Pourshirazi may not explicitly disclose, but Park teaches wherein priority of the address information of the memory row adjacent to the first memory row is a lowest priority in the first sub-table (“the table-based refresh for each of the memory rows 290 may be performed once per tREF, … the table-based refresh for each of the memory cell rows 270 may be performed twice per tREF.” Para 0044 and FIG. 3. That is, refresh addresses associated with rows 270 have a higher priority (must be done twice as often) than refresh addresses associated with rows 290).
The same motivation that was utilized for combining Meier and Park as set forth in claim 8 is equally applicable to claim 9.
As per dependent claim 10, Meier in combination with Pourshirazi and Park discloses the device of claim 5. Meir does not explicitly teach the number of pieces of stored addresses reaching a threshold and therefore does not explicitly teach “wherein the peripheral circuit is further configured to: when a number of pieces of address information stored in the second sub-table is greater than a set threshold, delete at least one piece of address information in the second sub-table”.
However, Meier teaches “the apparatus controller 102 can simultaneously generate the RFM commands 272 for all devices/modules coupled to the corresponding controller channel 404, such as when a value tracked by the shared counter reaches a threshold value.” Para 0073.
Hence, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Meier with “wherein the peripheral circuit is further configured to: when a number of pieces of address information stored in the second sub-table is greater than a set threshold, delete at least one piece of address information in the second sub-table”. The motivation would be that the invention compensates for charge loss on word lines that are adjacent to an heavily activated word line, para 0014 of Meier.
As per dependent claim 11, Meier in combination with Pourshirazi and Park discloses the device of claim 10. Meir teaches wherein the peripheral circuit is configured to: delete address information in the second sub-table in order of priority, wherein address information with a lower priority is to be deleted earlier (“The tracking circuit 252 can remove the addresses once the corresponding location is serviced/refreshed.” Para 0048).
As per dependent claims 17-20, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 4-7.
Conclusion
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/MASUD K KHAN/Primary Examiner, Art Unit 2132
Prosecution Insights