Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
2. In the amendment filed on02/13/2026, the examiner acknowledges the following:
3. Claims 1 – 5, 7 – 8 and 10 – 14 were amended.
4. Claims 15 and 16 were added to the claim disclosure.
5. Claim language was amended as for claims 1, 3, 4, 11, 13 and 15 and the previous claim objections for English language are withdrawn by the Examiner.
6. Currently, claims 1 – 16 are pending and they are being considered for examination.
Response to Arguments
7. Applicant's arguments filed on February 13, 2026, have been fully considered and they were persuasive. On pages 9 – 11 , Applicant argues that Rhodes teaches a two-stage transfer gate for the charges generated by the photodiode to be transferred into the floating diffusion and that the instant application teaches only one transfer gate located between the photodiode and the floating diffusion. However, the Examiner found another art similar to Rhodes that includes one transfer gate transistor or transient gate as the current patent application and it will be used in combination with Rhodes art.
In conclusion, even though Applicant argued about the rejections and claims were amended. Claim 1 has the same disclosure as before, since Applicant just replaced the expression “capable of” by configured to”, which one and the same thing. Claims 1, 11, 13 and 14 are they are right now are not allowable. Therefore, Rhodes art still good art and it will be used wherever it applies.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over “Howard Rhodes, US 2009/0294632 A1, hereinafter Rhodes” in view of “Thomas Ayers et al., US 2013/0021466 A1, hereinafter Ayers”.
Regarding Claims 1, 11, 13 and 14:
Rhodes teaches an image sensor, comprising: an array of pixels formed using a substrate, wherein each of the pixels in the array include: a photosensitive region formed in the substrate; a storage gate transistor coupled to the photosensitive region; a transfer gate transistor coupled to the storage gate; a floating diffusion region coupled to transfer gate transistor; an amplifier coupled to the floating diffusion region to amplify a voltage of the floating diffusion region; and a global reset transistor that is coupled to the floating diffusion region, wherein the global reset transistor includes a gate that is coupled to receive a global reset signal to reset the pixel, wherein the photosensitive region comprises a diode formed by an P-well in a N-type substrate, wherein the storage gate transistor, the transfer gate transistor, are coupled to be activated in response to the global reset signal and, further comprising a barrier gate transistor coupled between the storage gate transistor and the photosensitive region.
Ayers teach an image sensing device comprising: an array of light sensing elements, each light sensing element comprising a photodiode and a plurality of control transistors, the plurality of control transistors comprising at least a transfer gate transistor and a reset transistor, the transfer gate transistor having a drain terminal being a floating diffusion node and a source terminal coupled to the photodiode, the reset transistor having a drain terminal coupled to a reset level voltage and a source terminal coupled to the floating diffusion node, wherein each light sensing element generates an output pixel voltage indicative of an intensity level of light impinging on the photodiode, and the plurality of control transistors are configured to control reset, light integration, charge transfer and data read operations of each light sensing element; and wherein the light sensing element is configured to selectively operate in a first operation mode for high conversion gain or a second operation mode for low conversion gain, the reset level voltage being a positive power supply voltage in the first operation mode and the reset level voltage being a voltage slightly less than a pinning voltage of the photodiode in the second operation mode; and in the second operation mode, the photodiode and the floating diffusion node are reset to about the same voltage potential and are reset to a voltage potential below the pinning voltage during the reset operation of the light sensing element, wherein in the second operation mode, during the charge transfer operation with the transfer gate transistor is turned on, charge collected at the photodiode from the impinging light equilibrating between the photodiode and the floating diffusion node.
As for claims 1 and 13:
Rhodes teaches for claims 1 and 13:
A solid-state imaging device (Fig 1, sample image sensor 100. See [0020]) comprising: a pixel part having pixels arranged therein (Fig 1, pixel array 110. See [0020]), each pixel being configured to perform photoelectric conversion (Fig 2, one pixel shared structure 200. See [0021]), wherein each pixel includes:
a photoelectric conversion element for generating photocharges by photoelectric conversion (Fig 2 210. See [0021]); a floating diffusion (FD) to which the photocharges generated by the photoelectric conversion element are transferred (Fig 2, floating diffusion region 214. See [0026]); and
wherein the FD and the photoelectric conversion element are coupled by the first transient gate, and the photocharges generated by the photoelectric conversion element are transferred immediately to the FD (Fig 2, the FD 214 and the photodiode 210 are coupled by the transfer gate transistor TG with gate 226 and the charges generated by the photodiode 210 are transferred to the FD 214. See [0026]).
Even though, Rhodes teaches several limitations of claim 1, Rhodes fails to teach or to fairly suggest “a first transient gate formed between the FD and the photoelectric conversion element and capable of controlling a charge transfer path between the FD and the photoelectric conversion element”, which in the same field of endeavor is taught by Ayers. As shown above, Ayers teaches an image sensing device comprising: an array of light sensing elements, each light sensing element comprising a photodiode and a plurality of control transistors, the plurality of control transistors comprising at least a transfer gate transistor and a reset transistor, the transfer gate transistor having a drain terminal being a floating diffusion node and a source terminal coupled to the photodiode. Ayers Fig 3 shows photodiode PD and the transfer gate TG directly formed between the PD and the floating diffusion, wherein the transfer gate transistor is controlled by a transfer gate signal (Tg), which is aet to a high level (See [0027; 0028; 0029]). Additionally, Ayers Fig 6 shows the potential of a 4T pixel circuit of Fig 3 when operating in the high conversion gain CG mode according to his invention. Fig 6( c ) shows the transfer gate signal Tg is asserted and the charge collected by the PD are transferred to the floating diffusion FD through the channel of the transfer gate transistor. The transfer gate signal Tg is boosted to a voltage greater than VDD. Fig 6 shows that it is possible to operate a 4T pixel circuit as in Fig 3 under high conversion gain CG, where the floating diffusion capacitance is minimized as to optimize the sensitivity of the pixel (See [0037; 0038])
By modifying Rhodes by using one transfer gate transistor as taught by Ayers instead the two elements as used by Rhodes when transferring the charges for the photodiode to the floating diffusion, which would simplify the pixel circuit and to be able to operate it in a high conversion gain mode, which optimize the pixel sensitivity (See Ayers [0038]).
Regarding Claim 13:
Claim 13 pertains to the method steps as to operate the solid-state imaging device of claim 1. In order to operate an image device as disclosed in claim 1, it would have necessitated to perform the steps as disclosed in claim 13. The limitations of claim 13 are similar to the ones disclosed in claim 1 (See the rejection above for more details). As for the method, Rhodes claims 11 – 13 disclose the method for operating an image device. Ayers claims 16 – 20 disclose a method of operation for his image device.
Regarding Claim 11:
The rejection of claim 1 is incorporated herein. As for claim 11 limitations, Rhodes teaches in Fig 2, a global reset transistor formed using regions 216 and 214 by forming the global reset gate 228. It controls flow of electrons from the reset voltage VRST region 216 to floating diffusion region FD 214 when the pixel is being globally reset (See [0027]). Fig 5 shows an example of signal FDX conveys the buffered floating diffusion voltage (See [0045]). Fig 5 shows the comparator, wherein a first and a second sampled voltage are compared to generate a signal for the difference of the charges stored in capacitors 512 and 522 (See [0040]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over “Howard Rhodes, US 2009/0294632 A1, hereinafter Rhodes” in view of “Thomas Ayers et al., US 2013/0021466 A1, hereinafter Ayers” and in further view of “Hirofumi Sumi, US 2014/0160332 A1, hereinafter Sumi”.
Regarding Claim 14:
Claim 14 pertains to and electronic apparatus with the same elements as disclosed in claim 1 with an optical system for forming a subject image on the solid-state device. Rhodes teaches all limitations of claim 14 but it did not mention an optical system, which is well known in the art. Ayers teaches an imaging device with similar elements as claim 1 As for that matter see Sumi Fig 16, which is very similar to Fig 13 of the instant application. Sumi Fig 16 shows camera system 400 has an imaging device 410, an optical system/lens 420, a signal processor circuit 440 and a drive circuit 330 (See [0177 – 0179]).
By adding an optical system to the image sensor of the combination of Rhodes and Ayers, that would produce the electronic device as disclosed in claim 14.
Claim Objections – Allowable Subject Matter
9. Claims 3, 5 – 10 and 15 – 16 are objected because its dependence to a base rejected claim; however, they would be allowable if written in an independent form.
Claims 2, 4 and 12 are allowed, since the prior art of record does not teach them.
Conclusion
10A. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
10B. The prior art is made of record and not relied upon is considered pertinent to applicant’s disclosure.
1. T. Ayers et al., US 2013/0020466 A1 – it teaches an image sensor including an array of pixel elements is operated according to two operation modes to modulate the conversion gain of the pixel to operate the image sensor based on the impinging light conditions. More specifically, an image sensor pixel element is operated in a high conversion gain mode for low light conditions and in a low conversion gain mode for bright light conditions. The low conversion gain mode implements charge sharing between the floating diffusion and the photodiode. The low conversion gain mode further implements partial reset where the photodiode and the floating diffusion are reset to the same potential and to a potential slightly less than the pinning voltage of the photodiode.
Contact
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARLY S.B. CAMARGO whose telephone number is (571)270-3729. The examiner can normally be reached on M-F 8:00-5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MARLY S CAMARGO/Primary Examiner, Art Unit 2638
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