DETAILED ACTION
Claims 1-3, 5-12 and 14-19 are pending in this action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1, 3, 5-10, 12 and 14-19 and are rejected under 35 U.S.C. 103 as being unpatentable Nardi et al. (US PGPUB No. 2020/0401534) [hereinafter “Nardi”] in view of Lin et al. (US PGPUB No. 2008/0062802) [hereinafter “Lin”] in further view of Gupta et al. (US PGPUB No. 2023/0291541) [hereinafter “Gupta”] in further view of Weingarten (US PGPUB No. 2011/0246792).
As per claim 1, Nardi teaches a system for configuring a data structure in a nonvolatile memory module, comprising: a non-transitory memory having instructions stored thereon; a processor configured to execute the instructions to perform an operation on a nonvolatile memory (NVM) module, wherein the NVM module includes at least one memory cell comprising two transistors coupled to each other such that a logic value is stored in a complementary manner ([0040], logical values stored in bits which may be implemented as transistors see [0079]), the operation including: encrypting the at least one memory cell by generating a cipher text (CT) by performing an XOR operation on plain text (PT) stored in the at least one memory cell ([0038], XOR operation performed on plaintext and key), and performing the XOR operation on a corresponding key ([0038], XOR operation performed on plaintext and key).
Nardi does not explicitly teach two transistors so as to form complementary threshold voltage states. Lin teaches two transistors so as to form complementary threshold voltage states (Fig. 1 and [0002], describing conventionally how SRAM uses transistors to form complimentary voltage states on two bit lines).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Nardi with the teachings of Lin, two transistors so as to form complementary threshold voltage states, to implement the properties required of a memory cell.
The combination of Nardi and Lin does not explicitly teach the operation as an in-situ operation of encrypting and decrypting (Examiner Note: Examiner’s understanding based on the specification, see [0057], is that “in-situ” means encrypting/decrypting at the memory cell directly – without sending to an external module). Gupta teaches the operation as an in-situ operation of encrypting and decrypting ([0023], client is equipped with an accelerator to perform in-memory operations that include encrypting/decrypting data and encoding/decoding data – also described as “in-situ” see Abstract and [0009]).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Nardi with the teachings of Lin, the operation as an in-situ operation of encrypting and decrypting, to improve performance be reducing latency associated with external encryption and encoding.
The combination of Nardi, Lin and Gupta does not explicitly teach decrypting cipher text (CT) of the at least one memory cell by applying a read voltage pattern to the two transistors, the read voltage pattern being based on a key. Weingarten teaches decrypting cipher text (CT) of the at least one memory cell by applying a read voltage pattern to the two transistors, the read voltage pattern being based on a key (Fig. 1 and [0030], decrypting information from a memory cell using a stream generated from a key that have a voltage pattern).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Nardi, Lin and Gupta with the teachings of Weingarten, decrypting cipher text (CT) of the at least one memory cell by applying a read voltage pattern to the two transistors, the read voltage pattern being based on a key, to provide a secure and efficient way to store logical values on a NVM memory for other processing including encryption/decryption.
As per claim 3, the combination of Nardi, Lin, Gupta and Weingarten teaches the system of claim 1, wherein: the two transistors are field-effect-transistors (Nardi; FETs) ([0105], MOS field-effect transistors).
As per claim 5, the combination of Nardi, Lin, Gupta and Weingarten teaches the system of claim 1, wherein: the NVM module includes at least one memory block comprising plural memory cells (Nardi; [0034], memory array in NVM comprising plural memory cells see [0003]).
As per claim 6, the combination of Nardi, Lin, Gupta and Weingarten teaches the system of claim 5, wherein: the NVM module includes plural memory blocks, and each memory cell within an individual memory block is associated with a key (Nardi; [0091], associated key for an associated NVM memory module where the associated key is stored in a single or multiple cells – stored interpreted to be a type of association [0092]).
As per claim 7, the combination of Nardi, Lin, Gupta and Weingarten teaches the system of claim 5, wherein: the plural memory cells is arranged in an array (Nardi; [0034], arranging NVM as a memory cell array).
As per claim 8, the combination of Nardi, Lin, Gupta and Weingarten teaches the system of claim 7, wherein: the plural memory cells is arranged as an AND array, a NAND array, or a NOR array (Nardi; [0034], memory array as NAND OR NOR memory cores each with plural memory cells see [0003]).
As per claim 9, the combination of Nardi, Lin, Gupta and Weingarten teaches the system of claim 1, wherein: after the CT, the processor is configured to execute the instructions to generate the PT by sensing current when a signal representative of the key is applied to the at least one memory cell (Nardi; [0045], receiving signal which triggers key retrieval and XOR operation to generate plaintext).
As per claim 10, the substance of the claimed invention is identical or substantially similar to that of claim 1. Accordingly, this claim is rejected under the same rationale.
As per claim 12, the substance of the claimed invention is identical or substantially similar to that of claim 3. Accordingly, this claim is rejected under the same rationale.
As per claim 14, the substance of the claimed invention is identical or substantially similar to that of claim 5. Accordingly, this claim is rejected under the same rationale.
As per claim 15, the substance of the claimed invention is identical or substantially similar to that of claim 6. Accordingly, this claim is rejected under the same rationale.
As per claim 16, the substance of the claimed invention is identical or substantially similar to that of claim 7. Accordingly, this claim is rejected under the same rationale.
As per claim 17, the substance of the claimed invention is identical or substantially similar to that of claim 8. Accordingly, this claim is rejected under the same rationale.
As per claim 18, the substance of the claimed invention is identical or substantially similar to that of claim 9. Accordingly, this claim is rejected under the same rationale.
As per claim 19, the substance of the claimed invention is identical or substantially similar to that of claim 1. Accordingly, this claim is rejected under the same rationale.
Claims 2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Nardi, Lin, Gupta and Weingarten in view of Tanikawa et al. (US PGPUB No. 2012/0163075) [hereinafter “Tanikawa”].
As per claim 2, the combination of Nardi, Lin, Gupta and Weingarten teaches the system of claim 1.
The combination of Nardi, Lin, Gupta and Weingarten does not explicitly teach wherein: the two transistors coupled to each other are two consecutively situated transistors. Tanikawa teaches wherein: the two transistors coupled to each other are two consecutively situated transistors ([0032], implementing serial transistors in memory storage).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Nardi, Lin, Gupta and Weingarten with the teachings of Tanikawa, wherein: the two transistors coupled to each other are two consecutively situated transistors, to provide a efficient way to store logical values on a NVM memory for other processing including encryption/decryption.
As per claim 11, the substance of the claimed invention is identical or substantially similar to that of claim 2. Accordingly, this claim is rejected under the same rationale.
Response to Arguments
With respect to the rejection of independent claims 1-20 under 35 U.S.C. 103, Applicant argues that claim 1 has been amended to add the decrypting feature which was previously an optional feature. Examiner has fully considered this amendment and agrees that the cited prior art references, Nardi, Lin and Gupta do not teach this feature however after reconsidering the cited reference used for dependent claims 4, 13 and 20, Weingarten, various sections of Weingarten appear to teach this decrypting feature. Examiner has added these citations to claim 1. Examiner notes that claims 4, 13 and 20 are now canceled.
In an effort to expedite prosecution, Examiner suggests including details regarding the two keys in the claim, i.e. where are they stored, and perhaps including a relationship between the two keys. Also, Examiner is open to conducting an after-interview to discuss other ideas for amending the claims that may move this application towards allowance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lea et al. (US Patent No. 10,049,721), Jain et al. (US Patent No. 10,073,733), Young et al. (US PGPUB No. 2019/0042159), Xu et al. ("Embedding Security into Ferroelectric FET Array via In-Situ Memory Operation," arXiv:2306.01863, June 2, 2023) and Lei et al. ("An eDRAM-Based In-Situ-Computing Processor for Homomorphic Encryption Evaluation on the Edge," 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), Bruges, Belgium, 2024, pp. 464-467, doi: 10.1109/ESSERC62670.2024.10719576) all disclose various aspects of the claimed invention including encryption/decryption using FET transistor read patterns.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER C SHAW whose telephone number is (571)270-7179. The examiner can normally be reached Max Flex.
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/PETER C SHAW/Primary Examiner, Art Unit 2493 September 11, 2026
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