The present application, filed on or after March 16, 2013, is being examined under first to invent provisions of the AIA .
DETAILED ACTION
This Action is in response to communications filed 1/28/2026.
Claims 1, 3, 9, 14-17 and 19-20 are amended.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 28, 2026 has been entered.
Response to Arguments
7. Applicant`s arguments filed January 28, 2026 have been fully considered but they are not persuasive with respect to prior art rejection.
8. As per the 103 rejection of claims 1 and 15, Applicant argued Jung/Choi/Chen fails to disclose or suggest the feature of " determine a write mode of a memory block of the memory device … based on whether a first condition based on a temperature of the storage device is satisfied and whether a second condition based on a number of read reclaim operations that have been performed in the memory block is satisfied", where Examiner relies on a newly cited reference Kurosawa to disclose the limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8 and 15 are rejected under 35 U.S.C. 103(a) as being unpatentable over Jung et al. (US 9,672,104) (hereinafter ‘Jung’), in view of Chen et al. (US PGPUB 2022/0004341) (hereinafter ‘Chen’), in view of Kurosawa et al. (US PGPUB 2022/0075562) (hereinafter ‘Kurosawa’) and further in view of Choi et al. (US PGPUB 2020/0057581) (hereinafter ‘Choi’).
As per independent claim 1, Jung discloses a storage device, comprising: a memory device including a plurality of memory blocks, each including a plurality of memory cells configured to store data [(Column 8, lines 3-12; FIGs 1 and 2) where Jung teaches where the nonvolatile memory device 1400 may include a memory cell array having a first memory area and a second memory area. In example embodiments, a bits-per-cell number of the first memory area may be less than a bits-per-cell number of the second memory area. For example, the first memory area may be formed of memory blocks which store 1-bit data per cell, and the second memory area may be formed of memory blocks which store 3-bit data per cell. However, the bits-per-cell number of each of the first and second memory areas is not limited to this example to correspond to the claimed limitation]; and a memory controller in communication with the memory device and configured to 1) determine a write mode of a memory block of the memory device to be either a first write mode in which one data bit is stored in a memory cell of a memory block or a second write mode in which a plurality of data bits is stored in a memory cell [(Column 8, lines 12-20; FIGs 1 and 2) where Jung teaches where the memory controller 1200 may perform a read reclaim operation according to whether the number of error bits of data read from one of memory blocks in the second memory area exceeds a reference. With the read reclaim operation of the inventive concept, data stored at a memory block in the second memory area may be moved to memory blocks in the first memory area, and not to a memory block in the second memory area to correspond to the claimed limitation] based on a temperature of the storage device and a number of read reclaim operations that have been performed in the memory block [(Column 13, lines 1-60; FIGs 8A-B) where Jung teaches where the threshold voltage distributions of memory cells may be shifted from an ideal programmed distribution. For example, variations in temperature, multiple read operation iterations, and so on, can cause threshold voltage distribution to shift over time.
This shift of threshold voltage distributions may cause an increase in the number of error bits contained within read data. This is particularly the case where read margins are low, such in the case of a TLC block which stores 3-bit data per cell. That is, the number of error bits caused by threshold voltage distributions may further increase multi-bit memory cells. Thus, a read reclaim operation may be performed to secure the integrity of read data. The read reclaim operation refers to an operation in which valid data of a TLC block including page data is moved to a new block. The page data may be determined to be uncorrectable and is thus moved to a new block, or the page data may be determined to have a high probability of a later increase in the number of error bits and is thus moved to a new block. The read reclaim operation may be performed because a shift of threshold voltage distributions of memory cells at which page data is stored affects adjacent memory cells. CPU 1230 may select a TLC block being a target block of a read reclaim operation of a flash translation layer FTL based on information stored at a queue. For example, it is assumed that a selected TLC block includes 64 word lines. Therefore, in the case of 3-bits-per-cell memory, 192 pages of data may be stored at one TLC block. In the case that 192 pages of data stored at the selected TLC block are all valid, there may be required three SLC blocks to move 192 pages of data stored at the selected TLC block. 64 pages of data may be read from a TLC block selected to perform a read reclaim operation, and the 64 pages of read data may be stored at one SLC block SB0 of a first memory area 1411 via an ECC circuit 1250 of a memory controller 1200. Then, 64 pages of data may be read from the selected TLC block for the read reclaim operation, and the 64 pages of read data may be stored at one SLC block SB1 of the first memory area 1411 via the ECC circuit 1250 of the memory controller 1200. Finally, 64 pages of data may be read from the selected TLC block for the read reclaim operation, and the 64 pages of read data may be stored at one SLC block SB2 of the first memory area 1411 via the ECC circuit 1250 of the memory controller 1200 to correspond to the claimed limitation] and 2) control the memory device to perform a write operation in the determined write mode [(Column 18, lines 40-50; FIGs 1 and 12) where Jung teaches where he memory controller 2404 may manage TLC blocks being a target block of a read reclaim operation, select a TLC block according to information stored at a queue at a specific time (e.g., at a write request of a host), and control the storage medium 2505 such that valid pages of data of the selected TLC block are moved to SLC blocks included in a nonvolatile memory device. The memory controller 2404 may process a read reclaim operation on the selected TLC block to be completed when valid pages of data of the selected TLC block are moved to SLC blocks included in a nonvolatile memory device to correspond to the claimed limitation].
Jung does not appear to explicitly disclose wherein the memory controller is further configured to perform a read reclaim operation in response to a number of error bits in data read from the memory device being greater than or equal to a predetermined number.
However, Chen discloses wherein the memory controller is further configured to perform a read reclaim operation in response to a number of error bits in data read from the memory device being greater than or equal to a predetermined number [(Paragraphs 0082 and 0092-0094 ; FIGs 1 and 9 and related text) where Chen teaches where the read reclaim procedure for moving the data having the number of ECC error bits greater than a predetermined error bit threshold to a new memory block, a read refresh procedure for moving the data having a read count greater than a predetermined read count threshold to a new memory block, or the likes to correspond to the claimed limitation].
Jung and Chen are analogous art because they are from the same field of endeavor of data storage management.
At the time of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jung and Chen before him or her, to modify the method of Jung to include the read reclaim operations of Chen because it will enhance system performance.
The motivation for doing so would be to improve the read speed of the memory device, a data processing method for effectively processing data stored in the memory device and improving the access performance of the memory device is highly required [(Paragraph 0015 by Chen].
Jung does not appear to explicitly disclose determine a write mode of a memory block of the memory device … based on whether a first condition based on a temperature of the storage device is satisfied and whether a second condition based on a number of read reclaim operations that have been performed in the memory block is satisfied.
However, Kurosawa discloses determine a write mode of a memory block of the memory device … based on whether a first condition based on a temperature of the storage device is satisfied and whether a second condition based on a number of read reclaim operations that have been performed in the memory block is satisfied [(Paragraphs 0255-0258 ; FIGs 1 and 28 and related text) where Chen teaches where the memory system 3 determines whether the temperature at the time of the write process is less than threshold N3. Specifically, for example, when the write process is executed, the NAND flash memory 10 outputs temperature information to the memory controller 30 based on an output from a temperature sensor (not shown) provided in the NAND flash memory 10. The memory controller 30 determines whether the temperature at the time of the write process is less than threshold N3 based on the temperature information from the NAND flash memory 10. In step ST65, the memory system 3 determines whether the number of error bits of data read by the read process (read data) is less than threshold N4. Specifically, for example, the NAND flash memory 10 outputs the read data to the memory controller 30. The ECC circuit 34 in the memory controller 30 executes the error correction process on the read data, and calculates the number of error bits. The memory controller 30 determines whether the number of error bits calculated is less than threshold N4. If the number of error bits is threshold N4 or more (step ST65; no), the processing proceeds to step ST67, and if the number of error bits is less than threshold N4 (step ST65; yes), the processing omits step ST67. In step ST66, the memory system 3 determines whether the read voltage update amount by the update patrol process is less than threshold N5. In step ST67, the memory controller 30 refers to the patrol management information 21, and increases the level of the recommended patrol mode for the target region. Specifically, if it is determined that the temperature is threshold N3 or more in step ST64, the memory controller 30 increases the level of the recommended patrol mode set for the write target region. If it is determined that the number of error bits is threshold N4 or more in step ST65, the memory controller 30 increases the level of the recommended patrol mode set for the read target region. If it is determined that the read voltage update amount is threshold N5 or more in step ST66, the memory controller 30 increases the level of the recommended patrol mode set for the target region of the update patrol process. In step ST67, the specified patrol mode does not change, and therefore, the level of the patrol mode of the patrol process executed subsequently does not change to correspond to the claimed limitation].
Jung and Kurosawa are analogous art because they are from the same field of endeavor of data storage management.
At the time of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jung and Kurosawa before him or her, to modify the method of Jung to include the read reclaim count of Kurosawa because it will enhance system performance.
The motivation for doing so would be to improve the controllability of the host device 2 can be improved [(Paragraph 0216 by Kurosawa].
Jung does not appear to explicitly disclose wherein the memory controller is further configured to count the number of the read reclaim operations.
However, Choi discloses wherein the memory controller is further configured to count the number of the read reclaim operations [(Paragraphs 0013 and 0221 ; FIGs 1 and 9 and related text) where Chen teaches where the controller A30 may determine the ranking of a memory device in which the value of a read reclaim count accumulated based on a set time is relatively small, among the two or more memory devices, to be relatively higher to correspond to the claimed limitation].
Jung and Choi are analogous art because they are from the same field of endeavor of data storage management.
At the time of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jung/Chen and Choi before him or her, to modify the method of Jung to include the read reclaim count of Choi because it will enhance system performance.
The motivation for doing so would be to improve the reliability and processing speed of data to be accessed to the memory system [(Paragraph 0028 by Choi].
Therefore, it would have been obvious to combine Jung, Chen, Kurosawa and Choi to obtain the invention as specified in the instant claim.
As per claim 8, Jung discloses wherein the memory controller is configured to control the memory device to perform the write operation based on the write mode during an idle period in which a request for any operation is not received from a host or a background operation is not triggered [(Column 7, lines 49-60) where the memory controller 1200 may be configured to control the nonvolatile memory device 1400 according to an external request (e.g., a write request, a read request, etc). The memory controller 1200 may be configured to control the nonvolatile memory device 1400 according to an internal request (e.g., an operation associated with sudden power-off, a wear-leveling operation, a read reclaim operation, etc.) and without an external request. An operation corresponding to an internal request of the memory controller 1200 may be executed within a timeout period of a host after a host request is processed. Alternatively, an operation corresponding to an internal request of the memory controller 1200 may be executed within an idle time of the memory controller 1200 to correspond to the claimed limitation].
As for independent claims 15, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
Claims 4 and 7 are rejected under 35 U.S.C. 103(a) as being unpatentable over Jung/Chen/Kurosawa/Choi, as applied to claim 1 above, in view of Bueb et al. (US PGPUB 2021/0117338) (hereinafter ‘Bueb’).
As per claim 4, Jung discloses the storage device according to claim 1.
Despite Jung teaches threshold voltage distributions of memory cells may be shifted from an ideal programmed distribution. For example, variations in temperature, multiple read operation iterations, and so on, can cause threshold voltage distribution to shift over time. This shift of threshold voltage distributions may cause an increase in the number of error bits contained within read data. This is particularly the case where read margins are low, such in the case of a TLC block which stores 3-bit data per cell. That is, the number of error bits caused by threshold voltage distributions may further increase multi-bit memory cells. Thus, a read reclaim operation may be performed to secure the integrity of read data. The read reclaim operation refers to an operation in which valid data of a TLC block including page data is moved to a new block (paragraph 0087).
Jung does not appear to explicitly disclose wherein the memory controller is configured to control the memory device to perform the write operation based on the second write mode in response to the temperature being higher than first reference temperature corresponding to low temperature and lower than second reference temperature corresponding to high temperature.
However, Bueb discloses wherein the memory controller is configured to control the memory device to perform the write operation based on the second write mode in response to the temperature being higher than first reference temperature corresponding to low temperature and lower than second reference temperature corresponding to high temperature [(Paragraphs 0030, 0035-0042; Figs. 1 and 2) where Bueb teaches where the operating temperature of the memory sub-system can be assigned a higher priority than other operating requirements of the memory sub-system. The processing device can also have received, from the host system, a parameter value of an average operating temperature of the host system, a parameter value corresponding to an estimation of an amount of time the host system will operate in temperatures exceeding 50° F., and a parameter value corresponding to an estimation of a number of write operation requests that the host system will transmit to the memory sub-system while the temperature of the automobile is below 50° F. Based on the priority of the operating requirement and the received parameter values, the processing device can determine one or more programming operation settings for a programming operation to be performed at the memory sub-system. For example, the processing device can determine to set an initial write mode of host data stored at the memory sub-system to an SLC write mode (i.e., host data is to be stored at a data block with SLCs), when host data is received when the temperature of the automobile is below 50° F. The processing device can further determine to set a subsequent write mode of host data stored at the memory sub-system to a TLC write mode (i.e., host data is to be stored at a data block with TLCs) when the temperature of the host system exceeds 50° F, wherein Bueb teaches that the write mode depends on the temperature range of the memory system to correspond to the claimed limitation].
Jung and Bueb are analogous art because they are from the same field of endeavor of data storage management.
At the time of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jung and Bueb before him or her, to modify the method of Jung to include the memory sub-systems, and more specifically, relate to adjustable memory operation settings based on memory sub-system operating requirements of Bueb because it will enhance system performance.
The motivation for doing so would be [ satisfying Quality of Service (QoS) requirements associated with the various operating requirements at the memory sub-system (Paragraph 0013 by Bueb)].
Therefore, it would have been obvious to combine Jung and Bueb to obtain the invention as specified in the instant claim.
As per claim 7, Bueb discloses wherein the memory controller is configured to control the memory device to store data corresponding to the write operation based on the write mode in response to receiving a request for the write operation from a host or during a garbage collection operation including the write operation [(Paragraphs 0010 and 0045) where programming operations, such as read operations, program (i.e., write) operations, and erase operations, can be performed at one or more memory components to program host data at the memory sub-system. In another example, background management operations, such as garbage collection operations, data refresh operations, and wear leveling operations, can be performed at one or more memory components to manage data stored at the memory sub-system. A memory operation, such as the programming operations and background management operations previously described, can be associated with one or more operation settings that affect a performance of the memory operation. For example, a read operation to retrieve data from the memory sub-system can be associated with a read voltage setting, which indicates a voltage to be applied to a data block of the memory sub-system in retrieving the data. In another example, a garbage collection operation can be associated with a garbage collection frequency setting, which indicates a frequency in which a garbage collection operation is to be performed at the memory sub-system. background management operation can include a garbage collection operation, a data refresh operation, or a data wear leveling operation. A background management operating setting can include a frequency of a performance of each of the garbage collection operation, the data refresh operation, or the data wear leveling operation, a garbage collection operation write mode, a data refresh operation write mode, a portion of data blocks of the memory sub-system to be subject to the garbage collection operation, the data refresh operation, or the data wear leveling operation, etc. In other embodiments, the background management operation setting can include any setting corresponding to a background management operation to correspond to the claimed limitation].
Claim 5 is rejected under 35 U.S.C. 103(a) as being unpatentable over Jung/Chen/Kurosawa/Choi, as applied to claim 1 above, in view of Fai et al. (US PGPUB 2012/0224425) (hereinafter ‘Fai’).
As per claim 5, Jung discloses the storage device according to claim 1.
Despite Jung teaches threshold voltage distributions of memory cells may be shifted from an ideal programmed distribution. For example, variations in temperature, multiple read operation iterations, and so on, can cause threshold voltage distribution to shift over time. This shift of threshold voltage distributions may cause an increase in the number of error bits contained within read data. This is particularly the case where read margins are low, such in the case of a TLC block which stores 3-bit data per cell. That is, the number of error bits caused by threshold voltage distributions may further increase multi-bit memory cells. Thus, a read reclaim operation may be performed to secure the integrity of read data. The read reclaim operation refers to an operation in which valid data of a TLC block including page data is moved to a new block (paragraph 0087).
Jung does not appear to explicitly disclose wherein the memory controller is configured to control the memory device to perform the write operation based on the second write mode in response to a change of the temperature during a preset time being less than or equal to a reference value.
However, Fai discloses wherein the memory controller is configured to control the memory device to perform the write operation based on the second write mode in response to a change of the temperature during a preset time being less than or equal to a reference value [(Paragraphs 0023, 0076; Figs. 1 and 2) where Fai teaches where the data can be written in SLC mode or MLC based on the obtained temperature. For instance, if the temperature of the NVM exceeds a threshold level above which MLC mode is less reliable, then the data can be written in SLC mode. In contrast, if the temperature of the NVM is below a threshold level at which MLC programming is sufficiently reliable, then the data can be written in MLC mode to correspond to the claimed limitation].
Jung and Fai are analogous art because they are from the same field of endeavor of data storage management.
At the time of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Jung and Fai before him or her, to modify the method of Jung to include the performing memory operations using temperature information of Fai because it will enhance system performance.
The motivation for doing so would be [ to provide a variety of improvements for NVM, such as improved data integrity for NVM (Paragraph 0023 by Fai)].
Therefore, it would have been obvious to combine Jung and Fai to obtain the invention as specified in the instant claim.
a(2) CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 2, 3, 6, 9-14, 16 and 19, but would be allowable if claims are amended to overcome the prior art rejections.
The reasons for allowance of claim 2 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the memory controller is configured to control the memory device to perform the write operation based on the first write mode in response to satisfying a first condition that the temperature is lower than first reference temperature corresponding to lower temperature or higher than second reference temperature corresponding to high temperature and a second condition that a performance cycle of the read reclaim operations based on the number of read reclaim operations is shorter than a reference cycle”.
The reasons for allowance of claim 3 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the memory controller is configured to control the memory device to perform the write operation based on the first write mode in response to satisfying a first condition that a change in the temperature is greater than a reference value during a preset period and a second condition that a performance cycle of a read reclaim operation based on the number of read reclaim operations is shorter than a reference cycle”.
The reasons for allowance of claim 6 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the memory controller is configured to control the memory device to perform the write operation based on the second write mode in response to a performance cycle of the read reclaim operations that is obtained based on the number of read reclaim operations is equal to or longer than a reference cycle”.
The reasons for allowance of claim 9 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the memory controller is configured to control the memory device to migrate data stored in a first memory block in the first write mode among the plurality of memory blocks to a second memory block in the second write mode in response to satisfying a first condition that the temperature is higher than first reference temperature corresponding to low temperature and lower than second reference temperature corresponding to high temperature and a second condition that a performance cycle of the read reclaim operations based on the number of read reclaim operations is equal to or longer than a reference cycle after the write operation is performed depending on the first write mode”.
The reasons for allowance of claim 14 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the memory controller is configured, after the write operation for the memory block is performed based on the first write mode, to control the memory device to migrate data stored in the memory block in the first write mode to another memory block in a second write mode in response to satisfying a first condition that a change in the temperature is less than or equal to a reference value during a preset period and a second condition that a performance cycle of the read reclaim operations obtained based on the number of read reclaim operations is equal to or longer than a reference cycle”.
The reasons for allowance of claim 16 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein selecting of the write mode comprises: selecting the first write mode in response to satisfying a first condition that the temperature falls within a preset temperature range or that a change in the temperature is greater than a reference value during a preset period and a second condition that a performance cycle of the read reclaim operations obtained based on the number of read reclaim operations is shorter than a reference cycle”.
The reasons for allowance of claim 19 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the selecting one of the write mode further comprises: selecting the second write mode in response to satisfying a first condition that the temperature falls out of a preset temperature range and a change in the temperature is less than or equal to a reference value during a preset period or a second condition that a performance cycle of the read reclaim operation is equal to or longer than the reference cycle”.
The reasons for allowance of claim 20 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the memory controller is configured to control the memory device to perform the write operation based on the first write mode in response to satisfying a first condition that the temperature is lower than first reference temperature corresponding to lower temperature or higher than second reference temperature corresponding to high temperature and a second condition that a performance cycle of the read reclaim operations based on the number of read reclaim operations is shorter than a reference cycle”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Error! Unknown document property name. whose telephone number is Error! Unknown document property name.. The examiner can normally be reached on Error! Unknown document property name..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135