Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/26/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-30 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art, hereafter referred to as AAPA in view of Guim Bernat et al. (U.S. Publication No. 2023/0029026 A1), hereafter referred to as GuimBernat’026.
Referring to claim 1, AAPA, as claimed, an apparatus (see Fig. 1B) comprising: an I/O interface configured to receive at least one operation (interfaces such as interfaces 104, 105a-b allow computer nodes 100 to receive and/or execute computer operable tasks and instructions, see Figs 1A-B, paras. [0031] and [0032]; also note: shared or parallel operations, para. [0032]); and a set of nodes configured to provide supplemental resources to at least one external host (memory expanders and near memory computes (NMCs) that are connected to and subsequently utilized by primary host computing nodes, see para. [0003]; also note: each computing node of the set of computing nodes 100 can function as supplemental sources of memory, see para. [0031]) and perform the received at least one operation (computing nodes 100a, 100b, see Fig. 1B and para. [0032]), each node of the set of nodes comprising: at least one peer-to-peer interface configured to connect to another node of the set of nodes and communicate the received at least one operation (interface 104 enables computing nodes 100a, 100b be connected for shared or parallel operations, see Fig. 1B and para. [0032]); and local memory configured to store data (memory components 102a, 102b, 103a, 103b, 112, 113, see Fig. 1A-B, paras. [0002], [0003], [0031] and [0032]).
However, AAPA does not appear to teach a sub tier configuration of supplemental nodes providing comprising local memory configured to store data.
GuimBernat’026 discloses a sub tier configuration of supplemental nodes comprising local memory configured to store data (As introduced above, a service mesh can be composed of one or multiple clusters (e.g. 505 510). Host devices (e.g., 515a, 515b, 520a, 520b, etc.) may each host various programs, services or applications (e.g. 525a-h)…All of the data moving within the cluster’s network processing device (e.g., 535, 540), with the network processing device further handling inter-cluster communications and the internal connections of hosts and the network processing device within the cluster. Attached memory of the network processing utilized to implement memory pool for the cluster…the host device can utilize CXL memory accesses (550, 555) to directly read or write data through the CXL cached memory as if it were local memory, see paras. [0058]-[0060]; CXL network 705 interconnecting two platforms or nodes or clusters (e.g. 710, 715);…resources of new device shared with other elements in the system (e.g. at the local data center or other locations…devote a portion of the new device (or other devices connected in the system) for access and use by other peers of the infrastructure, see paras. [0064], [0069], [0072], [0073], [0074], [0089], Figs. 5, 7B, 8, and 9).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify AAPA’s invention to comprise a sub tier configuration of supplemental nodes comprising local memory configured to store data, as taught by GuimBernat’026, in order to facilitate efficient data transfers utilizing CXL by enabling modular system building to effectively plug-and-play various computing resources from a remote node to a given node (see paras. [0063] and [0064]) and it has been held to be within the general skill of a worker in the art for various node configurations to provide resources on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125, USPQ 416.
As to claim 2, AAPA also discloses at least one supplemental node of the set of nodes is a memory expander configured to provide additional memory for performing the received at least one operation (Expander 310 providing additional memory, see Fig. 3A, paras. [0003], [0032], and [0042]).
As to claim 3, AAPA also discloses at least one supplemental node of the set of nodes is a near memory compute (NMC) configured to provide additional compute power for performing the received at least one operation (near memory computes (NMCs) 310 providing additional computing power, see Fig. 3A, paras. [0003], [0032], and [0042]).
As to claim 4, AAPA also discloses the set of nodes are further configured to execute the received at least one operation in parallel (parallel operations, see para. [0032]).
As to claim 5, AAPA also discloses the set of nodes are connected by the peer-to-peer interfaces in a daisy chain topology (see Figs. 1A-B and 3A).
As to claim 6, AAPA also discloses the at least one operation originates from the at least one external host (The set of host nodes 100 receive, originate, and/or execute computer operable task and instructions, see paras. [0002], [0003], [0031], Figs. 1A-B).
As to claim 7, AAPA also discloses the at least one external host utilizes the set of nodes as a unitary entity (nodes 100a-b and additional node 110 can be integrated into a unitary, server, device or board, see para. [0032]).
As to claim 8, AAPA also discloses at least one of the I/O interface and the at least one peer-to-peer interface are PCI Express (PCle) interfaces (PCIe ports, see para. [0032] and Fig. 1B).
As to claim 9, AAPA also discloses the PCI Express (PCIe) interfaces utilize Computer Express Link (CXL) protocol (PCIe port that utilizes CXL, see para. [0032] and Fig. 1B).
As to claim 10, AAPA also discloses the set of nodes are modular and a number of supplemental nodes are variable (utilize more primary (“host”) computing nodes or chips; off-chip and/or external memory and computing power, such as memory expanders and near memory computes (NMCs), see paras. [0003], [0032], Figs. 1B and 3A).
As to claim 11, AAPA also discloses the I/O interface is configured to removably couple the set of nodes to the at least one external host computing node (interfaces such as interfaces 104, 105a-b enables host computing nodes 100a, 100b, additional node 110 to be connected, see Figs. 1B, 3 and para. [0032]).
As to claim 12, AAPA also discloses the at least one external host computing node is located on a different chip than the set of nodes (off-chip and/or external memory and computing power, such as memory expanders and near memory computes (NMCs), see paras. [0003], [0032], Figs. 1B and 3A).
As to claim 13, AAPA also discloses the at least one peer-to-peer interface is further configured to removably couple the set of nodes (host computing nodes 100a, 100b, additional node 110 are connected through the interfaces and PCIe ports allows the nodes to be removable, see para. [0032], Figs. 1B and 3).
As to claim 14, AAPA also discloses the set of nodes jointly execute the received at least one operation (computing nodes 100a-b connected for shared operations, see para. [0032], Figs. 1B and 3).
Note claims 15 and 25 recite similar limitations of claim 1. Therefore they are rejected based on the same reason accordingly.
Note claims 16 and 26 recite the corresponding limitations of claim 2. Therefore they are rejected based on the same reason accordingly.
Note claims 17 and 27 recite the corresponding limitations of claim 3. Therefore they are rejected based on the same reason accordingly.
Note claim 18 recites the corresponding limitations of claim 5. Therefore it is rejected based on the same reason accordingly.
As to claim 19, AAPA also discloses sending, from the at least one host computing node, the at least one operation (The set of host nodes 100 receive, originate, and/or execute computer operable task and instructions, see paras. [0002], [0003], [0031], Figs. 1A-B).
As to claim 20, AAPA also discloses the at least one host computing node is located on a server external to the set of nodes (nodes 100a-b and additional node 110 can be integrated into a server, see para. [0032]; also note: off-chip and/or external memory and computing power, such as memory expanders and near memory computes (NMCs), see paras. [0003], [0032], Figs. 1B and 3A).
Note claims 21 and 28 recite similar limitations of claim 11. Therefore they are rejected based on the same reason accordingly.
Note claims 22 and 29 recite similar limitations of claim 7. Therefore they are rejected based on the same reason accordingly.
Note claim 23 recites the corresponding limitations of claim 8. Therefore it is rejected based on the same reason accordingly.
As to claim 24, AAPA also discloses modulating the number of supplemental nodes based upon the requirements of the received at least one operation (satisfying the increased need for more memory and compute is to utilize more primary (“host”) computing nodes or chips; off-chip and/or external memory and computing power, such as memory expanders and near memory computes (NMCs), see paras. [0003], [0032], Figs. 1B and 3A).
Note claim 30 recites the corresponding limitations of claim 24. Therefore it is rejected based on the same reason accordingly.
Response to Arguments
Applicant's arguments filed 11/26/2025 have been fully considered but they are moot due to new grounds of rejection.
In summary, AAPA and GuimBernat’026 teach the claimed limitations as set forth.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
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/TITUS WONG/Primary Examiner, Art Unit 2181