Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This is an AIA application filed May 31, 2024.
The earliest effective filing date of this AIA application is seen as May 31, 2024, the actual filing date, there being no earlier priority applications.
The present application is also related to the applications giving rise to the following patent publication(s) (some redundancy may be present):
Office
Application
App. Date
Pub. #
Pub. Date
US
PCT/US25/28635
05/09/2025
WO 2025250336 A1
12/04/2025
The claims originally filed May 31, 2024 are entered, currently outstanding, and subject to examination.
This action is in response to the information disclosure statement/IDS filing of October 3, 2025.
Claims 1-20 are currently pending and outstanding.
No claims have been amended, cancelled, withdrawn, or added.
Claims 1-20 are currently outstanding and subject to examination.
This is a non-final action and is the first action on the merits.
Allowable subject matter is not indicated below.
Often, in the substance of the action below, formal matters are addressed first, claim rejections second, and any response to arguments third.
Special Definitions for Claim Language - MPEP § 2111.01(IV)
No special definitions as defined by MPEP § 2111.01(IV) are seen as present in the specification regarding the language used in the claims. Consequently, the words and phrases of the claims are given their plain meaning. MPEP §§ 2173.01, 2173.05(a), and 2111.01.
If special definitions are present, Applicant should bring those to the attention of the examiner and the prosecution history with its next response in a manner both specific and particular. In doing so, there will be no mistake, confusion, and/or ambiguity as to what constitutes the special definition(s). Per above, such special definitions must conform to the requirements of MPEP § 2111.01(IV).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, 7-11, 13-16, and 20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 20230089433 of Li et al. (Li, cited by Applicant).
With respect to claim 1, Li discloses a device (¶ 54, "FIG. 1A is a side, cross-sectional illustration of a photonic package 100,") comprising:
a substrate (package substrate 124);
an opto-electronic integrated device (PIC 102) coupled to the substrate (124);
a first integrated device (bridge die 202) coupled to the substrate (124) through a first plurality of solder interconnects (¶ 68, interconnects 150; ¶ 70, "Interconnects 150 may comprise any suitable interconnection, including flip-chips and ball-grid array (BGA) with corresponding metallization, pads and vias, including through-substrate-vias (TSVs) (not shown) through bridge die 202, PIC 102, EIC 114 and/or XPU 118.” "The actual shapes of interconnects 130 and/or 150 for example, may result from natural processes occurring during solder reflow."); and
a second integrated device (EIC 114) coupled to the first integrated device (202) through a second plurality of solder interconnects (per Fig. 1A).
With respect to claim 3, Li as set forth above discloses the device of claim 1, including one wherein
the first integrated device (202) comprises a front side (top) and a back side (bottom), and
wherein the back side of the first integrated device (202) is coupled to the substrate through the first plurality of solder interconnects (150).
With respect to claim 4, Li as set forth above discloses the device of claim 3, including one wherein
the second integrated device (114) is coupled to the front side of the first integrated device (202) through the second plurality of solder interconnects (per Fig. 1A).
With respect to claim 7, Li as set forth above discloses the device of claim 1, including one wherein
the second integrated device (114) is configured to be electrically coupled to the opto-electronic integrated device through the first integrated device (202) and the substrate.
The second integrated device (114) is seen as so configured via the mutual connection of die 202 and PIC 102 via substrate 124
With respect to claim 8, Li as set forth above discloses the device of claim 1, including one wherein
the opto-electronic integrated device is configured to convert a first optical beam into at least one first electrical signal, and
wherein the opto-electronic integrated device is further configured to convert at least one second electrical signal into a second optical beam.
¶ 54, "In some embodiments, PIC 102 may include optical elements, such as an edge connector, a v-groove connector, or an angled reflector with a grating coupler, at an active surface 105 that allow PIC 102 to transmit and/or receive light through a lateral surface that is substantially perpendicular to the active surface 105 (e.g., lateral transmission and reception of light, as shown below, for example, in FIG. 20)."
With respect to claim 9, Li as set forth above discloses the device of claim 1, including one that further comprises
a plurality of lenses coupled to the opto-electronic integrated device.
Lens arrays, etc., Fig. 3, ¶ 86
"For example, in some embodiments, the optical surface component 140 and the optical component having defined pathways 131 are optically aligned fiber array blocks, waveguides, laser written waveguides, lens arrays, pass-through structures, or composite optical components (e.g., components with two or more different optical parts, such as, lenses and waveguides or lenses and fiber array), among others."
With respect to claim 10, Li as set forth above discloses the device of claim 1, including one further comprising
an optical fiber connector (optical components 137) coupled to the substrate.
¶ 54 provides:
"Examples of optical components 137 include any suitable optical structures for propagating optical signals, such as, a glass block, a fiber array block, an optical lens, a planar lens (e.g., for beam collimation), a micro-lens, a glass block with a reflector, a glass block with a curved surface, a mirror reflector, a multi-directional reflector, a waveguide, a laser written waveguide, and combinations thereof."
Associated connectors/couplers are generally seen as inherent for the operation of the device.
With respect to claim 11, Li as set forth above discloses a device comprising (see claim 1, above):
a substrate (124);
an opto-electronic integrated device (102) coupled to the substrate (124); and
a group of integrated devices comprising:
a first integrated device (202);
a first encapsulation layer (insulating material 133, lower section) at least partially encapsulating the first integrated device (202);
a second integrated device (114) coupled to the first integrated device (202),
wherein the second integrated device (114) vertically overlaps with the first integrated device (202); and
a second encapsulation layer (insulating material 133, upper section) at least partially encapsulating the second integrated device (114).
With respect to claim 13, Li as set forth above discloses the device of claim 11, including one wherein
the first integrated device (202) comprises a first front side and a first back side,
wherein the second integrated device (114) comprises a second front side and a second back side, and
wherein the first front side of the first integrated device (202) is coupled to the second front side of the first integrated device (202).
Such coupling is seen to occur by the coupling of the devices.
With respect to claim 14, Li as set forth above discloses the device of claim 11, including one wherein
the first integrated device (202) comprises a first plurality of through substrate vias, and
wherein the second integrated device (114) comprises a second plurality of through substrate vias.
Per ¶ 70, generally via interconnects 130 and/or 150:
"Interconnects 150 may comprise any suitable interconnection, including flip-chips and ball-grid array (BGA) with corresponding metallization, pads and vias, including through-substrate-vias (TSVs) (not shown) through bridge die 202, PIC 102, EIC 114 and/or XPU 118."
With respect to claim 15, Li as set forth above discloses the device of claim 11, including one further comprising
a plurality of through encapsulation layer vias that extend through the first encapsulation layer and the second encapsulation layer.
Per Fig. 1A.
With respect to claim 16, Li as set forth above discloses the device of claim 15, including one further comprising
a patch substrate coupled to the group of integrated devices through a plurality of solder interconnects.
The term “patch substrate” is seen to include any non-circuit element and is seen to be shown in Fig. 1A regarding the encapsulation layers or otherwise, including TIM 154.
With respect to claim 20, Li as set forth above discloses the device of claim 11, including one further comprising
an optical fiber connector coupled to the substrate.
Per claim 10, above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims, the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 5, 6, 12, and 17-19 are rejected under 35 U.S.C. § 103 as being unpatentable over .
With respect to claim 2, Li as set forth above discloses the device of claim 1, but not one wherein
the opto-electronic integrated device is located at least partially in the substrate.
Li Fig. 1A shows "heat transfer structure 155 in the package substrate 124" per ¶ 83. As such, circuit elements are seen as being located "at least partially in the substrate".
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to at least partially embed circuit elements, including an optoelectronic/OE device, along the lines of Li in a system according to Li as set forth above in order to provide more mechanical protection as well as providing additional thermal regulation in conjunction with the heat transfer structure 155. This provides one rationale to combine the references.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), the combining of prior art elements (listed above) according to known methods (per the reference) to yield predictable results (an optoelectronic device) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
the opto-electronic integrated device is located at least partially in the substrate.
With respect to claim 5, Li as set forth above discloses the device of claim 1, further comprising:
a third integrated device (XPU 118) coupled to the first integrated device (202) through a third plurality of solder interconnects.
Li as set forth above does not disclose:
a fourth integrated device coupled to the first integrated device (202) through a fourth plurality of solder interconnects.
Mere duplication of parts has no distinguishing significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960); MPEP § 2144.04(VI)(B).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include additional integrated circuit elements/devices in a system according to Li as set forth above as a duplication of parts. The modular nature of IC elements allow for any number of configurations for signal processing and/or voltage/current control and/or operation.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), the combining of prior art elements (listed above) according to known methods (per the references) to yield predictable results (an optoelectronic device) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
a fourth integrated device coupled to the first integrated device (202) through a fourth plurality of solder interconnects.
With respect to claim 6, Li as set forth above discloses the device of claim 5, including one wherein
the second integrated device (114) comprises a low noise amplifier (¶ 66, "trans-impedance amplifiers (TIA)").
Li as set forth above does not disclose:
wherein the third integrated device comprises a filter, and
wherein the fourth integrated device comprises a power amplifier.
¶ 182 provides:
"The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to TSVs 1706. The interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1704."
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use any number of available IC circuit elements along the lines of ¶ 182 (including a capacitor/filter as well as a power amplifier) in a system according to Li as set forth above in order to allow for any number of configurations for signal processing and/or voltage/current control and/or operation. This provides one rationale to combine the references.
The modular nature of IC elements allow for any number of configurations for signal processing and/or voltage/current control and/or operation.
Another completely independent and separately sufficient rationale arises as follows. In making the combination (above), the combining of prior art elements (listed above) according to known methods (per the reference) to yield predictable results (an optoelectronic device) would occur as each element merely performs the same function in combination as it does separately. MPEP § 2141(III). This additional rationale is a sufficient, a complete, and an explicitly-recognized rationale to combine the references and conclude that the claim is obvious both under the controlling KSR Supreme Court case and MPEP § 2141(III)(A). Current Office policy regarding the determination of obviousness is set forth in the Federal Register notice at 89 Fed. Reg. 14449 (Feb. 27, 2024).
Further, the combination would then provide:
wherein the third integrated device comprises a filter, and
wherein the fourth integrated device comprises a power amplifier.
With respect to claim 12, Li as set forth above discloses the device of claim 11, including one wherein
the opto-electronic integrated device is located at least partially in the substrate.
See claim 2, above.
With respect to claim 17, Li as set forth above discloses the device of claim 11, including one wherein the group of integrated devices further comprises:
a third integrated device located at least partially in the first encapsulation layer; and
a fourth integrated device located at least partially in the second encapsulation layer,
wherein the fourth integrated device vertically overlaps with the third integrated device.
Per claim 5 above with the spatial configuration deemed to be shown by the several elements and drawings in Li as set forth above.
With respect to claim 18, Li as set forth above discloses the device of claim 17, including one wherein the group of integrated devices further comprises
a fifth integrated device located at least in the second encapsulation layer,
wherein the fifth integrated device vertically overlaps with the first integrated device (202).
Per claims 5 and 17 above with the spatial configuration deemed to be shown by the several elements and drawings in Li as set forth above. Any number of IC elements are disclosed and shown in Li with vertical overlapping of such elements also shown and disclosed.
With respect to claim 19, Li as set forth above discloses the device of claim 18, including one wherein
the third integrated device comprises a third plurality of through substrate vias,
wherein the fourth integrated device comprises a fourth plurality of through substrate vias, and
wherein the fifth integrated device comprises a fifth plurality of through substrate vias.
Per duplication of parts, above (see claim 5, above) and the disclosures shown and made in Li.
Conclusion
Applicant’s publication US 20250370196 A1 published December 4, 2025 is cited.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited references have elements related to Applicant’s disclosure and/or claims or are otherwise associated with the other cited references, particularly with respect to optoelectronic systems and related devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW JORDAN whose telephone number is (571) 270-1571. The examiner can normally be reached most days 1000-1800 PACIFIC TIME ZONE (messages are returned).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. While examiner does not examine over the phone (see 37 C.F.R. § 1.2), examiner is glad to clarify or discuss issues so long as it forwards prosecution.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas (Tom) HOLLWEG can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andrew Jordan/
Primary Examiner, Art Unit 2874
V: (571) 270-1571 (Pacific time)
F: (571) 270-2571
June 3, 2026
Prosecution Insights