DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the request for continued examination filed 12 December 2025 and the response filed 17 November 2025.
Claims 1-21 are pending and have been presented for examination.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 17 November 2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 12 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 6-9, 11-15 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over SPROUSE (U.S. Patent Application Publication #2014/0136758) in view of HOANG (U.S. Patent #11,410,727) and LI (U.S. Patent Application Publication #2014/0133233).
2. SPROUSE discloses A system comprising: a memory device comprising a plurality of memory planes (see HOANG below) each comprising a content addressable memory (CAM) block arranged using a CAM architecture (see [0065]: key block where the keys are arranged along bit lines) and storing a plurality of stored search keys (see [0028]-[0029]: NAND memory operated as a CAM) and a value data block (see [0031]: when the key has a match, corresponding data can be fetched from a data block) not arranged using a CAM architecture (see [0076]: data blocks are stored in a separate location); and a processing device, operatively coupled with the memory device (see [0081]: memory can be used in a host, where the host performs data processing functions implying that a processor is present), to perform operations comprising: receiving an input search key (see [0031]: search key is broadcast); simultaneously searching for the input search key across the plurality of memory planes in parallel (see HOANG below) to identify one of the plurality of stored search keys that matches the input search key, wherein the simultaneously searching comprises causing voltage signals to be applied to wordlines of each CAM block according to the input search key, wherein each CAM block comprises an array of memory cells organized into a plurality of strings along corresponding bit lines, wherein the searching determines which bit lines conduct in response to the applied voltage signals (see LI below), and wherein the one of the plurality of stored search keys has an associated match location in the CAM block (see [0031]: match of the search key) of one of the plurality of memory planes (see HOANG below); identifying, using the associated match location, a corresponding value location in the value data block (see [0031]: column index can be used to fetch data) not arranged using the CAM architecture (see [0076]: data blocks are stored in a separate location), the value location corresponding to the associated match location (see [0031]: a match of the index in the NAND block will provide an index to the data block, therefore the value location is associated with the match location); and retrieving, from the value location in the value data block not arranged using the CAM architecture, data representing a value associated with the input search key (see [0031]: corresponding data is retrieved from a data block).
HOANG discloses the following limitations that are not disclosed by SPROUSE: a memory device comprising a plurality of memory planes (see column 7, lines 59-65: NAND memory; column 8, lines 52-55: memory array can have additional planes) each comprising a content addressable memory (CAM) block arranged using a CAM architecture (see column 10, lines 60-67: NAND memory uses as a content addressable memory); simultaneously searching for the input search key across the plurality of memory planes in parallel (see column 16, lines 37-43: parallel search of keys; column 18, lines 19-30: parallel search of memory blocks and memory planes); and identifying a match location in the CAM block of one of the plurality of memory planes (see column 16, lines 15-21: match/non-match location is read out). HOANG discloses a similar NAND CAM implementation as SPROUSE. HOANG provides additional improvements in allowing for parallel searching of a key among memory blocks and planes. By increasing the level or parallelism and leveraging both block and plane parallelism, a CAM search system can improve throughput and total latency (see column 18, lines 30-35).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SPROUSE to implement a NAND CAM with multiple planes and simultaneously search for a key across the planes in parallel, as disclosed by HOANG. One of ordinary skill in the art would have been motivated to make such a modification to improve throughput and total latency, as taught by HOANG. SPROUSE and HOANG are analogous/in the same field of endeavor as both references are directed to CAM architectures implemented in NAND memory.
LI discloses the following limitations that are not disclosed by SPROUSE: wherein the simultaneously searching comprises causing voltage signals to be applied to wordlines of each CAM block according to the input search key (see [0079]: to find a match, a sensing voltage is applied and a determination is made regarding which lines conduct; [0088]: driver circuitry is modified to broadcast the key down the wordlines of a block, instead of a single line, this would be a simultaneous search), wherein each CAM block comprises an array of memory cells organized into a plurality of strings along corresponding bit lines (see [0092]: keys stored along bit lines), wherein the searching determines which bit lines conduct in response to the applied voltage signals (see [0079]: to find a match, a sensing voltage is applied and a determination is made regarding which lines conduct; [0096]: four planes can be sensed in parallel). LI discloses multiple options for storing keys in a NAND CAM. Once option is a key, and the inverse stored twice in bit lines (see [0092]). Another option is a key, and the inverse, stored in a single bit line (see [0097]). The inherent AND functionality in NAND is useful to compare thousands of keys. All of the bit lines are sensed at the same time, and multiple die can be operated in parallel (see [0105]), and multiple planes can be searched in parallel (see [0104]). This can enhance performance (see [0105]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SPROUSE to simultaneously search wordlines of a CAM block, as disclosed by LI. One of ordinary skill in the art would have been motivated to make such a modification since searching multiple die, and planes, in parallel can improve performance, as taught by LI. SPROUSE and LI are analogous/in the same field of endeavor as both references are directed to searching for a key in a CAM.
6. The system of claim 2, wherein the memory device comprises a negative and (NAND) type flash memory device (see SPROUSE [0029]: NAND memory), and wherein the associated match location in the CAM block comprises a memory address of a string on the NAND type flash memory device (see SPROUSE [0031]: match line contains an index of the data item).
7. The system of claim 2, further comprising: a lookup table comprising a plurality of entries, wherein each entry of the plurality of entries associates a match location from the CAM block with a value location in the value data block where data representing a value corresponding to a respective stored search key from the CAM block is stored (see [0075] and figure 12: search key match location is used as an index to an associated block table to fetch a pointer to the data table).
8. The system of claim 7, wherein determining the corresponding value location in the value data block comprises identifying an entry of the plurality of entries in the lookup table corresponding to the associated match location and associating the associated match location with the corresponding value location (see [0075] and figure 12: search key match location is used as an index to an associated block table to fetch a pointer to the data table).
9. The system of claim 7, wherein the lookup table is maintained on the memory device (see [0073]: key to value mapping tables maintained in much the same way as the usual logical to physical mapping tables as far as storing them and updating them, the memory device is managing the tables and therefore the tables would be stored on the memory device).
11. The system of claim 2, wherein the input search key is received from a host system, and wherein the processing device is to perform operations further comprising: providing the data representing the value associated with the input search key to the host system (see SPROUSE [0081]).
12. SPROUSE discloses A method comprising: receiving an input search key (see [0031]: search key is broadcast); simultaneously searching for the input search key across a plurality of memory planes of a memory device in parallel (see HOANG below) to identify one of a plurality of stored search keys in a CAM block of one of the plurality of memory planes (see HOANG below) of the memory device that matches the input search key, wherein the CAM block is arranged using a CAM architecture (see [0065]: key block where the keys are arranged along bit lines), wherein the memory device comprises the plurality of memory planes each comprising a CAM block (see HOANG below), wherein the simultaneously searching comprises causing voltage signals to be applied to wordlines of each CAM block according to the input search key, wherein each CAM block comprises an array of memory cells organized into a plurality of strings along corresponding bit lines, wherein the searching determines which bit lines conduct in response to the applied voltage signals (see LI below), and wherein the one of the plurality of stored search keys has an associated match location in the CAM block (see [0031]: match of the search key); identifying, using the associated match location, a corresponding value location in a value data block of the memory device (see [0031]: column index can be used to fetch data), wherein the value data block is not arranged using the CAM architecture (see [0076]: data blocks are stored in a separate location), the value location corresponding to the associated match location (see [0031]: a match of the index in the NAND block will provide an index to the data block, therefore the value location is associated with the match location); and retrieving, from the value location in the value data block not arranged using the CAM architecture, data representing a value associated with the input search key (see [0031]: corresponding data is retrieved from a data block).
HOANG discloses the following limitations that are not disclosed by SPROUSE: simultaneously searching for the input search key across a plurality of memory planes of a memory device in parallel (see column 16, lines 37-43: parallel search of keys; column 18, lines 19-30: parallel search of memory blocks and memory planes); identify one of a plurality of stored search keys in a CAM block of one of the plurality of memory planes that matches the search key (see column 16, lines 15-21: match/non-match location is read out); and wherein the memory device comprises the plurality of memory planes each comprising a CAM block (see column 7, lines 59-65: NAND memory; column 8, lines 52-55: memory array can have additional planes; column 10, lines 60-67: NAND memory uses as a content addressable memory). HOANG discloses a similar NAND CAM implementation as SPROUSE. HOANG provides additional improvements in allowing for parallel searching of a key among memory blocks and planes. By increasing the level or parallelism and leveraging both block and plane parallelism, a CAM search system can improve throughput and total latency (see column 18, lines 30-35).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SPROUSE to implement a NAND CAM with multiple planes and simultaneously search for a key across the planes in parallel, as disclosed by HOANG. One of ordinary skill in the art would have been motivated to make such a modification to improve throughput and total latency, as taught by HOANG. SPROUSE and HOANG are analogous/in the same field of endeavor as both references are directed to CAM architectures implemented in NAND memory.
LI discloses the following limitations that are not disclosed by SPROUSE: wherein the simultaneously searching comprises causing voltage signals to be applied to wordlines of each CAM block according to the input search key (see [0079]: to find a match, a sensing voltage is applied and a determination is made regarding which lines conduct; [0088]: driver circuitry is modified to broadcast the key down the wordlines of a block, instead of a single line, this would be a simultaneous search), wherein each CAM block comprises an array of memory cells organized into a plurality of strings along corresponding bit lines (see [0092]: keys stored along bit lines), wherein the searching determines which bit lines conduct in response to the applied voltage signals (see [0079]: to find a match, a sensing voltage is applied and a determination is made regarding which lines conduct; [0096]: four planes can be sensed in parallel). LI discloses multiple options for storing keys in a NAND CAM. Once option is a key, and the inverse stored twice in bit lines (see [0092]). Another option is a key, and the inverse, stored in a single bit line (see [0097]). The inherent AND functionality in NAND is useful to compare thousands of keys. All of the bit lines are sensed at the same time, and multiple die can be operated in parallel (see [0105]), and multiple planes can be searched in parallel (see [0104]). This can enhance performance (see [0105]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SPROUSE to simultaneously search wordlines of a CAM block, as disclosed by LI. One of ordinary skill in the art would have been motivated to make such a modification since searching multiple die, and planes, in parallel can improve performance, as taught by LI. SPROUSE and LI are analogous/in the same field of endeavor as both references are directed to searching for a key in a CAM.
13. The method of claim 12, wherein the memory device comprises a negative and (NAND) type flash memory device (see SPROUSE [0029]: NAND memory), and wherein the associated match location in the CAM block comprises a memory address of a string on the NAND type flash memory device (see SPROUSE [0031]: match line contains an index of the data item).
14. The method of claim 12, wherein determining the corresponding value location in the value data block comprises identifying an entry of a plurality of entries in a lookup table corresponding to the associated match location and associating the associated match location with the corresponding value location (see [0075] and figure 12: search key match location is used as an index to an associated block table to fetch a pointer to the data table).
15. The method of claim 14, wherein the lookup table is maintained on the memory device (see [0073]: key to value mapping tables maintained in much the same way as the usual logical to physical mapping tables as far as storing them and updating them, the memory device is managing the tables and therefore the tables would be stored on the memory device).
17. SPROUSE discloses A non-transitory machine readable storage medium storing instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving an input search key (see [0031]: search key is broadcast); simultaneously searching for the input search key across a plurality of memory planes in parallel (see HOANG below) to identify one of a plurality of stored search keys in a CAM block of one of the plurality of memory planes (see HOANG below) of the memory device that matches the input search key, wherein the CAM block is arranged using a CAM architecture (see [0065]: key block where the keys are arranged along bit lines), wherein the memory device comprises the plurality of memory planes each comprising a CAM block (see HOANG below), wherein the simultaneously searching comprises causing voltage signals to be applied to wordlines of each CAM block according to the input search key, wherein each CAM block comprises an array of memory cells organized into a plurality of strings along corresponding bit lines, wherein the searching determines which bit lines conduct in response to the applied voltage signals (see LI below), and wherein the one of the plurality of stored search keys has an associated match location in the CAM block of one of the plurality of planes (see [0031]: match of the search key); identifying, using the associated match location, a corresponding value location in a value data block of the memory device (see [0031]: column index can be used to fetch data), wherein the value data block is not arranged using the CAM architecture (see [0076]: data blocks are stored in a separate location), the value location corresponding to the associated match location (see [0031]: a match of the index in the NAND block will provide an index to the data block, therefore the value location is associated with the match location); and retrieving, from the value location in the value data block not arranged using the CAM architecture, data representing a value associated with the input search key (see [0031]: corresponding data is retrieved from a data block).
HOANG discloses the following limitations that are not disclosed by SPROUSE: simultaneously searching for the input search key across a plurality of memory planes of a memory device in parallel (see column 16, lines 37-43: parallel search of keys; column 18, lines 19-30: parallel search of memory blocks and memory planes); identify one of a plurality of stored search keys in a CAM block of one of the plurality of memory planes that matches the search key (see column 16, lines 15-21: match/non-match location is read out); and wherein the memory device comprises the plurality of memory planes each comprising a CAM block (see column 7, lines 59-65: NAND memory; column 8, lines 52-55: memory array can have additional planes; column 10, lines 60-67: NAND memory uses as a content addressable memory). HOANG discloses a similar NAND CAM implementation as SPROUSE. HOANG provides additional improvements in allowing for parallel searching of a key among memory blocks and planes. By increasing the level or parallelism and leveraging both block and plane parallelism, a CAM search system can improve throughput and total latency (see column 18, lines 30-35).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SPROUSE to implement a NAND CAM with multiple planes and simultaneously search for a key across the planes in parallel, as disclosed by HOANG. One of ordinary skill in the art would have been motivated to make such a modification to improve throughput and total latency, as taught by HOANG. SPROUSE and HOANG are analogous/in the same field of endeavor as both references are directed to CAM architectures implemented in NAND memory.
LI discloses the following limitations that are not disclosed by SPROUSE: wherein the simultaneously searching comprises causing voltage signals to be applied to wordlines of each CAM block according to the input search key (see [0079]: to find a match, a sensing voltage is applied and a determination is made regarding which lines conduct; [0088]: driver circuitry is modified to broadcast the key down the wordlines of a block, instead of a single line, this would be a simultaneous search), wherein each CAM block comprises an array of memory cells organized into a plurality of strings along corresponding bit lines (see [0092]: keys stored along bit lines), wherein the searching determines which bit lines conduct in response to the applied voltage signals (see [0079]: to find a match, a sensing voltage is applied and a determination is made regarding which lines conduct; [0096]: four planes can be sensed in parallel). LI discloses multiple options for storing keys in a NAND CAM. Once option is a key, and the inverse stored twice in bit lines (see [0092]). Another option is a key, and the inverse, stored in a single bit line (see [0097]). The inherent AND functionality in NAND is useful to compare thousands of keys. All of the bit lines are sensed at the same time, and multiple die can be operated in parallel (see [0105]), and multiple planes can be searched in parallel (see [0104]). This can enhance performance (see [0105]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SPROUSE to simultaneously search wordlines of a CAM block, as disclosed by LI. One of ordinary skill in the art would have been motivated to make such a modification since searching multiple die, and planes, in parallel can improve performance, as taught by LI. SPROUSE and LI are analogous/in the same field of endeavor as both references are directed to searching for a key in a CAM.
18. The non-transitory machine readable storage medium of claim 17, wherein the memory device comprises a negative and (NAND) type flash memory device (see SPROUSE [0029]: NAND memory), and wherein the associated match location in the CAM block comprises a memory address of a string on the NAND type flash memory device (see SPROUSE [0031]: match line contains an index of the data item).
19. The non-transitory machine readable storage medium of claim 17, wherein determining the corresponding value location in the value data block comprises identifying an entry of a plurality of entries in a lookup table corresponding to the associated match location and associating the associated match location with the corresponding value location (see [0075] and figure 12: search key match location is used as an index to an associated block table to fetch a pointer to the data table).
20. The non-transitory machine readable storage medium of claim 19, wherein the lookup table is maintained on the memory device (see [0073]: key to value mapping tables maintained in much the same way as the usual logical to physical mapping tables as far as storing them and updating them, the memory device is managing the tables and therefore the tables would be stored on the memory device).
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over SPROUSE (U.S. Patent Application Publication #2014/0136758), HOANG (U.S. Patent #11,410,727) and LI (U.S. Patent Application Publication #2014/0133233) as applied to claims 2, 6-9, 11-15 and 17-20 above, and further in view of BANDO (U.S. Patent Application Publication #2013/0198445).
3. The system of claim 2, wherein each string of the CAM blocks stores one of the plurality of stored search keys and comprises a plurality of memory cells connected in series (see [0029]-[0030]: search keys are stored in the memory and aligned along the bit lines, this would be the string) between a precharged match line (see [0031]: bit lines are precharged, the line that is left with a charge after the search would be the matching search line, this is how CAM memories function) and a page buffer (see BANDO below), and wherein each of the plurality of memory cells is connected to one of a plurality of search lines (see [0031]: bit line is connected to the word line and performs a comparison during the search).
BANDO discloses the following limitation not disclosed by SPROUSE: a plurality of memory cells connected in series between a precharged match line and a page buffer (see [0057]: hit miss string stored in a page buffer). Storing the result in the page buffer reduces the amount of transmitted data that is sent between the memory and an external device, thereby allowing for more efficient output (see [0059]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SPROUSE to utilize a page buffer, as disclosed by BANDO. One of ordinary skill in the art would have been motivated to make such a modification to reduce data transmission and provide more efficient output, as taught by BANDO. SPROUSE and BANDO are analogous/in the same field of endeavor as both references are directed to operating a CAM.
4. The system of claim 3, wherein the input search key comprises a first sequence of bits, and wherein the processing device is to perform operations further comprising: generating a search pattern based on the first sequence of bits, the search pattern comprising a first set of voltage signals representing the first sequence of bits and a second set of voltage signals representing a second sequence of bits comprising an inverse of the first sequence of bits (see SPROUSE [0030]: keys are stored in the inverted and non-inverted form).
5. The system of claim 4, wherein the processing device is to perform operations further comprising: providing the search pattern as an input to the plurality of search lines of the CAM block (see SPROUSE [0031]: search key is broadcast to all the lines), wherein the search pattern to cause at least one string of the plurality of strings storing the one of the plurality of stored search keys that matches the input search key to be conductive and provide a signal to the page buffer in response to the input search key matching the one of the plurality of stored search keys stored on the at least one string (see SPROUSE [0031]: match line is conductive), the signal resulting from the precharged match line discharging (see SPROUSE [0031]: lines that are not a match are discharged, as that results in the matching line still being conductive, this is how a CAM works), and the page buffer storing data based on the signal (see [0057]: match line result is stored in page buffer).
Claim(s) 10, 16 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over SPROUSE (U.S. Patent Application Publication #2014/0136758), HOANG (U.S. Patent #11,410,727) and LI (U.S. Patent Application Publication #2014/0133233) as applied to claims 2, 6-9, 11-15 and 17-20 above, and further in view of MIURA (U.S. Patent Application Publication #2019/0286570).
10. The system of claim 7 (see SPROUSE above), further comprising a dynamic random access memory (DRAM) device, wherein the lookup table is maintained in the DRAM device (see MIURA below).
MIURA discloses the following limitations that are not disclosed by SPROUSE: further comprising a dynamic random access memory (DRAM) device, wherein the lookup table is maintained in the DRAM device (see [0094]-[0098]: translation entries are cached in DRAM). Caching translation entries in DRAM allows for lower latency access to the translation data (see [0101]). SPROUSE already discloses maintaining key to value mapping tables in the same way as the usual logical to physical mapping tables. MIURA discloses that caching mapping data inn a RAM allows for lower latency access to this data compared to accessing the data from the flash memory. Therefore, modifying SPROUSE to maintain the lookup table on DRAM would result in more efficient access to the lookup table data.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SPROUSE to maintain the lookup table in DRAM, as disclosed by MIURA. One of ordinary skill in the art would have been motivated to make such a modification to allow for lower latency access to the table, as taught by MIURA. SPROUSE and MIURA are analogous/in the same field of endeavor as both references are directed to managing lookup tables for accessing data in a flash memory system.
16. The method of claim 14 (see SPROUSE above), wherein the lookup table is maintained in a dynamic random memory (DRAM) device (see MIURA below).
MIURA discloses the following limitations that are not disclosed by SPROUSE: further comprising a dynamic random access memory (DRAM) device, wherein the lookup table is maintained in the DRAM device (see [0094]-[0098]: translation entries are cached in DRAM). Caching translation entries in DRAM allows for lower latency access to the translation data (see [0101]). SPROUSE already discloses maintaining key to value mapping tables in the same way as the usual logical to physical mapping tables. MIURA discloses that caching mapping data inn a RAM allows for lower latency access to this data compared to accessing the data from the flash memory. Therefore, modifying SPROUSE to maintain the lookup table on DRAM would result in more efficient access to the lookup table data.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SPROUSE to maintain the lookup table in DRAM, as disclosed by MIURA. One of ordinary skill in the art would have been motivated to make such a modification to allow for lower latency access to the table, as taught by MIURA. SPROUSE and MIURA are analogous/in the same field of endeavor as both references are directed to managing lookup tables for accessing data in a flash memory system.
21. The non-transitory machine readable storage medium of claim 19 (see SPROUSE above), wherein the lookup table is maintained in a dynamic random memory (DRAM) device (see MIURA below).
MIURA discloses the following limitations that are not disclosed by SPROUSE: further comprising a dynamic random access memory (DRAM) device, wherein the lookup table is maintained in the DRAM device (see [0094]-[0098]: translation entries are cached in DRAM). Caching translation entries in DRAM allows for lower latency access to the translation data (see [0101]). SPROUSE already discloses maintaining key to value mapping tables in the same way as the usual logical to physical mapping tables. MIURA discloses that caching mapping data inn a RAM allows for lower latency access to this data compared to accessing the data from the flash memory. Therefore, modifying SPROUSE to maintain the lookup table on DRAM would result in more efficient access to the lookup table data.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify SPROUSE to maintain the lookup table in DRAM, as disclosed by MIURA. One of ordinary skill in the art would have been motivated to make such a modification to allow for lower latency access to the table, as taught by MIURA. SPROUSE and MIURA are analogous/in the same field of endeavor as both references are directed to managing lookup tables for accessing data in a flash memory system.
Conclusion
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132