Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the claim listing filed on 05/31/2024. Claims 1-20 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected 35 U.S.C. 103 as being unpatentable over Chang et al. (USPGPUB No. 2019/0254013 A1, hereinafter referred to as Chang) in view of Follett et al. (USPGPUB No. 2014/0032150 A1, hereinafter referred to as Follett) in view of van Rooyen et al. (USPGPUB No. 2018/0181708 A1, hereinafter referred to as van Rooyen) and further in view of Bhallamaudi et al. (USPGPUB No. 20230300114 B1, hereinafter referred to as Bhallamaudi).
As per claim 1, Chang discloses a system for storing and displaying {“RF signals may power a passive NFC tag (e.g., a microchip embedded in a sticker or wristband) to transmit stored data to the NFC circuitry 540, or initiate data transfer between the NFC circuitry 540 and another active NFC device (e.g., a smartphone or an NFC-enabled POS terminal)” ([0100], last sentence) displayed via “touchscreen driver to control and allow access to a touchscreen interface of the platform 500, sensor drivers to obtain sensor readings of sensor circuitry 521 and control and allow access to sensor circuitry 521, actuator drivers to obtain [measurement signals] actuator positions of the actuators 522 and/or control and allow access to the actuators 522, a camera driver to control and allow access to an embedded image capture device, audio drivers to control and allow access to one or more audio devices”, see Fig. 1, [0101], last sentence} measurement signals of a spectrum analyzer {“synthesizer circuitry 706d may be a fractional-N synthesizer or a fractional N/N+1 synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable”, see Fig. 1 [0125], 2nd sentence} with real time spectrum analysis (RTSA) {“separate radio IC circuitry may be provided for processing signals [analysis] for each spectrum”, see Fig. 1, [0125], 1st sentence} in real time {“NAICS, MBMS, real-time services”, see Fig. 1 [0019]}, the system comprising:
an analog to digital converter (ADC) {“analog-to-digital and digital-to-analog converter circuitry, analog circuitry”, see Fig. 1, [0117], last sentence};
a detector unit configured to convert {“The audio subsystem may include DSP circuitry, buffer memory, program memory, speech processing accelerator circuitry, data converter circuitry”, [0117]} the sampled digital data from the time domain {“N.sub.symb.sup.DL consecutive OFDM symbols in the time domain and N.sub.sc.sup.RB consecutive subcarriers in the frequency domain”, [0029]}, to frequency domain to provide detected spectrum digital data {”to one slot in a [detected spectrum digital data] radio frame”, see Fig. 2, [0027]; the radio frame coordinated by “control functions for the digital baseband circuitry and/or radio frequency circuitry (e.g., the radio front end modules 715”, see Fig. 7, [0117], last sentence};
Chang does not appear to explicitly disclose wherein the ADC configured to sample a measurement signal acquired from a device under test (DUT) during a measurement by the RTSA, and to output sampled digital data in a data stream in time domain;
a circular buffer having a predetermined buffer length, wherein the circular buffer is configured to receive the spectrum digital data via a first interface, to write the spectrum digital data as buffered digital data in a predetermined order starting at a beginning of the predetermined buffer length until reaching an end of the predetermined buffer length, to output the buffered digital data in the predetermined order, and to overwrite previously buffered digital data in the predetermined order starting at the beginning of the predetermined buffer length after reaching the end of the predetermined buffer length;
a storage unit configured to receive the buffered digital data output from the circular buffer in real time via a second interface;
and a controller configured to determine whether the buffered digital data are output from the circular buffer faster than the spectrum digital data are written in the circular buffer,
wherein when the controller determines that the buffered digital data are output from the circular buffer faster than the spectrum digital data are written in the circular buffer, the controller is further configured to enable the circular buffer to continue to write the spectrum digital data in the predetermined order and to output the buffered digital data to the storage unit uninterrupted in real time via the second interface, and wherein when the controller determines that the buffered digital data are output from the circular buffer slower than the spectrum digital data are written in the circular buffer, but an entirety of the predetermined buffer length of the circular buffer is able to be output by the circular buffer at least once before the buffered digital data are overwritten, the controller is further configured to control the circular buffer to continue to write the spectrum digital data in the predetermined order until the circular buffer is about to begin overwriting buffered digital data of the previously buffered digital data that has not yet been output to the storage unit.
However, Follett discloses wherein the ADC configured to sample a measurement signal {“analog-to-digital converter (ADC) 120 digitizes the IF signal to produce a continuous stream of digital samples”, see Fig. 2 [0003], 2nd sentence} acquired from a device under test (DUT) {“device under test”, [0008], last two sentences} during a measurement by the RTSA {“used in a real-time spectrum analyzer… and measurement instrument that displays frequency domain signals”, see Figs. 1 and 2 [0034]}, and to output sampled digital data {“The digital samples are [output] input to”, [0003], 3rd sentence} in a data stream in time domain {“stream of digital samples into thousands of spectra 210 every second”, see Fig. 1, [0004], 3rd sentence};
a circular buffer {“the circular buffer 125”, see Fig. 1, [0003] last three sentences} having a predetermined buffer length {“causes an acquisition memory 135 to store the digital samples held in the circular buffer 125 [length]”, see Fig. 1, [0003] last three sentences};
a storage unit {“causes an acquisition memory 135”, see Fig. 1 [0003], last two sentences} configured to receive the buffered digital data output from the circular buffer {“ the acquisition memory stores incoming data.”, see Fig. 1, [0006], last two sentences}, wherein the storage unit comprises a plurality of data structures {“combined to form a data structure referred to as a ‘bitmap database’ 220”, see Fig. 2 [0004]} is separately retrievable in real time by a processor for display {“bitmap database 220 may be displayed as an image referred to as a ‘bitmap’ on the display device 145”, see Fig. 2 [0005], last two sentences} during the measurement by the RTSA {“rasterized spectra 215 and the bitmap database 220 are depicted in the Drawings as having 10 rows and 11 columns for simplicity”, see Fig. 2 [0005], 1st sentence};
and a controller {“uses a continuous-time processor 150 to process the continuous stream of digital samples”, see Fig. 1 [0004], 2nd sentence} configured to determine whether the buffered digital data are output from the circular buffer faster than the spectrum digital data are written in the circular buffer {“’Violate’ means either [faster than] ‘exceeds’ depending on a user-specified parameter”, see Fig. 1, [0003], last two sentences},
wherein when the controller determines that the buffered digital data are output from the circular buffer faster {“that a trigger may be created whenever a [buffered digital data] signal is present more or less frequently than a defined percentage of time”, see Figs. 1 [0006], last sentence} than the spectrum digital data are written in the circular buffer {“the spectra may be fed to a triggering system, comparing each spectra to a pre-defined trigger mask [via the circular buffer]”, see Figs. 1 and 2, [0006], 3rd sentence};
Chang and Follett are analogous because they are from the same field of endeavor, managing networked device(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Chang and Follett before him or her, to modify Chang’s “platform 500” (see Fig. 1, [0101]) incorporating Follett’s “bitmap database 220 may be displayed as an image referred to as a ‘bitmap’ on the display device 145” (see Fig. 2 [0005], last two sentences).
The suggestion/motivation for doing so would have been to incorporate test and measurement instruments that seamlessly capture RF signals so that, unlike conventional swept spectrum analyzers and vector signal analyzers, no data is missed within a specified bandwidth (Follett [0002], last sentence).
Therefore, it would have been obvious to combine Follett with Chang to obtain the invention as specified in the instant claim(s).
Neither Chang nor Follet appears to explicitly disclose wherein the circular buffer is configured to receive the spectrum digital data via a first interface, to write the spectrum digital data as buffered digital data in a predetermined order starting at a beginning of the predetermined buffer length until reaching an end of the predetermined buffer length, to output the buffered digital data in the predetermined order, and to overwrite previously buffered digital data in the predetermined order starting at the beginning of the predetermined buffer length after reaching the end of the predetermined buffer length;
a storage unit configured to receive the buffered digital data output from the circular buffer in real time via a second interface, wherein the storage unit comprises a plurality of segmented BIN files configured to store portions of the received digital data in binary format, respectively, wherein each segmented BIN file of the plurality of segmented BIN files is separately retrievable in real time by a processor for display during the measurement by the RTSA;
the controller is further configured to enable the circular buffer to continue to write the spectrum digital data in the predetermined order and to output the buffered digital data to the storage unit uninterrupted in real time via the second interface, and wherein when the controller determines that the buffered digital data are output from the circular buffer slower than the spectrum digital data are written in the circular buffer, but an entirety of the predetermined buffer length of the circular buffer is able to be output by the circular buffer at least once before the buffered digital data are overwritten, the controller is further configured to control the circular buffer to continue to write the spectrum digital data in the predetermined order until the circular buffer is about to begin overwriting buffered digital data of the previously buffered digital data that has not yet been output to the storage unit.
However, van Rooyen discloses wherein the circular buffer is configured to receive the spectrum digital data via a first interface {“stream reads from the host [first interface] into circular buffers in memory,”, see Fig. 40 [0668], last two sentences}, to write the spectrum digital data as buffered digital data in a predetermined order {“ BAM output 414, reduced BAM output 416, and/or [predetermined buffered digital data as claimed] CRAM compression 418 can be replaced with variant calling, compression and decompression”, see Fig. 40 [0668], last sentence} starting at a beginning of the predetermined buffer length {“L+1 delay may be a shift register or a shallow circular buffer length”, see Figs. 6 and 40 [0399], 1st sentence} until reaching an end of the predetermined buffer length {“a pipeline anti-diagonal in progress should be able to straddle [reaching] between the right end of one swath and the left end of the next”, see Fig. 40 [0399]}, to output the buffered digital data in the predetermined order {“Results at the bottom of the swath may be stored in a [predetermined order] local memory”, see Figs. 6 and 40, [0399], 2nd sentence}, and to overwrite previously buffered digital data in the predetermined order {“may be [overwrite previously] re-injected into the pipeline each time the position wraps vertically in the next swath”, see Figs. 6 and 40, [0399], 2nd sentence} starting at the beginning of the predetermined buffer length after reaching the end of the predetermined buffer length {“pipeline anti-diagonal in progress should be able to [starting at the beginning of] straddle between the right end of one swath and the left end of the next”, see Figs. 6 and 40 [0399] last sentence};
wherein the storage unit configured to receive the buffered digital data output from the circular buffer {“HMM accelerator module 8 may include or otherwise be associated with various interfaces, e.g., 3, 5, 10, and/or so as to allow the efficient transfer of data to and from the processing engines 13” ([0421], last sentence) including subcomponent circular buffer “circular buffers in memory” (see Fig. 40 [0668], last two sentences)} in real time via a second interface {such “circular buffers in memory” (See Fig. 40) via second interface “MID Calc 17b” (see Fig. 14) and “scratchpad”/” One or more scratch RAMs 17c may also be included” (see Fig. 14 [0458], last sentence)}, wherein the storage unit comprises a plurality of data structures configured {“FASTQ file may be used to produce seeds of a predetermined length”, see Fig. 1, [0166], 1st sentence; “information represented by these reads may be in a digital format, such as in FASTQ, BCL, or other similar file format”, [0121], last sentence} to store portions of the received digital data in binary format {“which seeds may be converted into binary form and fed through a hash function”, see Fig. [0166], 1st sentence}, respectively, wherein each segmented data structure of the plurality of segmented data structures {“[each segmented data structure] one or more of the generated sample seeds per read, need only be compared such as to an index containing equivalent seed portions of the reference genome”, see Fig. [0167], 1st sentence} is separately retrievable in real time by a processor {“seeds from one read, e.g., in [separately retrievable] one or more lookups, such as a plurality of lookups, 2, 3, or 4”, see Fig. [0167], last three sentences} for display during the measurement by the RTSA {“where desired the [for display] GUI menu and system function calls … operations 800 including: [real-time measurement] non-invasive prenatal testing (NIPT) 123a, N/P ICU 123b, [real-time measurement] cancer related diagnostics and/or therapeutic modalities 123c”, see Fig. 33B, [0626], last sentence};
the controller is further configured to enable the circular buffer to continue to write the spectrum digital data {“time taken for storing and retrieving such intermediate results data [to the circular buffer]”, see Fig. 4 [0396], 1st sentence} in the predetermined order and to output the buffered digital data to the storage unit uninterrupted in real time via the second interface {“particular HMM implementations, multiple engine instances 13a-.sub.(n+1) may be grouped into a cluster 11 that is serviced by a [second interface] single connection, e.g., PCIe bus 5, to the PCIe interface 4 and DMA 3”, see Fig. 16, [0503], last two sentences}, and wherein when the controller determines that the buffered digital data are output {“[buffered digital data output] Run-time extension fails if the extended”, see Fig. 1, [0202], last sentence} from the circular buffer slower than the spectrum digital data are written in the circular buffer {“[buffered digital data output] Run-time extension fails if the extended seed overruns either [slower than] end of the read” to the storage unit as claimed, see Fig. 1, [0202], last sentence}, but an entirety of the predetermined buffer length of the circular buffer is able to be output {“read sequence data storage 18, and M, I, D state storage at the bottom edge of the region (or swath), e.g., via a [circular buffer] scratch pad memory”, see Figs. 17 and 19, [0497], 1st sentence} by the circular buffer at least once before the buffered digital data are overwritten {“[overwritten] storing the results of the swath boundary”, see Figs. 6 and 11, [0503], 2nd sentence}, the controller is further configured to control the circular buffer to continue to write the spectrum digital data in the predetermined order {the controller “HMM engine instance 13” ([0440], 1st sentence) to continue “enough space is provisioned in the HMEM to hold one, two, or more complete [spectrum digital data in the predetermined order] reference sequences per HMM job 20”, see Fig. 12, [0443], 2nd sentence} until the circular buffer is about to begin overwriting buffered digital data of the previously buffered digital data that has not yet been output to the storage unit {“[buffered digital data] various of the HMM jobs 20 may result in underruns [has not yet been output]” to the storage unit as claimed, see Figs. 17 and 18 [0494], 2nd sentence}.
Chang/Follett and van Rooyen are analogous because they are from the same field of endeavor, managing networked device(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Chang/Follett and van Rooyen before him or her, to modify Chang/Follett’s device incorporating van Rooyen’s “circular buffers” (see Fig. 40) and adjoining controller “HMM accelerator module 8” (see Fig. 40, [0668]).
The suggestion/motivation for doing so would have been to incorporate variant call function, e.g., an HMM or paired MINI operation, on the accessed reads, by a third or fourth subset of the hardwired digital logic circuits of the integrated circuit, so as to produce a variant call file detailing how the mapped, aligned, and/or sorted reads vary from that of one or more reference, e.g., haplotype, sequences (van Rooyen [0061]) via a hardware solution, the hardware, as presented herein, has been designed to perform these functions and/or their attendant processes in an optimized manner so as to be performed faster and/or with better accuracy for execution by that media (van Rooyen [0025], last sentence).
Therefore, it would have been obvious to combine van Rooyen with Chang/Follett to obtain the invention as specified in the instant claim(s).
Neither one of the group consisting of Chang, Follet, and van Rooyen appears to explicitly disclose wherein the storage unit comprises a plurality of segmented BIN files configured to store portions of the received digital data in binary format, respectively, wherein each segmented BIN file of the plurality of segmented BIN files is separately retrievable in real time by a processor for display during the measurement by the RTSA;
Additionally, Bhallamudi discloses wherein the storage unit comprises a plurality of segmented BIN files configured {“at least a cryptographic hash of the entire file 820 and an ordered [plurality] sequence of hashes of variable length [segmented] chunks of the extracted text… the fingerprint data 808 as bin (binary) files”, see Fig. 13 [0152]} to store portions of the received digital data in binary format {“fingerprint data 808 as bin (binary) files are then uploaded”, see Fig. 13 [0152], 2nd sentence}, respectively, wherein each segmented BIN file of the plurality of segmented BIN files {“The [segmented] bin files 828 are combined into a lookup table 840A”, see Fig. 15 [0155], 3rd sentence} is separately retrievable in real time by a processor {“Each [processor] tenant 830 has its own documents 802 that are used [separably retrievable]”, see Fig. 15 [0155], 3rd sentence} for display during the measurement by the RTSA {“IT administrators can drill-down [via a display] to a per-user level to understand events and correlate threats, to identify compromised devices, to have application visibility, and the like”, see Fig. 1 [0045], 3rd sentence};
Chang/Follett/van Rooyen and Bhallamudi are analogous because they are from the same field of endeavor, managing networked device(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Chang/Follett and Bhallamudi before him or her, to modify Chang/Follett’s device incorporating Bhallamudi’s “cryptographic hash of the entire file 820” and “bin files 828” respectively via cryptographic hashing (see Fig. 13).
The suggestion/motivation for doing so would have been to incorporate Encryption increases the problem because sensitive data is typically concealed in Secure Sockets Layer (SSL)/Transport Layer Security (TLS) traffic, which is difficult and expensive to inspect). While relying visibility and control, coordinating around organizations are at an increased risk of dataloss, due either to unintentional or malicious reasons (Bhallamudi [0003], last sentence).
Therefore, it would have been obvious to combine Bhallamudi with Chang/Follett/van Rooyen to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Chang discloses wherein the circular buffer comprises a dynamic random-access memory (DRAM) {“DRAM, SRAM, EPROM, EEPROM, Flash memory, solid-state memory, and/or any other type of memory device technology”, see Fig. 4, [0076] last sentence}.
As per claim 3, the rejection of claim 1 is incorporated and Chang discloses wherein the processor is provided in a remote processing unit coupled with the RTSA {“the gNB-DUs may include one or more remote [processing unit] radio heads or RFEMs” (see Fig. 2, [0025] last two sentences) “gNB-CU may be operated by a server that is located in the RAN 110 (not shown) or by a server pool in a similar manner as the CRAN/vBBUP” in which the RTSA “synthesizer circuitry 706d” is a subcomponent how “the baseband circuitry 410 and/or RFEMs 415 to communicate with the nodes and components of the positioning network… also provide position data and/or time data to the application circuitry 405, which may use the data to synchronize operations with various infrastructure (e.g., RAN nodes 111” such as the “synthesizer circuit 706d” (see Figs. 3 and 4).
As per claim 4, the rejection of claim 1 is incorporated and van Rooyen discloses wherein the controller is configured to determine whether the buffered digital data are output from the circular buffer faster {“[buffered digital data] various of the HMM jobs 20 may result in underruns [has not yet been output]” to the storage unit as claimed, see Figs. 17 and 18 [0494], 2nd sentence} than the spectrum digital data are written in the circular buffer by monitoring a write pointer indicating {“contains a [read/write] chain pointer pointing toward where the record is continued in the bucket chain”, [0191], 1st sentence} where the spectrum digital data are being written in the circular buffer from the detector unit and a read pointer {“if required for such storage [write pointer] and retrieval [read pointer]”, [0191], 1st sentence} indicating where the buffered digital data are being output from the circular buffer to be stored in the storage unit {“after following any chain pointer to a second bucket [or likewise the claimed storage unit]”, [0191]}.
As per claim 5, the rejection of claim 4 is incorporated and van Rooyen discloses wherein the controller is configured to detect when the circular buffer is about to begin overwriting {“may be [overwrite previously] re-injected into the pipeline each time the position wraps vertically in the next swath”, see Figs. 6 and 40, [0399], 2nd sentence; “For instance, N pipelines could be configured [about] to work on N swaths at a time, wherein each stays behind the compute wavefront 35 in the swath above”, [0401], 2nd sentence} the buffer digital data of the previously buffered digital data that has not yet been output {“read sequence data storage 18, and M, I, D state storage at the bottom edge of the region (or swath), e.g., via a [circular buffer] scratch pad memory”, see Figs. 17 and 19, [0497], 1st sentence} from the circular buffer by detecting when only about 2 percent to about 10 percent of the circular buffer {“unmapped portions of the read, or longer by some factor, such as 10%... to fully align to the reference window [of the circular buffer]”, [0237], 1st sentence} is left before the write pointer laps the read pointer {“where an “inferior” seed chain may be filtered out if it substantially overlaps a read having a “superior” seed”, [0209], 2nd sentence}.
As per claim 6, the rejection of claim 1 is incorporated and van Rooyen discloses wherein the controller is further configured to provide an alert {“Read and Hap IDs are the [alert] mechanism the system 1 uses to properly associate jobs with results”, see Figs. 13 and 14 [0450], 2nd sentence} indicating that the circular buffer is no longer writing the spectrum digital data {“after it has completed its currently assigned task [thus no longer writing as claimed.”, see Figs. 13 and 14 [0451], 1st sentence}.
As per claim 7, the rejection of claim 1 is incorporated and van Rooyen discloses wherein the controller is further configured to:
initially determine whether the buffered digital data will be output from the circular buffer {“beginning of the processing of the next swath 35b may be initiated [determining the buffered digital data], as described in greater detail with respect to FIG. 24”, see Figs. 15 and 16 [0470], last sentence} slower than the spectrum digital data will be written in the circular buffer {“[buffered digital data output] Run-time extension fails if the extended seed overruns either [slower than] end of the read” to the storage unit as claimed, see Fig. 1, [0202], last sentence}, and that an entirety of the predetermined buffer length of the circular buffer cannot be received {“thus minimizing downtime between jobs [where the buffer cannot be received/sent]”, see Figs. 13 and 14 [0451], 2nd sentence} by the storage unit at least once before being overwritten {“[overwritten] storing the results of the swath boundary”, see Figs. 6 and 11, [0503], 2nd sentence},
when it is determined that the buffered digital data will be output from the circular buffer slower than the spectrum digital data will be written in the circular buffer {“be configured to automatically take the input job 20 sent by the data distributor 9 and assign it to one of the HMM engine instances 13 in the cluster 11 that can receive a new job”, see Fig. 13, [0451], last two sentences}, and the entirety of the predetermined buffer length of the circular buffer cannot be received by the storage unit at least once before being overwritten {“[overwritten] storing the results of the swath boundary”, see Figs. 6 and 11, [0503], 2nd sentence}, reconfigure the circular buffer as a linear buffer to buffer the spectrum digital data once {linear buffer “a ping-pong structure may be implemented therein such that once the memories”, see Fig. 14, [0456], 1st sentence} in the predetermined order starting at the beginning of the predetermined buffer length until reaching the end of the predetermined buffer length {“L+1 delay may be a shift register or a shallow circular buffer length”, see Figs. 6 and 40 [0399], 1st sentence}, without overwriting afterwards {“[buffered digital data output] Run-time extension fails if the extended seed overruns either [slower than] end of the read” to the storage unit as claimed, see Fig. 1, [0202], last sentence}, and provide an alert {“Read and Hap IDs are the [alert] mechanism the system 1 uses to properly associate jobs with results”, see Figs. 13 and 14 [0450], 2nd sentence} indicating that the circular buffer is no longer writing the spectrum digital data {“after it has completed its currently assigned task [thus no longer writing as claimed.”, see Figs. 13 and 14 [0451], 1st sentence}.
As per claim 8, the rejection of claim 7 is incorporated and van Rooyen discloses wherein the controller initially determines whether the buffered digital data will be output from the circular buffer slower than the spectrum digital data will be written in the circular buffer by {“be configured to automatically take the input job 20 sent by the data distributor 9 and assign it to one of the HMM engine instances 13 in the cluster 11 that can receive a new job”, see Fig. 13, [0451], last two sentences}:
determining speeds of the first and second interfaces {“adjacent-swath 35.sub.n [first and second interfaces] pipelines may be configured so as to be synchronized”, see Figs. 6 and 7 [0401], 2nd sentence};
determining a first time required {“to avoid [first time] N*L dead cycles”, see Fig. 6 [0401], last sentence} to fill the circular buffer with the spectrum digital data based on the predetermined buffer length of the circular buffer {“memory may be used as an elastic First In First Out (“FIFO”) [buffer length] to capture output data from the HMM engine instances 13”, see Figs. 19 and 20 [0504], sentence}, a size of the spectrum digital data {“size of this FIFO may be made parametrizable”, see Figs. 19 and 20 [0504], last three sentences}, and the speed of the first interface {“the [first interface type] pipelines can compute one cell per cycle at 300 MHz”, see Fig. 6, [0400], 3rd sentence};
determining a second time to write the buffered digital data {“that 200 MHz is the speed of the clock associated with the Cluster Buses 10 and a data width of 32 bits is moving through the bus of each HMM cluster 11 during each clock cycle”, see Figs. 9 and 10, [0435], 1st sentence} to the storage unit based on the speed of the second interface {“initial configuration for the Cluster Buses 10 may involve a 200 MHz clock and data transfer rate as well as six HMM clusters 11a-f.”, see Figs. 9 and 10 [0435], last two sentences};
and Bhallamudi discloses comparing the second time to the first time to determine whether all buffered digital data {“first enforcement node and the second enforcement node can be configured to forward the DLP incident information”, see Fig. 11 [0125], 1st sentence} in one cycle of the circular buffer can be output to the segmented BIN files {“[each segmented] The bin files 828 are combined into a lookup table 840A, 840B for each tenant 830A, 830B”, see Fig. [0155], 3rd sentence} before being entirely overwritten {“When indexing a directory of files belonging to the same document profile, an IDM bin file 828 is created containing the fingerprint data 808 of all files belonging to the same profile” including any appropriate overwrites, see Fig. 14 [0153], last sentence}.
As per claim 9, the rejection of claim 1 is incorporated and Bhallamudi discloses further comprising:
a display configured to display {“This enables IT administrators to have a unified view [and display] of user activity, threat intelligence, application usage, etc. For example, IT administrators can drill-down to a per-user level to understand events and correlate threats, to identify compromised devices, to have application visibility, and the like”, see Fig. 1 [0045], 2nd sentence} selected segmented BIN files of the plurality of segmented BIN files of the storage unit “[each selected data structure] one or more of the generated sample seeds per read, need only be compared such as to an index containing equivalent seed portions of the reference genome”, see Fig. [0167], 1st sentence}, wherein the selected segmented BIN files are identified via a user interface {“IT administrators can drill-down to a per-user level to understand events and correlate threats, to identify [user interface] compromised devices, to have application visibility, and the like”, see Figs. 1 and 2 [0045], 3rd sentence}.
As per claim 10, the rejection of claim 9 is incorporated and Chang discloses wherein the display comprises an instrument display of the spectrum analyzer {“analyzed by a post-analysis processor 140, and the results may be displayed on a display device 145 or stored in a storage device”, see Fig. 1 [0003], last sentence}.
As per claim 11, the rejection of claim 1 is incorporated and Chang discloses wherein each segmented BIN file of the plurality of segmented BIN files stores a same number N of frequency slices {“Each of the resource grids 200A and 200B are a [N] time-frequency plane representation”, see Fig. 2, [0027], 2ND sentence} of the received digital data {“[digital data] OFDM symbol and one OFDM subcarrier”, see Fig. 2, [0027], 3rd sentence}, wherein N is greater than 1 {“One or several [greater than 1] resource grids 200A of N.sub.RB.sup.DLN.sub.sc.sup.RB subcarriers and N.sub.symb.sup.DL OFDM symbols is used to describe a transmitted signal in each slot”, see Fig. 2 [0028], 1st sentence}.
As per claim 12, the rejection of claim 1 is incorporated and Bhallamudi discloses wherein the storage unit comprises a hard drive in the spectrum analyzer, a Google drive interfacing with the RTSA, network accessible storage (NAS) interfacing with the spectrum analyzer {“server 200 through a network, such as, for example, a network-attached file server”, see Fig. 3, [0055], last sentence}, a universal serial bus (USB) drive interfacing with the spectrum analyzer, or a hard drive on a personal computer (PC) mapped to the hard drive in the spectrum analyzer {Examiner’s interpretation: the recitation “or” renders this dependent claim as a Markush claim, thus the reference needs only disclose at least one group member to address the claim}.
Referring to claims 13-19 are method claims computer readable medium reciting claim functional language corresponding to the system claim of claim 1, thereby rejected under the same rationale as claim 1 recited above.
Referring to claim 20 is a non-transitory computer readable medium reciting claim functional language corresponding to the system claim of claim 1, thereby rejected under the same rationale as claim 1 recited above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative the current state of the art regarding claim 1’s “circular buffer”, “storage unit”, or “analog to digital converter”: US 20230300114 A1, US 10622096 B2, US 20190254013 A1, US 20190247050 A1, US 20140306688 A1, US 20140220502 A1, and US 20140032150 A1.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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