DETAILED ACTION
Claims 1-20 are presented for examination.
The present application is being examined under the AIA (America Invents Act) First Inventor to File.
This Office Action is Non-Final.
Claims 1, 10 and 18 are independent claims. Claims 2-9, 11-17 and 19-20 are dependent claims.
This action is responsive to the following communication: corresponding claims filed on 05-31-2024.
Domestic Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) (International) is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01-03-2025 is in compliance with the provisions of 37 CFR 1.97.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 8-9, 18-19 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by U.S. Publication No. 2021/0089296 (hereinafter, “Banik”).
As per claim(s) 1, 18, Banik discloses a device comprising:
a plurality of special purpose processors (firs cores, second core…fourth core; Fig. 7) configured to perform, in parallel, (parallel; ¶ [0021]) a power on transition sequence for the device. (booting process that may include “boot process “hard boot, soft boot, warm boot, cold boot” ; ¶ [0021] )
Banik discloses the following; (emphasis added by the Examiner)
“at time T.sub.1 the process 100 may identify from the IET that firmware associated processes may be executed in parallel in a multi-threaded environment to enhance performance and reduce an overall boot time. Thus, the system may switch to a multithreaded environment in which the first processor core 114, the second processor core 124, the third processor core 126 and the fourth processor core 128 may be divided between firmware associated tasks for SoC components and other boot stage tasks.” ¶ [0023]
As per claim(s) 2, 19, Banik discloses a device wherein the power on transition sequence corresponds to restoring previously-cached data of a cache of a general purpose processor of the device. (cache on RAM availibity; ¶ [0028], [0058] )
As per claim(s) 3, Banik discloses a device wherein each of the plurality of special purpose processors includes a local storage for storing a portion of the cached data. (system “may access lower levels of cache (e.g., L4 cache) to reduce latency” according. ¶ [0048] Also, cache 142 illustrated by Fig. 11)
As per claim(s) 8, Banik discloses a device wherein the power on transition sequence corresponds to a device boot sequence. (¶s [0019]-[0021] discloses running a multithreaded process during a boot process)
As per claim(s) 9, Banik discloses a device wherein the power on transition sequence corresponds to exiting a low power state. (begin to execute to boot to a fully operational state, which suggest to a person having ordinary skill a power transition from a lower power state to fully operational state; ¶ [0021] )
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-7, 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2021/0089296 (hereinafter, “Banik”) and further view of U.S. Publication No. 2015/0106613 (hereafter, “Amann”).
As per claim(s) 4, Banik discloses a device further comprising a plurality of device[s] interface controllers, wherein each of the plurality of special purpose processors are configured to perform, in parallel, the power on transition sequence for at least one of the plurality of device[s] interface controllers. (¶ [0023] states “at time T.sub.1 the process 100 may identify from the IET that firmware associated processes may be executed in parallel in a multi-threaded environment to enhance performance and reduce an overall boot time. Thus, the system may switch to a multithreaded environment in which the first processor core 114, the second processor core 124, the third processor core 126 and the fourth processor core 128 may be divided between firmware associated tasks for SoC components and other boot stage tasks” )
Banik does not distinctly disclose a plurality interface controllers.
However, Amann explicitly discloses a plurality interface controllers. (¶ [0032] states “connection logic 116, 126, 136, and 146 for connecting to peripheral devices, e.g., peripheral component interconnect express (PCIe) logic and multi-chip connection logic 118, 128, 138, and 148 for providing a communication connection between the processor chips 110, 120, 130, and 140” and “performing multi-chip initialization using a parallel firmware boot process. The illustrative embodiments use a parallel approach to booting a multi-chip system with the assistance of firmware. The same firmware code is executed on all of the processor chips from the initiation of the boot process until late in the boot process. After a parallel initialization phase the inter-processor link is setup and one processor chip takes over control as the master-chip. “ ¶ [0020] )
It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Banik and Amann because both references are in the same field of endeavor. Ammann’s teaching of plurality of interface controllers would enhance Banik's system by enhancing the boot execution flow, and by extension, faster boot.
As per claim(s) 5, Banik as modified discloses a device wherein the power on transition sequence corresponds to restoring previously-trained operational parameters for the plurality of device interface controllers. (Banik: cache on RAM availibity; ¶ [0028], [0058] and “Such a boot performance analysis may be self-tuning or self-learning and may include predefined training parameters (e.g., “reduce boot time for entries having >100 ms of execution time”). Such training data may be retrieved as part of an OS upgradable script and enable modification if boot time enhancement goals are more aggressive for certain platforms (e.g., internet-of-things compared to client devices” ;) [0068] ) & (memory initialization included a “training operation”; ¶ [0044] and address mapping “based on a knowledge of how the chip-unit is accessible directly after reset” ¶ [0049])
As per claim(s) 6, 20, Banik as modified discloses a device wherein each of the plurality of special purpose processors includes a local storage for storing the previously-trained operational parameters. (Banik: cache on RAM availibity; ¶ [0028], [0058] and “Such a boot performance analysis may be self-tuning or self-learning and may include predefined training parameters (e.g., “reduce boot time for entries having >100 ms of execution time”). Such training data may be retrieved as part of an OS upgradable script and enable modification if boot time enhancement goals are more aggressive for certain platforms (e.g., internet-of-things compared to client devices” ;) [0068] ) & (memory initialization included a “training operation”; ¶ [0044] and address mapping “based on a knowledge of how the chip-unit is accessible directly after reset” ¶ [0049])
As per claim(s) 7, Banik as modified discloses a device wherein each of the plurality of special purpose processors are configured to perform, in parallel, a boot training sequence for determining operational parameters for the plurality of device interface controllers. (Banik: cache on RAM availibity; ¶ [0028], [0058] and “Such a boot performance analysis may be self-tuning or self-learning and may include predefined training parameters (e.g., “reduce boot time for entries having >100 ms of execution time”). Such training data may be retrieved as part of an OS upgradable script and enable modification if boot time enhancement goals are more aggressive for certain platforms (e.g., internet-of-things compared to client devices” ;) [0068] ) & (memory initialization included a “training operation”; ¶ [0044] and address mapping “based on a knowledge of how the chip-unit is accessible directly after reset” ¶ [0049])
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by U.S. Publication No. 2015/0106613 (hereafter, “Amann”).
As per claims 10, Amann discloses a system comprising:
a physical memory; (flash memory; Fig. 1A)
at least one physical general purpose processor; (processor chips; Fig. 1A)
a plurality of special purpose processors each including a local storage; and (logics devices within the processor chip having hip id registers; Fig. 1A)
a control circuit ( boot-assist-logic 170) configured to coordinate each of the plurality of special purpose processors to perform, in parallel, a power on transition sequence for the system using data stored in the local storage. (intera alia: a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system; abstract)
As per claim 11, Amann discloses a system wherein the power on transition sequence corresponds to restoring previously-cached data of a cache of a general purpose processor and the data stored in the local storage corresponds to a portion of the cached data. (the boot process continues in a copy of boot code in the cache now accessible via the recently established mapping.; ¶ [0054])
As per claim 12, Amann discloses a system further comprising a plurality of device interface controllers, wherein the control circuit further configured to coordinate each of the plurality of special purpose processors to perform, in parallel, the power on transition sequence for at least one of the plurality of device interface controllers. (¶ [0032] states “connection logic 116, 126, 136, and 146 for connecting to peripheral devices, e.g., peripheral component interconnect express (PCIe) logic and multi-chip connection logic 118, 128, 138, and 148 for providing a communication connection between the processor chips 110, 120, 130, and 140” and “performing multi-chip initialization using a parallel firmware boot process. The illustrative embodiments use a parallel approach to booting a multi-chip system with the assistance of firmware. The same firmware code is executed on all of the processor chips from the initiation of the boot process until late in the boot process. After a parallel initialization phase the inter-processor link is setup and one processor chip takes over control as the master-chip. “ ¶ [0020] )
As per claim 13, Amann discloses a system wherein the power on transition sequence corresponds to restoring previously-trained operational parameters for the plurality of device interface controllers and the data stored in the local storage corresponds to the previously-trained operational parameters. (memory initialization included a “training operation”; ¶ [0044] and address mapping “based on a knowledge of how the chip-unit is accessible directly after reset” ¶ [0049])
As per claim 14, Amann discloses a system wherein the control circuit is further configured to coordinate each of the plurality of special purpose processors to perform, in parallel, a boot training sequence for determining operational parameters for the plurality of device interface controllers. (memory initialization included a “training operation”; ¶ [0044] and address mapping “based on a knowledge of how the chip-unit is accessible directly after reset” ¶ [0049])
As per claim 15, Amann discloses a system wherein the plurality of device interface controllers correspond to at least one of a memory interface or an input/output interface. (memory controller/multi-chip connection; Fig 1A)
As per claim16, Amann discloses a system wherein the power on transition sequence corresponds to a device boot sequence. (abstract states “a boot process for booting each of a plurality of processor chips” )
As per claim 17, Amann discloses a system wherein the power on transition sequence corresponds to exiting a low power state. (abstract states “a boot process for booting each of a plurality of processor chips”. In other words, the system is transitioning from OFF phase to an ON phase. )
As per claim 18, Amann discloses a method comprising:
receiving an indication to initiate a power on transition sequence for a device; (multi-chip initialization using a parallel firmware boot process; ¶ [0020])
coordinating a plurality of special purpose processors to perform, in parallel, the power on transition sequence; and (performing multi-chip initialization using a parallel firmware boot process. The illustrative embodiments use a parallel approach to booting a multi-chip system with the assistance of firmware. The same firmware code is executed on all of the processor chips from the initiation of the boot process until late in the boot process. After a parallel initialization phase the inter-processor link is setup and one processor chip takes over control as the master-chip. The result is a coherent multi-processor boot process with each processor chip having its own individual physical-address-map and configuration; ¶ [0020])
restoring a state, in parallel by each of the plurality of special purpose processors as part of the power on transition sequence, using data stored in a local storage of each of the plurality of special purpose processors. (inter alia: the initial boot operation 212, that is executed in response to a power-up of the processor chip, is executed from the flash memory 180 first, before the boot code in the flash memory 180 is loaded into the processor cache. Once the boot code transitions from the flash memory 180 to the processor cache, the boot code continues to execute from the processor cache ¶s [0048], [0051], [0053]-[0054] )
As per claim 19, Amann discloses a method wherein the power on transition sequence corresponds to restoring previously-cached data of a cache of a general purpose processor and the data stored in the local storage corresponds to a portion of the cached data. (memory initialization included a “training operation”; ¶ [0044] and address mapping “based on a knowledge of how the chip-unit is accessible directly after reset” ¶ [0049])
As per claim 20, Amann discloses a method wherein the power on transition sequence corresponds to restoring previously-trained operational parameters for a plurality of device interface controllers and the data stored in the local storage corresponds to the previously-trained operational parameters. (memory initialization included a “training operation”; ¶ [0044] and address mapping “based on a knowledge of how the chip-unit is accessible directly after reset” ¶ [0049])
Conclusion
With respect to any newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See MPEP §714.02 and § 2163.06. For example, when responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AUREL PRIFTI/Primary Examiner, Art Unit 2175
Aurel Prifti
Primary Examiner
Art Unit 2175
Tel. (571) 270-1743
Fax (571) 270-2743
aurel.prifti@uspto.gov