Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection mailed on 02/06/2026. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/07/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Savic et al. (US Pat No. 10091295 B1, hereinafter referred to as Savic) and further in view of Kashyap et al. (USPGPUB No. 2023/0359582 A1, hereinafter referred to as Kashyap) and further in view of Chandrasekaran et al. (USPGPUB No. 2022/0052936 A1, hereinafter referred to as Chandra).
Referring to claim 1, Savic discloses an integrated circuit (IC), comprising {“iCNA 700” (see Fig. 7, Col 14, lines 28-34) that includes integrated circuit implementation “system-on-chip (SoC), application-specific integrated circuits (ASICs)” (Col 3, line 41)}:
an application accelerator circuit {“’hardware accelerator’ broadly refers to any hardware that performs “hardware acceleration” to perform certain functions faster and more efficient”, see Figs. 2 and 3, Col 3, lines 45-47} configured to detect an IO transaction {“performance metrics such as latency, IOPS (Input/Output Operations Per Second), and other performance [detection] measurements”, see Figs. 2 and 3, Col 10, lines 42-44; another IO transaction type “The second API for management and orchestration services allows [I/O transactions] new services (e.g., data deduplication, data compression, data encryption, etc.” (Col 8, lines 17-19)} related to an application program executing on a processor {processors “distributed compute elements 252, 262, and 272”, see Figs. 2 and 3, Col 10, lines 42-44}, and to perform a function {among those IO transactions produce/perform a function “implement functions for generating and managing metadata”, see Figs. 2 and 3, Col 8, lines 28-30} of the application program based on the IO transaction {“which is used for handling scale-out aspects … and/or run management and orchestration services [of the application program]”, see Figs. 2 and 3, Col 8, lines 28-32}.
Savic does not appear to explicitly disclose wherein the application accelerator circuit configured to interface between a host executing an application program and a first input/output (IO) device, and wherein the application accelerator circuit comprises discrete logic configured to detect an IO transaction of the application program based on one or more of an address and an identifier of the IO transaction, and to perform a function of the application program based on detection of the IO transaction and configurable rules: wherein the IO transaction comprises one of an IO transaction issued by the application program and an IO transaction directed to the application program.
However, Kashyap discloses wherein the application accelerator circuit configured to interface between a host {“accelerators 842”, (see Fig. 8 [0085]) interfacing to host “host interface circuitry” (see Figs. 7a, 7B, 7C, and 8, [0082], last sentence)} executing an application program {“ a host connected via a host interface, VM or [software/hardware] container executed by processor”, see Fig. 8 [0025]} and a first input/output (IO) device {“remote direct memory access (RDMA)-enabled NIC, SmartNIC, … data processing unit (DPU), or [input/output] edge processing unit ”, see Figs. 1 and 8 [0018]}, and wherein the application accelerator circuit comprises discrete logic {“ System management can initiate a new or another transaction from the worker nodes”, see Figs. 4 and 5 [0052], last sentence} configured to detect an IO transaction {“manage storage transactions”, see Figs. 6 and 8 [0058], last sentence} of the application program based on one or more of an address {“transmitted into packets, that include destination and source addresses along with network control information and error detection hash values”, see Figs. 6 and 8 [0059], last sentence} and an identifier of the IO transaction {identifier “using information stored in a ternary content-addressable memory (TCAM) tables”, see Figs. 6 and 8 [0061], 1st sentence}, and to perform a function {a plurality of functions “packet parsing (parser), exact match-action (e.g., small exact match (SEM) engine or a large exact match (LEM)), wildcard match-action (WCM), longest prefix match block (LPM), a hash block (e.g., receive side scaling (RSS)), a packet modifier (modifier), or traffic manager (e.g., transmit rate metering or shaping)”, see Figs. 6 and 8 [0061], last two sentences} of the application program based on detection of the IO transaction {“ can implement access control list (ACL) or packet drops [transactions]” based on detection as claimed, see Figs. 6 and 8 [0061], last sentence} and configurable rules {configurable rules “packets to identify packet processing rules and next hops”, see Figs. 6 and 8 [0061], 1st sentence}:
wherein the IO transaction comprises one of an IO transaction issued by the application program {“[application memory controller to generate and issue commands to memory 830.” see Figs. 6 and 8 [0086]} and an IO transaction directed to the application program {“ may cancel a transaction and notify [directed to the application program] the worker nodes to abort the operation”, see Fig. 4 [0052], last two sentences}.
Savic and Kashyap are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic’s “iCNA 700" (see Fig. 7) incorporating Kashyap’s “accelerators 842” (see Fig. 8, [0085]).
The suggestion/motivation for doing so would have been to provide an endpoint switch that can communicate with worker nodes using a reliable transport protocol and the endpoint switch can maintain connection state information for packet communications to or from the worker nodes (Kashyap [0014], 2nd sentence).
Therefore, it would have been obvious to combine Kashyap with Savic to obtain the invention as specified in the instant claim(s).
Neither Savic or Kashyap appears to explicitly disclose wherein the application acceleration circuit comprises discrete logic and a programmable look-up table, and wherein the discrete logic is configured to detect an IO transaction, look-up a function of the application program in the programmable look-up table based on features of the IO transaction and perform the function of the application program.
However, Chandra discloses wherein the application acceleration circuit comprises discrete logic {“specialized hardware modules purposely optimized to handle [discrete logic] specific tasks at wire speed” ([0084]) including discrete logic “discrete packet processing operations such as L7 applications” (see Fig. 6, [0083])} and a programmable look-up table {“pipeline can have multiple parsers and can have multiple deparsers. The parser can be a P4 compliant programmable parser” ([0103], 1st couple sentences) those pipeline parsers “pipeline MPUs of the match-action units 905, 910, 911, 912”, see Fig. 8, [0105]}, and wherein the discrete logic is configured to detect an IO transaction {“AXI interface 802 may include features that support unaligned data transfers using byte strobes, burst based transactions”, see Fig. 7 [0093]}, look-up a function {“table entries, or other data according to the actions specified”, see Fig. 8 [0102]} of the application program {“actions specified by the [application] P4 program”, see Fig. 8 [0102]} in the programmable look-up table {“table engine 906 may be configured to hash, lookup, and/or compare keys to table entries”, see Figs. 7 and 8 [0106], 2nd sentence} based on features of the IO transaction {“[features] PHV fields to use as a lookup key”, see Figs. 7 and 8, [0106], 3rd sentence} and perform the function of the application program {“which then [perform the function] generates a table selection key and compares the result using a TCAM to select the active tables”, see Figs. 7 and 8 [0107], last two sentences}.
Savic/Kashyap and Chandra are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic/Kashyap’s device incorporating Chandra’s “pipeline MPUs of the match-action units 905, 910, 911, 912 [respectively]” (see Fig. 8, [0105]).
The suggestion/motivation for doing so would have been to implement discrete packet processing operations such as L7 applications in a manner that provides fast path performance as is expected of data plane processing (Chandra [0083]).
Therefore, it would have been obvious to combine Chandra with Savic/Kashyap to obtain the invention as specified in the instant claim(s).
As per claim 3, the rejection of claim 1 is incorporated and Kashyap discloses wherein the function comprises processing a subsequent entry of a submission queue {processing via “include descriptors that reference data or [subsequent entry] packets in transmit queue 606”, see Figs. 6 and 8 [0066]} of the application program, and wherein the discrete logic is further configured to:
format the subsequent entry {“packet may be used herein to refer to various formatted collections of bits that may be sent across a network”, see Fig. 3 [0041]} of the submission queue as a message {“Computation 304 can provide the summation into a [message] packet and send the packet upstream to an upstream switch”, see Fig. 3 [0044], last sentence};
transmit the message to the IO device {“data slots in buffers 326 using counters or registers to determine when an aggregation is complete”, see Fig. 3 [0040], 1st sentence};
and write a completion transaction {“To drain the list of completed slots, buffer management 308 can cause transmission of a packet with the data from a slot and generate (e.g., by packet replication) a second packet that is recirculated”, see Fig. 3 [0040], last sentence} to a completion queue of the application program {“[application specific] Descriptor queues 620 can include descriptors that reference data or packets in transmit queue 606 or receive queue 608”, see Figs. 6 and 8 [0066]; such descriptor queue including completion descriptor “To drain the list of completed slots, buffer management 308” (see Fig. 3, [0040], last sentence)}.
Referring to claim 8, Savic discloses a system {“computing system having a converged infrastructure that is implemented using distributed compute element”, see Fig. 1, Col 3, lines 63-65}, comprising:
` a network interface controller (NIC) {“network interface controller”, see Fig. 2, Col 7, lines 52-53}:
an application accelerator circuit {“multiple hardware-based accelerators”, Col 3, lines 36-37} comprising discrete logic {“[discrete logic performing] storage processing functions (e.g., data hashing, erasure coding, data deduplication, data compression, data encryption, data placement, etc.”, see Fig. 2, Col 8, lines 2-5} and a programmable look-up table {“services to query databases [table(s)]”, Col 4, line 50};
and a system-on-chip comprising a processor {“system-on-chip (SoC)” (Col 3, line 41)}, memory encoded with an application program {“translating block level calls to disk from a file system of the OS to an internal addressing scheme of the [memory encoded] flash NAND 740.”, see Fig. 7, Col 14, lines 40-41} that comprises instructions that, when executed by the processor {processors “distributed compute elements 252, 262, and 272”, see Figs. 2 and 3, Col 10, lines 42-44}, cause the processor to perform a first function {among those IO transactions produce/perform a function “implement functions for generating and managing metadata”, see Figs. 2 and 3, Col 8, lines 28-30}, a host interface configured to interface with the host device {host interface “a first API (application programming interface) to the host application server nodes 250 which enables the host application server nodes 250”, see Figs. 2 and 3, Col 7, line 66 though Col 8 line 1}, a memory controller configured to interface with the memory device {“FTL controller 75”, see Fig. 7, Col 14, lines 38-41}, an offload engine configured to perform a function {“offload network processing functions … to the [offload engine] compute elements 252”, see Figs. 2 and 3, Col 8, lines 1-5} of one or more the host device and the application program {“processing functions and storage processing functions”, see Figs. 2 and , Col 8, lines 1-4}, a processor {“PCIe interface 760 provides an interface that enables the SoC 710 to communicate” (see Fig. 7, Col 14, lines 42-44) and additional processing by converting PCIe and SAS “the storage interface adapters 277 comprise PCIe-to-SAS host adapters, which enables the storage media node 270-m to be connected to one or more DAEs 278 using corresponding SAS connectors 279” (Col 6, line 67 through Col 7, line 3.}, and an interconnect configured to interface with the host interface {interconnect “data to and from persistent storage elements of the respective data storage arrays 273 using appropriate storage interfaces,” (Col 9, lines 12-17) those storage interfaces by “various storage interface protocols” (Col 8, lines 8-12) interfaces “{host interface “a first API (application programming interface)” (see Figs. 2 and 3, Col 7, line 66)}, the memory controller, the offload engine, the processor, and the application accelerator circuit {“second API for management and orchestration services… to be implemented by the compute elements 252… in real-time”, see Figs. 2 and 3, Col 8, lines 8-12};
wherein the application accelerator circuit is configured to detect an input/output (IO) transaction of the IO device {“performance metrics such as latency, IOPS (Input/Output Operations Per Second), and other performance [detection] measurements”, see Figs. 2 and 3, Col 10, lines 42-44; another IO transaction type “The second API for management and orchestration services allows [I/O transactions] new services (e.g., data deduplication, data compression, data encryption, etc.” (Col 8, lines 17-19)} that relates to the application program, and to perform a second function based on the detected IO transaction {“ metadata allows multiple copies of data to be created (e.g. active, backup, and compliance copies) and provide information as to the locations of such copies. Further, metadata provides the ability to create [subsequent IO transactions] workflows around stored content and share the stored content appropriately [to a particular IO device or storage]” (see Figs. 2 and 3, Col 8, lines 49-54)}.
Savic does not appear to explicitly disclose an input/output device configured to interface with a remote IO device; wherein the application accelerator circuit comprises discrete logic configured to monitor messages exchanged between the application accelerator circuit and the IO device and to detect a first IO transaction of the application program based on one or more of an address and an identifier of the first IO transaction;
Furthermore, Kashyap discloses input/output device {“accelerators 842”, (see Fig. 8 [0085]) interfacing to host “host interface circuitry” (see Figs. 7a, 7B, 7C, and 8, [0082], last sentence)} configured to interface with a remote IO device {“remote direct memory access (RDMA)-enabled NIC, SmartNIC, … data processing unit (DPU), or [input/output] edge processing unit ”, see Figs. 1 and 8 [0018]};
wherein the application accelerator circuit comprises discrete logic {“ System management can initiate a new or another transaction from the worker nodes”, see Figs. 4 and 5 [0052], last sentence} configured to monitor messages exchanged {“Computation 304 can provide the summation into a [message] packet and send the packet upstream to an upstream switch”, see Fig. 3 [0044], last sentence} between the application accelerator circuit and the IO device {“data slots in buffers 326 using counters or registers to determine when an aggregation is complete”, see Fig. 3 [0040], 1st sentence} and to detect a first IO transaction of the application program {“manage storage transactions”, see Figs. 6 and 8 [0058], last sentence} based on one or more of an address {“transmitted into packets, that include destination and source addresses along with network control information and error detection hash values”, see Figs. 6 and 8 [0059], last sentence} and an identifier of the first IO transaction {identifier “using information stored in a ternary content-addressable memory (TCAM) tables”, see Figs. 6 and 8 [0061], 1st sentence};
Savic and Kashyap are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic’s “iCNA 700” (see Fig. 7) incorporating Kashyap’s “accelerators 842” (see Fig. 8, [0085]).
The suggestion/motivation for doing so would have been to provide an endpoint switch that can communicate with worker nodes using a reliable transport protocol and the endpoint switch can maintain connection state information for packet communications to or from the worker nodes (Kashyap [0014], 2nd sentence).
Therefore, it would have been obvious to combine Kashyap with Savic/Kutch to obtain the invention as specified in the instant claim(s).
Neither Savic or Kashyap appears to explicitly disclose wherein the application acceleration circuit comprises discrete logic and a programmable look-up table, and wherein the discrete logic is configured to detect an IO transaction, look-up a function of the application program in the programmable look-up table based on features of the IO transaction and perform the function of the application program.
However, Chandra discloses wherein the application acceleration circuit comprises discrete logic {“specialized hardware modules purposely optimized to handle [discrete logic] specific tasks at wire speed” ([0084]) including discrete logic “discrete packet processing operations such as L7 applications” (see Fig. 6, [0083])} and a programmable look-up table {“pipeline can have multiple parsers and can have multiple deparsers. The parser can be a P4 compliant programmable parser” ([0103], 1st couple sentences) those pipeline parsers “pipeline MPUs of the match-action units 905, 910, 911, 912”, see Fig. 8, [0105]}, and wherein the discrete logic is configured to detect an IO transaction {“AXI interface 802 may include features that support unaligned data transfers using byte strobes, burst based transactions”, see Fig. 7 [0093]}, look-up a function {“table entries, or other data according to the actions specified”, see Fig. 8 [0102]} of the application program {“actions specified by the [application] P4 program”, see Fig. 8 [0102]} in the programmable look-up table {“table engine 906 may be configured to hash, lookup, and/or compare keys to table entries”, see Figs. 7 and 8 [0106], 2nd sentence} based on features of the IO transaction {“[features] PHV fields to use as a lookup key”, see Figs. 7 and 8, [0106], 3rd sentence} and perform the function of the application program {“which then [perform the function] generates a table selection key and compares the result using a TCAM to select the active tables”, see Figs. 7 and 8 [0107], last two sentences}.
Savic/Kashyap and Chandra are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic/Kashyap’s device incorporating Chandra’s “pipeline MPUs of the match-action units 905, 910, 911, 912 [respectively]” (see Fig. 8, [0105]).
The suggestion/motivation for doing so would have been to implement discrete packet processing operations such as L7 applications in a manner that provides fast path performance as is expected of data plane processing (Chandra [0083]).
Therefore, it would have been obvious to combine Chandra with Savic/Kashyap to obtain the invention as specified in the instant claim(s).
Claims 2, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Savic in view of Kashyap in view of Chandra and further view of Biederman et al. (USPGPUB No. 2024/0111691 A1, hereinafter referred to as Biederman).
As per claim 2, the rejection of claim 1 is incorporated and Kashyap discloses wherein the function comprises one or more of controlling an IO device to perform a subsequent IO transaction {“starting sequence number and increase sequence numbers for subsequent packets”, see Fig. 4 [0048], 1st sentence}:
loading a receive queue of the application program {“ Receive queue 608”, see Figs. 6 and 8 [0066]};
loading a submission queue of the application program {“ Transmit queue 606”, see Figs. 6 and 8 [0066]};
processing a subsequent entry of the submission queue {processing via “include descriptors that reference data or [subsequent entry] packets in transmit queue 606”, see Figs. 6 and 8 [0066]};
generating an application-specific completion descriptor based the IO transaction {“[application specific] Descriptor queues 620 can include descriptors that reference data or packets in transmit queue 606 or receive queue 608”, see Figs. 6 and 8 [0066]; such descriptor queue including completion descriptor “To drain the list of completed slots, buffer management 308” (see Fig. 3, [0040], last sentence)};
Neither one of the group consisting of Savic, Kashyap, and Chandra appears to explicitly disclose assigning a timestamp to the IO transaction and performing a transaction-level analysis based on the IO transaction and the timestamp.
Furthermore, Biederman discloses assigning a timestamp to the IO transaction {“[assigned timestamp] precise time is communicated by IEEE1588”, [0101]} and performing a transaction-level analysis {“may use [transaction-level] two-way latency measurements, that are divided by two to determine one-way latency”, see Figs. 5 and 6, [0065], 2nd sentence} based on the IO transaction and the timestamp {“information in the TPTs 116a, 116b”, see Fig. 5, [0065], 1st sentence}.
Savic/Kashyap/Chandra and Biederman are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic/Kashyap/Chandra’s device incorporating Biederman’s “NIC accessible portion 608” (see Fig. 6, [0067])
The suggestion/motivation for doing so would have been to provide allow computing systems to utilize memory more efficiently than systems which do not use precise time. In addition and/or alternatively, by leveraging precise time, embodiments disclosed herein may provide better determinism than systems which do not use precise time along with leveraging precise time, embodiments disclosed herein may allow computing systems to utilize bandwidth more efficiently than systems which do not use precise time (Biederman [0015]).
Therefore, it would have been obvious to combine Biederman with Savic/Kashyap/Chandra to obtain the invention as specified in the instant claim(s).
As per claim 10, the rejection of claim 8 is incorporated and Kashyap discloses wherein the second comprises one or more of:
loading a receive queue of the application program {“ Receive queue 608”, see Figs. 6 and 8 [0066]};
loading a submission queue of the application program {“ Transmit queue 606”, see Figs. 6 and 8 [0066]};
processing a subsequent entry of the submission queue {processing via “include descriptors that reference data or [subsequent entry] packets in transmit queue 606”, see Figs. 6 and 8 [0066]};
generating an application-specific completion descriptor based the IO transaction {“[application specific] Descriptor queues 620 can include descriptors that reference data or packets in transmit queue 606 or receive queue 608”, see Figs. 6 and 8 [0066]; such descriptor queue including completion descriptor “To drain the list of completed slots, buffer management 308” (see Fig. 3, [0040], last sentence)};
Neither Savic or Kashyap appear to explicitly disclose and assigning a timestamp to the IO transaction and performing a transaction-level analysis based on the IO transaction and the timestamp.
Furthermore, Biederman discloses and assigning a timestamp to the IO transaction {“[assigned timestamp] precise time is communicated by IEEE1588”, [0101]} and performing a transaction-level analysis {“may use [transaction-level] two-way latency measurements, that are divided by two to determine one-way latency”, see Figs. 5 and 6, [0065], 2nd sentence} based on the IO transaction and the timestamp {“information in the TPTs 116a, 116b”, see Fig. 5, [0065], 1st sentence}.
Savic/Kashyap/Chandra and Biederman are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic/Kashyap/Chandra device incorporating Biederman’s “NIC accessible portion 608” (see Fig. 6, [0067])
The suggestion/motivation for doing so would have been to provide allow computing systems to utilize memory more efficiently than systems which do not use precise time. In addition and/or alternatively, by leveraging precise time, embodiments disclosed herein may provide better determinism than systems which do not use precise time along with leveraging precise time, embodiments disclosed herein may allow computing systems to utilize bandwidth more efficiently than systems which do not use precise time ( [0015]).
Therefore, it would have been obvious to combine Biederman with Savic/Kashyap/Chandra to obtain the invention as specified in the instant claim(s).
As per claim 11, the rejection of claim 8 is incorporated and Kashyap discloses wherein the second function comprises one or more of processing a subsequent entry of a submission queue {processing via “include descriptors that reference data or [subsequent entry] packets in transmit queue 606”, see Figs. 6 and 8 [0066]} of the application program; and the application accelerator circuit is further configured to:
format the subsequent entry {“packet may be used herein to refer to various formatted collections of bits that may be sent across a network”, see Fig. 3 [0041]} of the submission queue as a message {“Computation 304 can provide the summation into a [message] packet and send the packet upstream to an upstream switch”, see Fig. 3 [0044], last sentence};
transmit the message to the NIC {“data slots in buffers 326 using counters or registers to determine when an aggregation is complete”, see Fig. 3 [0040], 1st sentence}; write a completion transaction {“To drain the list of completed slots, buffer management 308 can cause transmission of a packet with the data from a slot and generate (e.g., by packet replication) a second packet that is recirculated”, see Fig. 3 [0040], last sentence} to a completion queue of the application program {“[application specific] Descriptor queues 620 can include descriptors that reference data or packets in transmit queue 606 or receive queue 608”, see Figs. 6 and 8 [0066]; such descriptor queue including completion descriptor “To drain the list of completed slots, buffer management 308” (see Fig. 3, [0040], last sentence)}.
Neither one of the group consisting of Savic, Kashyap, and Chandra appears to explicitly disclose assigning a timestamp to the IO transaction and performing a transaction-level analysis based on the IO transaction and the timestamp.
Furthermore, Biederman discloses assigning a timestamp to the IO transaction {“[assigned timestamp] precise time is communicated by IEEE1588”, [0101]} and performing a transaction-level analysis {“may use [transaction-level] two-way latency measurements, that are divided by two to determine one-way latency”, see Figs. 5 and 6, [0065], 2nd sentence} based on the IO transaction and the timestamp {“information in the TPTs 116a, 116b”, see Fig. 5, [0065], 1st sentence}.
Savic/Kashyap/Chandra and Biederman are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic/Kashyap’s device incorporating Biederman’s “NIC accessible portion 608” (see Fig. 6, [0067])
The suggestion/motivation for doing so would have been to provide allow computing systems to utilize memory more efficiently than systems which do not use precise time. In addition and/or alternatively, by leveraging precise time, embodiments disclosed herein may provide better determinism than systems which do not use precise time along with leveraging precise time, embodiments disclosed herein may allow computing systems to utilize bandwidth more efficiently than systems which do not use precise time ( [0015]).
Therefore, it would have been obvious to combine Biederman with Savic/Kashyap/Chandra to obtain the invention as specified in the instant claim(s).
Claims 4, 5, 6, 7, 9, 12, 13, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over by Savic and further in view of Kashyap and further in view of Chandra and further in view of Kutch et al. (USPGPUB No. 2021/0117360 A1, hereinafter referred to as Kutch).
As per claim 4, the rejection of claim 1 is incorporated however neither one of the group consisting of Savic, Kashyap, and Chandra appears to explicitly disclose any limitation in this dependent claim.
However, Kutch discloses wherein the function comprises generating an application-specific completion descriptor based on the IO transaction {“NIM provides [application specific] auto-doorbell to supply empty Rx descriptors to NIC. At (2), NIC reads a descriptor from descriptor ring handler (DR_H). At (3), NIC receive”, see Fig. 23 [0188], 1st sentence}.
Savic/Kashyap/Chandra and Kutch are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic/Kashyap/Chandra’s device incorporating Kutch’s “NIM” and subcomponent “PHY 4114” and “802” respectively (see Figs. 41 and 8a).
The suggestion/motivation for doing so would have been to provide Faster path packets with lower latency access to the NEXT packet processing pipeline using offload engines available to process (Kutch [0163]).
Therefore, it would have been obvious to combine Kutch with Savic/Kashyap/Chandra to obtain the invention as specified in the instant claim(s).
As per claim 5, the rejection of claim 4 is incorporated and Kutch discloses wherein the discrete logic is further configured to perform an additional function of the application program {“utilize specific doorbell or completion queues or write-back descriptors” and perform additional functions “to be accessed by the NIC, or convert NEXT format descriptors to NIC specific format” (see Figs. 8b and 10, both cited from [0153]} based on the application-specific completion descriptor {“NIM provides [application specific] auto-doorbell to supply empty Rx descriptors to NIC. At (2), NIC reads a descriptor from descriptor ring handler (DR_H). At (3), NIC receive”, see Fig. 23 [0188], 1st sentence}.
As per claim 6, the rejection of claim 1 is incorporated and Kutch discloses wherein function comprises decoding a payload of the IO transaction {multiple functions such as “to be accessed by the NIC, or convert NEXT format descriptors to NIC specific format” (see Figs. 8b and 10, [0153]) as well as “determine which packet is to be transmitted and what NIC to use and what ring on the NIC to write a descriptor to” in response to doorbell updates, see Figs. 18 and 19 {0160} ; “NIM provides [application specific] auto-doorbell to supply empty Rx descriptors to NIC. At (2), NIC reads a descriptor from descriptor ring handler (DR_H). At (3), NIC receive”, see Fig. 23 [0188], 1st sentence}.
The 103 motivation for this dependent claim relied upon as recited in claim 4 above.
As per claim 7, the rejection of claim 1 is incorporated and Kutch discloses wherein the programmable look-up table comprises a {“one or more discrete or integrated NICs 1800.” That performs lookup as claimed, see Fig. 19 [0152], 2nd sentence} programmable match-action table {“[match-action table] Mapping table can include a NEXT field information about corresponding NIC's descriptor field”, see Figs. 18 and 19 [0156]}.
The 103 motivation for this dependent claim relied upon as recited in claim 4 above.
As per claim 9, the rejection of claim 8 is incorporated however neither one of the group consisting of Savic, Kashyap, and Chandra appears to explicitly disclose any limitation in this dependent claim.
However, Kutch discloses wherein the host device is configured to:
allocate a buffer for the application program in the memory {two methods of buffer allocation “a subset of buffers is allocated to store only enqueue requests while another subset is reserved for only dequeue requests. Other ways for allocating the buffers, such as by core, by thread, by request type, by priority, service level agreement, etc., may also be used”, see Fig. 17, both cited in [0146]};
and configure a direct memory access (DMA) engine of the NIC {“For a packet transmission, a [DMA engine] VNF or other VEE 2420 can prepare a packet for transmission”, see Fig. 24 [0212], 1st sentence} to write to the buffer {“update the Tx descriptor to point to a memory address of that packet in a buffer 2422”, see Fig. 24 [0212], 1st sentence};
and programmable look-up table to cause the discrete logic to detect the IO transaction related {“[application accelerator circuit subcomponent] NEXT 2410 can be notified of the descriptor update by ringing a doorbell (e.g., tail bump)”, see Fig. 24 [0212], 2nd sentence} to the application program based on a destination addresses {“Setup of split of header from payload can utilize packet processing input-output memory management unit (IOMMU) [source/destination] Address Translation”, see Fig. 24 [0208], 2nd sentence} of a write transaction of the DMA engine {“Tx descriptor can indicate two buffers to DMA content from, including (1) packet header buffer (e.g., header (hdr) buffer 2414),”, see Fig. 24 [0213], 2nd sentence}.
Savic/Kashyap/Chandra and Kutch are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic/Kashyap/Chandra’s device incorporating Kutch’s “NIM” and subcomponent “PHY 4114” and “802” respectively (see Figs. 41 and 8a).
The suggestion/motivation for doing so would have been to provide Faster path packets with lower latency access to the NEXT packet processing pipeline using offload engines available to process (Kutch [0163]).
Therefore, it would have been obvious to combine Kutch with Savic/Kashyap/Chandra to obtain the invention as specified in the instant claim(s).
As per claim 12, the rejection of claim 8 is incorporated and Kutch discloses wherein the function comprises generating an application-specific completion descriptor based on the IO transaction {“NIM provides [application specific] auto-doorbell to supply empty Rx descriptors to NIC. At (2), NIC reads a descriptor from descriptor ring handler (DR_H). At (3), NIC receive”, see Fig. 23 [0188], 1st sentence}.
The 103 motivation for this dependent claim relied upon as claim 9.
As per claim 13, the rejection of claim 12 is incorporated and Kutch discloses wherein the discrete logic is further configured to perform an additional function of the application program based {“utilize specific doorbell or completion queues or write-back descriptors” and perform additional functions “to be accessed by the NIC, or convert NEXT format descriptors to NIC specific format” (see Figs. 8b and 10, both cited from [0153]} on the application-specific completion descriptor {“NIM provides [application specific] auto-doorbell to supply empty Rx descriptors to NIC. At (2), NIC reads a descriptor from descriptor ring handler (DR_H). At (3), NIC receive”, see Fig. 23 [0188], 1st sentence}.
As per claim 14, the rejection of claim 8 is incorporated and Kutch discloses wherein the look-up table is programmable to cause the discrete logic to perform one or more of multiple functions of the application program {multiple functions such as “to be accessed by the NIC, or convert NEXT format descriptors to NIC specific format” (see Figs. 8b and 10, [0153]) as well as “determine which packet is to be transmitted and what NIC to use and what ring on the NIC to write a descriptor to” in response to doorbell updates, see Figs. 18 and 19 {0160}} based on the detected IO transaction {“NIM provides [application specific] auto-doorbell to supply empty Rx descriptors to NIC. At (2), NIC reads a descriptor from descriptor ring handler (DR_H). At (3), NIC receive”, see Fig. 23 [0188], 1st sentence}.
The 103 motivation For this dependent claim relied upon as claim 9.
As per claim 15, the rejection of claim 8 is incorporated and Kutch discloses wherein the circuit look-up table comprises a {“one or more discrete or integrated NICs 1800.”, see Fig. 19 [0152], 2nd sentence; “PHY circuitry 4114 can include encoding and decoding circuitry (not shown) to encode and decode data packets”, see Fig. 41 [0303], 1st sentence} programmable match-action tables {“[match-action tables] Mapping table can include a NEXT field information about corresponding NIC's descriptor field”, see Figs. 18 and 19 [0156]}.
The 103 motivation for this dependent claim relied upon as claim 9.
Claims 16, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over by Savic in view of Kutch and further in view of Kashyap and further in view of Chandra.
Referring to claim 16, Savic discloses a method, comprising: monitoring a channel {“storage communications network implemented using Fiber Channel-based network switches” (see Figs. 1 and 2, Col 1, lines 20-22) such as “implement a [channel] CE communications network to enable communication between the application servers” (see Fig. 2, Col 6, lines 39-41}, by an application accelerator circuit {“’hardware accelerator’ broadly refers to any hardware that performs “hardware acceleration” to perform certain functions faster and more efficient”, see Figs. 2 and 3, Col 3, lines 45-47}, based on a match-action function that includes a configurable input/output (IO) transaction pattern {among those IO transactions produce/perform a function “implement functions for generating and managing metadata”, see Figs. 2 and 3, Col 8, and a corresponding configurable action {corresponding actions “management and orchestration services allows [I/O transactions] new services (e.g., data deduplication, data compression, data encryption, etc.” (Col 8, lines 17-19)} that relates to the application program {“processing functions and storage processing functions”, see Figs. 2 and , Col 8, lines 1-4}};
and detecting an IO transaction of the application program on the channel that matches the IO transaction pattern {“performance metrics such as latency, IOPS (Input/Output Operations Per Second), and other performance [detection] measurements”, see Figs. 2 and 3, Col 10, lines 42-44; another IO transaction type “The second API for management and orchestration services allows [I/O transactions] new services (e.g., data deduplication, data compression, data encryption, etc.” (Col 8, lines 17-19)}, by the application accelerator circuit, based on the monitoring (“CE ports provides a data entry point and data exit point to and from the CIDS 280” for the claimed monitoring;
and performing the function of the application program, by the discrete logic of the application accelerator circuit, {“metadata allows multiple copies of data to be created (e.g. active, backup, and compliance copies) and provide information as to the locations of such copies. Further, metadata provides the ability to create [subsequent IO transactions] workflows around stored content and share the stored content appropriately [to a particular IO device or storage]” (see Figs. 2 and 3, Col 8, lines 49-54);
Savic does not appear to explicitly disclose monitoring a direct memory access (DMA) channel;
However, Kutch discloses monitoring a direct memory access (DMA) channel {“DMA operations. Next, P2PB component can register with the NEXT PFD it has been assigned to by a configuration utility (e.g., configured by system administrator). Registering with the NEXT PFD can include opening a [DMA] communication channel with NEXT PFD,”, see Figs. 19 and 29 [0238], 2nd and 3rd sentences};
Savic and Kutch are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic’s “iCNA 700” (see Fig. 7) incorporating Kutch’s “NIM” and subcomponent “PHY 4114” and “802” respectively (see Figs. 41 and 8a).
The suggestion/motivation for doing so would have been to provide Faster path packets with lower latency access to the NEXT packet processing pipeline using offload engines available to process (Kutch [0163]).
Therefore, it would have been obvious to combine Kutch with Savic to obtain the invention as specified in the instant claim(s).
Neither Savic or Kutch appears to explicitly disclose monitoring a direct memory access (DMA) channel between a host executing an application program and an input/output (IO) device.
However, Kashyap discloses monitoring a direct memory access (DMA) channel {“ quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE) [channels]”, see Fig. 8 [0094]} between a host executing an application program {“accelerators 842”, (see Fig. 8 [0085]) interfacing to host “host interface circuitry” (see Figs. 7a, 7B, 7C, and 8, [0082], last sentence)} and an input/output (IO) device {“remote direct memory access (RDMA)-enabled NIC, SmartNIC, … data processing unit (DPU), or [input/output] edge processing unit ”, see Figs. 1 and 8 [0018]}.
Savic/Kutch and Kashyap are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic/Kutch’s device incorporating Kashyap’s “accelerators 842” (see Fig. 8, [0085]).
The suggestion/motivation for doing so would have been to provide an endpoint switch that can communicate with worker nodes using a reliable transport protocol and the endpoint switch can maintain connection state information for packet communications to or from the worker nodes (Kashyap [0014], 2nd sentence).
Therefore, it would have been obvious to combine Kashyap with Savic/Kutch to obtain the invention as specified in the instant claim(s).
Neither one of the group consisting of Savic, Kutch, and Kashyap appears to explicitly disclose detecting an IO transaction of an application program, on a direct memory access (DMA) channel between a host executing the an application program and an input/output (IO) device, based on one or more of an address and an identifier of the IO transaction, by discrete logic of an application accelerator circuit, looking up a function of the application program in a programmable look-up table of the application accelerator circuit based on features of the IO transaction, by the discrete logic of the application accelerator circuit;
However, Chandra discloses detecting an IO transaction {“AXI interface 802 may include features that support unaligned data transfers using byte strobes, burst based transactions”, see Fig. 7 [0093]} of an application program {“actions specified by the [application] P4 program”, see Fig. 8 [0102]}, on a direct memory access (DMA) channel {“AXI is a high-speed/high-end on-chip bus protocol and has channels” (see Fig. 7, [0093]) such channels via HBM bandwidth “DMA to/from memory regions in HBM or in the host device and various other actions” ([0094])} between a host executing the an application program {“Programs executable by the MPU or a match action pipeline can be any programs such as P4 programs related to reading table data, building headers, DMA to/from memory regions in HBM or in the host device”, see Fig. 8, [0094]} and an input/output (IO) device {“the packet data communication on-chip interconnect system according”, [0093]}, based on one or more of an address {“table address may be reported back to the table engine, causing future reads to the same table address to stall until the MPU has released the table lock”, see Fig. 8} and an identifier {“special metadata values such as hash value from table lookup”, see Fig. 8, [0095], last sentence} of the IO transaction, by discrete logic of an application accelerator circuit {“specialized hardware modules purposely optimized to handle [discrete logic] specific tasks at wire speed” ([0084]) including discrete logic “discrete packet processing operations such as L7 applications” (see Fig. 6, [0083])}, looking up a function of the application program {“actions specified by the [application] P4 program”, see Fig. 8 [0102]} in a programmable look-up table {“pipeline can have multiple parsers and can have multiple deparsers. The parser can be a P4 compliant programmable parser” ([0103], 1st couple sentences) those pipeline parsers “pipeline MPUs of the match-action units 905, 910, 911, 912”, see Fig. 8, [0105]} of the application accelerator circuit based on features of the IO transaction {“[features] PHV fields to use as a lookup key”, see Figs. 7 and 8, [0106], 3rd sentence}, by the discrete logic of the application accelerator circuit {“AXI interface 802 may include features that support unaligned data transfers using byte strobes, burst based transactions” received by discrete logic “specialized hardware modules” subcomponent, see Fig. 7 [0093]};
Savic/Kutch/Kashyap and Chandra are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic/Kutch/Kashyap’s device incorporating Chandra’s “pipeline MPUs of the match-action units 905, 910, 911, 912 [respectively]” (see Fig. 8, [0105]).
The suggestion/motivation for doing so would have been to implement discrete packet processing operations such as L7 applications in a manner that provides fast path performance as is expected of data plane processing (Chandra [0083]).
Therefore, it would have been obvious to combine Chandra with Savic/Kutch/Kashyap to obtain the invention as specified in the instant claim(s).
As per claim 19, the rejection of claim 16 is incorporated and Kutch discloses wherein the function comprises:
generating an application-specific completion descriptor based on the IO transaction {“NIM provides [application specific] auto-doorbell to supply empty Rx descriptors to NIC. At (2), NIC reads a descriptor from descriptor ring handler (DR_H). At (3), NIC receive”, see Fig. 23 [0188], 1st sentence}; and performing an additional function of the application program based on the application-specific completion descriptor {“utilize specific doorbell or completion queues or write-back descriptors” and perform additional functions “to be accessed by the NIC, or convert NEXT format descriptors to NIC specific format” (see Figs. 8b and 10, both cited from [0153]}.
As per claim 20, the rejection of claim 16 is incorporated and Kutch discloses wherein the programmable look-up table comprises a match-action table, the method further comprising: programming the match-action table based on {“[match-action tables] Mapping table can include a NEXT field information about corresponding NIC's descriptor field”, see Figs. 18 and 19 [0156]}, of the application program {“PHY circuitry 4114 can include encoding and decoding circuitry (not shown) to encode and decode data packets”, see Fig. 41 [0303], 1st sentence}.
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over by Savic in view of Kutch and further in view of Kashyap in view of Chandra and further in view of Biederman.
As per claim 17, the rejection of claim 16 is incorporated and Kashyap discloses wherein the function comprises controlling an IO device to perform a subsequent IO transaction {“content and share the stored content appropriately [to a particular IO device or storage]” (see Figs. 2 and 3, Col 8, lines 49-54)};
loading a receive queue of the application program {“ Receive queue 608”, see Figs. 6 and 8 [0066]};
loading a submission queue of the application program {“ Transmit queue 606”, see Figs. 6 and 8 [0066]};
processing a subsequent entry of the submission queue {processing via “include descriptors that reference data or [subsequent entry] packets in transmit queue 606”, see Figs. 6 and 8 [0066]};
generating an application-specific completion descriptor based the IO transaction {“[application specific] Descriptor queues 620 can include descriptors that reference data or packets in transmit queue 606 or receive queue 608”, see Figs. 6 and 8 [0066]; such descriptor queue including completion descriptor “To drain the list of completed slots, buffer management 308” (see Fig. 3, [0040], last sentence)};
Neither one of the group consisting of Savic, Kashyap, Kutch, and Chandra appears to explicitly disclose assigning a timestamp to the IO transaction and performing a transaction-level analysis based on the IO transaction and the timestamp.
Furthermore, Biederman discloses assigning a timestamp to the IO transaction {“[assigned timestamp] precise time is communicated by IEEE1588”, [0101]} and performing a transaction-level analysis {“may use [transaction-level] two-way latency measurements, that are divided by two to determine one-way latency”, see Figs. 5 and 6, [0065], 2nd sentence} based on the IO transaction and the timestamp {“information in the TPTs 116a, 116b”, see Fig. 5, [0065], 1st sentence}.
Savic/Kutch/Kashyap/Chandra and Biederman are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic/Kutch/Kashyap’s system incorporating Biederman’s “NIC accessible portion 608” (see Fig. 6, [0067])
The suggestion/motivation for doing so would have been to provide allow computing systems to utilize memory more efficiently than systems which do not use precise time. In addition and/or alternatively, by leveraging precise time, embodiments disclosed herein may provide better determinism than systems which do not use precise time along with leveraging precise time, embodiments disclosed herein may allow computing systems to utilize bandwidth more efficiently than systems which do not use precise time ( [0015]).
Therefore, it would have been obvious to combine Biederman with Savic/Kutch/Kashyap/Chandra to obtain the invention as specified in the instant claim(s).
As per claim 18, the rejection of claim 16 is incorporated and Kashyap discloses wherein the function comprises processing a subsequent entry of a submission queue {processing via “include descriptors that reference data or [subsequent entry] packets in transmit queue 606”, see Figs. 6 and 8 [0066]} of the application program, including:
formatting the subsequent entry {“packet may be used herein to refer to various formatted collections of bits that may be sent across a network”, see Fig. 3 [0041]} of the submission queue as a message {“Computation 304 can provide the summation into a [message] packet and send the packet upstream to an upstream switch”, see Fig. 3 [0044], last sentence};
transmitting the message to the IO device {“data slots in buffers 326 using counters or registers to determine when an aggregation is complete”, see Fig. 3 [0040], 1st sentence};
and writing a completion transaction {“To drain the list of completed slots, buffer management 308 can cause transmission of a packet with the data from a slot and generate (e.g., by packet replication) a second packet that is recirculated”, see Fig. 3 [0040], last sentence} to a completion queue of the application program {“[application specific] Descriptor queues 620 can include descriptors that reference data or packets in transmit queue 606 or receive queue 608”, see Figs. 6 and 8 [0066]; such descriptor queue including completion descriptor “To drain the list of completed slots, buffer management 308” (see Fig. 3, [0040], last sentence)}.
Neither one of the group consisting of Savic, Kashyap, Kutch, and Chandra appears to explicitly disclose assigning a timestamp to the IO transaction;
and performing a transaction-level analysis based on the IO transaction and the timestamp.
Furthermore, Biederman discloses assigning a timestamp to the IO transaction {“[assigned timestamp] precise time is communicated by IEEE1588”, [0101]} and performing a transaction-level analysis {“may use [transaction-level] two-way latency measurements, that are divided by two to determine one-way latency”, see Figs. 5 and 6, [0065], 2nd sentence} based on the IO transaction and the timestamp {“information in the TPTs 116a, 116b”, see Fig. 5, [0065], 1st sentence}.
Savic/Kutch/Kashyap/Chandra and Biederman are analogous art because they are from the same problem-solving area, method and systems for handling PCIe devices.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of before him or her, to modify Savic/Kutch/Kashyap/Chandra’s system incorporating Biederman’s “NIC accessible portion 608” (see Fig. 6, [0067])
The suggestion/motivation for doing so would have been to provide allow computing systems to utilize memory more efficiently than systems which do not use precise time. In addition and/or alternatively, by leveraging precise time, embodiments disclosed herein may provide better determinism than systems which do not use precise time along with leveraging precise time, embodiments disclosed herein may allow computing systems to utilize bandwidth more efficiently than systems which do not use precise time ( [0015]).
Therefore, it would have been obvious to combine Biederman with Savic/Kutch/Kashyap/Chandra to obtain the invention as specified in the instant claim(s).
Response to Arguments
Applicant’s arguments, filed on 04/07/2026, have been considered however rendered moot in view of the new ground of rejection(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references indicative of the current state of the art regarding claim 1’s “discrete logic”, “lookup table”, or “input/output devices”: US 12524360 B1, US 20250077453 A1, US 20240330216 A1, US 10983920 B2, US 10810135 B2, AND US 20200218676 A1.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.A.B./
Examiner
Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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