Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 1-20 are pending.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, 6-9, 11-13, 14-16, 18-20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Bobas et al. (US Pub No. 2017/0285717).
In regard to claim 1, 9, 16, Bobas et al. disclose an information handling system (i.e. computer); a non-transitory computer-readable medium or media comprising one or more sequences of instructions which, when executed by at least one processor, causes steps to be performed (see ¶ 29), a processor-implemented method comprising: responsive to a first processing element (PE) initialing a call to perform a parallel communication with one or more other PEs: monitoring at the first PE one or more indicators to determine whether one or more other PEs are ready to perform the parallel communication (as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Bobas discloses a plurality of processing cores 102-1, 102-2, 102-n (generically, core 102) are provided to process tasks in parallel. The core 102-1 would enter wait if the core 102-2 is not ready for synchronizing task processing. See ¶ 10-11);
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responsive to at least one of the one or more indicators indicating that at least one other participating PE is not ready: clocking down the speed of the first PE to a lower state (in Bobas, a first core is transitioned into a reduced power state responsive to a task executing on the core reaching a synchronization point, a threshold before a second task executing on a second core reaches the synchronization point. The first core is returned to a higher power state responsive to the second task reaching the synchronization point. See ¶ 10-11, 29, 36); waiting until a threshold condition has been met (in Bobas, the delay timer is triggered based on a call of a messaging wait routine from the first task. See ¶ 10-11, 31); and return to the monitoring step; and responsive to the one or more indicators indicating that the one or more other participating PEs are ready: clocking up the speed of the first PE to a default state; and completing the parallel communication (in Bobas, the first core is returned to a higher power state responsive to the second task reaching the synchronization point. See ¶ 10-11, 29).
In regard to claims 3, 11, Bobas et al. disclose wherein the parallel communication is related to a collective operation (in Bobas, the number of cores 102 can be arbitrarily large. Each core 120 includes a corresponding power management agent 114-1, 114-2-, 114-N (generically, power management agent 114). Power management agent 114 may be implemented as software, hardware, microcode etc. The power management agent 114 is used to place its core 120 in a lower power state when it reaches a synchronization point before other cores 120 processing other tasks 112. As used herein, “synchronization point” refers to any point in the processing where the further processing is dependent on receipt of data from another core in the system. See ¶ 9, figure 1).
In regard to claims 4, 12, 18, Bobas et al. disclose wherein the step of waiting until a threshold condition has been met comprises: waiting a set number of clock cycles (in Bobas, the power management agent 114 includes or has access to a timer 116-1, 116-2, 116-N, respectively (generically, timer 116) that delays entry into the low power state for a threshold period. The timer would be able to set or program numbers clock cycles as desired. See ¶ 10-11).
In regard to claims 5, 13, 19, Bobas et al. disclose wherein the step of clocking down a speed of the first PE to a lower state makes one or more resources available for a second PE to increase its speed to reduce its processing time for a task (in Bobas, the means for reducing power consumption includes means for reducing a clock frequency in the processing core. See ¶ 36-37).
In regard to claims 6, 15, 20, Bobas et al. disclose wherein the first PE and the second PE are on a same system and are working on a same task or on a different task (in Bobas, this allows task R to resume processing and begin processing of MSG 1 while receiving MSG 2, thereby improving performance. Even in a system where task R is merely residing in a spin loop, this message subdivision can improve power because the time spent in the spin loop (not performing any useful work) is reduced over systems in which task R waits in a spin loop for the receipt of the entire lengthy message (here, the composition of MSG 1 and MSG2). See ¶ 14, figure 2C-D).
In regard to claim 7, Bobas et al. disclose wherein the state is a c-state (in Bobas, the core transitions into a higher power/active state, that is, it goes to a higher power, possibly CO state, or exits a spin loop, for example. See ¶ 17).
In regard to claim 8, Bobas et al. disclose wherein the call is implemented through a software library that intercepts a standard function call and uses a custom implementation wrapping to implement the call (in Bobas, an inter-core messaging unit 104 provides messaging services between the different processing cores 120. In one embodiment, inter-core messaging unit 104 adheres to the message passing interface (MPI) protocol. See ¶ 10).
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
Claims 2, 10, 17, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an Examiner's statement of reasons for the indication of allowable subject matter: Claims 2, 10, 17, are allowable over the prior art of record because the prior arts, cited in its entirety, or in combination, do not teach
wherein the step of monitoring at the first PE one or more indicators to determine whether one or more other PEs are ready to perform the parallel communication comprise comprises the first PE checking whether a value at a memory address has changed (claims 2, 10, 17).
Conclusion
Claims 1, 3-5, 6-9, 11-13, 14-16, 18-20 are rejected. Claims 2, 10, 17, are objected.
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Lambert et al. (US No. 10,496,580) disclose a device is configured to provide an output signal via a first port, determine that the output signal is detected via a second port, determine if the first port and the second port are capable of being coupled, determine that the output signal is not detected via the second port, determine if the second port is coupled to a backplane, and disengage the serializer/deserializers associated with the second port if the second port is not coupled to the backplane.
Berghe (US Pub No. 2015/0378419) discloses a method involves monitoring wait times of nodes to determine that execution reaches an iteration phase, and determining an average wait time of the nodes. A power state for a subset of the nodes is changed. The wait times are continuously monitored, and the monitored wait times are compared with the wait times determined in a default power state to determine whether the iteration phase is input-output bound. The power state of the nodes is changed to reduce energy consumption, and the execution is continued if the iteration phase is the input-output bound.
Venkumahanti et al. (US Pub No. 2015/0301573) disclose the latency-based power mode unit (12) has a thread workload input (20) that receives workload information (22) relative to a status of threads in the processor core (14). A power mode setting (24) is generated to set the processor core to operate in a reduced power mode if the workload information indicates that the processor core has several threads in pending status and no threads in active status, and the power mode information (18) indicates a current data access latency of several threads in pending status corresponding to the reduced power mode.
O’Connor et al. (US Pub No. 2014/0089699) disclose the method involves monitoring the performance data associated with each execution of a repetitive workload by a processor (124), using the power control logic of the processor. The compute-bound and memory-bound of the processor is determined based on the monitored performance data associated with the execution of the repetitive workload. The operating frequency of the compute unit (118) and memory controller (130) are adjusted, based on determination of compute-bound and memory-bound of the processor by the power control logic (140).
Melpignano et al. (US Pub No. 2006/0259799) disclose a multi-processing system-on-chip including a cluster of processors having respective CPUs is operated by: defining a master CPU within the respective CPUs to coordinate operation of said multi-processing system, running on the CPU a cluster manager agent. The cluster manager agent is adapted to dynamically migrate software processes between the CPUs of said plurality and change power settings therein.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175