Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 12/18/2025 has been entered.
Claim Objections
Claims 5-7, 12-14 and 18-20 objected to because of the following informalities:
The above claims recite the acronyms KTE, LIF and PTE. Applicant is requested to define the acronyms within the claims.
Appropriate correction is required.
Claim 4 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 1. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: the distributed services platform in claim 15. Support in the specification, paragraph 68, states that the distributed services platform may represent an integrated circuit (IC).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, 8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Grubisic et al. (US 2015/0178220) in view of Yokoyama et al. (US 2020/0293454.
Regarding claim 1, Grubisic discloses an integrated circuit (IC), comprising: memory encoded with lookup tables; and a discrete logic translation circuit configured to convert virtual addresses to physical addresses based on contents of the lookup tables [see Fig. 1 & paragraphs 29-33 & 57-58; address translation circuitry includes a processing pipeline including a plurality of stages to translate a virtual address to a physical address utilizing lookup tables].
Grubisic does not expressly disclose converting virtual addresses to physical addresses based on operational codes within memory access requests.
Yokoyama discloses a memory system that translates virtual addresses to physical addresses. An access command includes a namespace ID (interpreted as opcode) and a logical (virtual) address, and the address is translated based on the address and namespace ID [see paragraph 22].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the namespace ID in the system of Grubisic.
The motivation for doing so would have been support storage devices utilizing namespaces, and to translate a logical address for its intended namespace [see paragraphs 18 & 22].
Therefore, it would have been obvious to combine Yokoyama with Grubisic for the benefits listed above, to obtain the invention as specified in claims 1 and 8.
Regarding claim 4, the combination discloses the IC of claim 1, wherein the discrete logic translation circuit is further configured to: convert the virtual addresses to the physical addresses based further on operational codes within the memory access requests [see Yokoyama, paragraph 22; instructions are individually translated based on a logical address and namespace ID provided with an access command].
Claims 8 and 11 recite similar claim limitations as claims 1 and 4 and are rejected using the same citations and interpretations as discussed above.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Grubisic in view of Yokoyama and further in view of Marcovitch et al. (US 2025/0028648).
Regarding claim 15, the combination of Grubisic and Yokoyama discloses a system, comprising:
a host device [see Grubisic, Fig. 1, GPU master];
a memory device [see Grubisic, Fig. 1; memory];
a distributed services platform comprising one or more integrated circuit (IC) devices, wherein the distributed services platform comprises,
a system-on-chip portion comprising a host interface configured to interface with the host device, a memory controller configured to interface with the memory device [see Grubisic, Fig. 1; translation circuitry interfaces hit GPU master (host) and memory], a processor, and an interconnect configured to interface with the host interface, the memory controller, the offload engine, the processor, and the networking portion;
wherein the networking portion comprises a processing pipeline comprising multiple processing stages that each comprises respective discrete logic translation circuits configured to convert virtual addresses to physical addresses based on table lookups based on operational codes within memory access requests [see Grubisic, Fig. 1 & paragraphs 29-33 & 57-58; address translation circuitry includes a processing pipeline including a plurality of stages to translate a virtual address to a physical address utilizing lookup tables & Yokoyama, paragraph 22; address translated based on provided logical address and namespace ID (operation code)].
The combination does not expressly disclose a networking portion, and an offload engine configured to perform a function of one or more the host device and the networking portion, a processor
Marcovitch discloses a RDMA network interface controller (NIC) comprising address translation services, a network interface, and a packet processor for sending and receiving packets over network for a connected host [see Fig. 1 & paragraph 26].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize network interface controller of Marcovitch in the system of Grubisic and Yokoyama.
The motivation for doing so would have been to provide improved techniques for address translation and memory access in computing systems [see Marcovitch, paragraph 18].
Therefore, it would have been obvious to combine Marcovitch with Grubisic and Yokoyama for the benefits listed above, to obtain the invention as specified in claim 15.
Allowable Subject Matter
Claims 3, 5-7, 10, 12-14, and 17-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record fails to teach or render obvious the claim limitations regarding the discrete logic translation circuit is further configured to: look-up up logical interface (LIF) keys based on LIF identifiers (LIF IDs) of memory access requests; look-up key table entries (KTEs) based on the LIF keys, translation keys of the memory access requests, and key table (KT) base addresses of the memory access requests; and look-up page table entries (PTE) based on the KTEs and virtual addresses of the memory access requests. The prior art of record fails to teach or render obvious the claim limitations regarding a match-action circuit to provide memory access requests to translation circuitry and one or more processors based on a matching input vector. The prior art of record fails to teach or render obvious the claim limitations regarding the encoding of LIF tables, key tables and page tables. The prior art of record fails to teach or render obvious the claim limitations regarding the translation circuitry processing memory access requests in accordance with the one or more claimed modes specified in the operational codes.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Auernhammer (US 2012/0303948) – Discloses the translation of virtual to physical memory addresses in a RDMA environment.
Kagan (US 2013/0067193) – Discloses a network interface controller with processing circuitry to use translation tables to translate virtual addresses to physical addresses.
Brandt (US 10,083,124) – Discloses a pipelines virtual address translation system wherein the pipeline comprises multiple stages.
Chandrashekhar (US 2015/0106804) – Discloses utilizing logical interfaces (LIFs) of incoming packets to support network address translations.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN BERTRAM whose telephone number is (571)270-1377. The examiner can normally be reached M-F 8:30-5MNT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RYAN BERTRAM/Primary Examiner, Art Unit 2137