DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4-7, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2013/0050949 (“MORRIS”) in view of CN 111511097 (“LIU”).
Regarding claim 1, MORRIS teaches an optical module (100) comprising: a module substrate (10) having a first surface that extends in a first direction and a second direction perpendicular to the first direction (FIGs. 1, 2); multiple optical ICs (18; par. [0018]) mounted on the first surface at different positions from each other in the first direction and configured to perform photoelectric conversion (par. [0018]); multiple fiber bundles (20) each including multiple optical fibers extending in parallel with each other, each of the fiber bundles extending out from a corresponding one of the multiple optical ICs toward a first side in the second direction (par. [0018]); multiple optical connectors located at opposite ends of the multiple fiber bundles from the multiple optical ICs, connected to external optical elements, and configured to allow transmission of optical signals (pars. [0022], [0023]); and at least one control IC (14) mounted on the module substrate and configured to control at least one of the multiple optical ICs (par. [0020]).
MORRIS does not teach at least one power supply IC (123) mounted on a module substrate (1) and configured to supply power to at least one optical IC (121; FIG. 13). LIU teaches at least one power supply IC mounted on the module substrate and configured to supply power to at least one of the multiple optical ICs. It would have been obvious to one of ordinary skill in the art at the effective filing date to modify the module of MORRIS with an at least one power supply IC, as taught by LIU. The motivation would have been to drive the optical ICs as desired.
Regarding claims 4 and 5, MORRIS teaches that the at least one control IC includes only one control IC, and the one control IC is configured to control the multiple optical ICs, and that the at least one power supply IC includes only one power supply IC, and the one power supply IC is configured to supply power to the multiple optical ICs (par. [0020]).
Regarding claim 6, LIU teaches that the at least one power supply IC includes two or more power supply ICs (123; FIG. 13), and the two or more power supply ICs are configured to supply powers of different voltages from each other and are configured to each supply power to the multiple optical ICs (par. [0056]).
Regarding claim 7, MORRIS teaches a cooling component (30) that is in direct or indirect contact with the multiple optical ICs and the module substrate and is configured to cool the multiple optical ICs and the module substrate (FIG. 1; pars. [0027]-[0032]).
Regarding claim 10, MORRIS teaches a motherboard electrically connected to the optical module (par. [0021]).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over MORRIS in view of LIU as applied to claim 1 above, and further in view of JP H08262277 (“MIKI”).
MORRIS in view of LIU renders obvious the limitations of the base claim 1. MORRIS does not teach that, among the multiple optical ICs, at least one optical IC is displaced in the second direction with respect to one or two optical ICs that are adjacent thereto in order of arrangement in the first direction. MIKI teaches an at least one optical IC that is displaced in a second direction with respect to one or two optical ICs that are adjacent thereto in order of arrangement in a first direction, wherein the at least one optical IC does not overlap the adjacent one or two optical ICs in terms of an arrangement range in the second direction, but does partially overlap the adjacent one or two optical ICs in terms of an arrangement range in the first direction (FIGs. 1, 2). It would have been obvious to one of ordinary skill in the art at the effective filing date to modify the module of MORRIS with the arrangement taught by MIKI. The motivation would have been to reduce the lateral distance between ICs.
Allowable Subject Matter
Claims 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, whether taken individually or in combination, when considered in light of the claimed subject matter as a whole as interpreted in light of the Specification as originally filed, fails to disclose or render obvious a regulating member configured to regulate a path of at least part of at least one fiber bundle among the multiple fiber bundles, wherein the multiple optical ICs include a first optical IC, and a second optical IC is located toward the first side relative to the first optical IC, the multiple fiber bundles include a first fiber bundle extending from the first optical IC, and a second fiber bundle extending from the second optical IC, when a length of each of the fiber bundles from the corresponding optical IC to the corresponding optical connector is called a total length, and a length by which each fiber bundle can extend out parallel to the second direction from an edge, on the first side, of the module substrate is called an extension length, the first fiber bundle and the second fiber bundle have identical total lengths, and the regulating member is configured to regulate a path of at least part of at least the second fiber bundle and make a difference between the extension length of the first fiber bundle and the extension length of the second fiber bundle smaller than a difference between positions of the first optical IC and the second optical IC in the first direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERRY M BLEVINS whose telephone number is (571)272-8581. The examiner can normally be reached Monday - Friday.
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/JERRY M BLEVINS/Primary Examiner, Art Unit 2874