MEMOMETER

DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is response to Application 18/681618 filed on 02/06/2024. Claims 1-20 are pending in the office action. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-7 and 12-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Madurawe et al., (U.S. Pub. 2009/0167349) in view of in view of O’Connel (U.S. Pat. 11,005,669). With respect to claims 1-2 and 12: Madurawe teaches an apparatus comprising a controller programmed to: establish a connection with an integrated circuit (‘349, par. [0007], programmable interconnect coupled to the latch and adapted to transmit the latch output to another logic element in the BLE (a basic logic element), par. [0009], local programmable interconnect use minimize global congestion related to logic placement in CAD); program a plurality of cross-coupled look up tables of the integrated circuit to generate a plurality of memory cells (‘349, the abstract, par. [0010], cross coupled logic element within programmable logic; the output of first LE (logic element) is coupled to the second LE and the output of second LE is coupled to first LE to form the cross-coupling. The first and second LE are configured to generate a latch function (i.e., memory cell), par. [0011], logic element and interconnects may be configured by a configuration circuit. Configuration circuits included RAM or ROM elements (i.e., memory cells)), each pair of cross-coupled look up tables comprising one memory cell (‘349, fig. 3 and par. [0027] [0031], logic element (example LUTs) cross coupled to form a LE latch (or LUT latch) (i.e., cross-coupled look up tables) (i.e., memory cell), two LUTs 311 and 322 are cross-coupled to form a latch and also see fig. 7 and fig. 10, CLB); and (claims 2 and 12) wherein the integrated circuit comprises a field programmable gate array (‘349, par. [0002], FPGA include programmable circuits, These programmable circuits are constructed with programmable LUT and registers (or Flip Flop), par. [0027], LUT latch). Madurawe does not teach associate a plurality of the memory cells with a digital fingerprint of the integrated circuit, a value of each memory cell after startup of the integrated circuit comprising one bit of the digital fingerprint. O’Connell teaches a physical unclonable function (PUF) generator includes: a PUF cell array that comprises a plurality of bit cells (i.e., memory cells) and an authentication circuit, coupled to the PUF cell array, wherein the authentication circuit is configured to access and determine second logical states of bit cells in at least one row of the PUF cell array by turning on the at least one enable transistor and turning off the at least two pre-charge transistors of each of the bit cell in the at least one row of the PUF cell array (the abstract). The PUF generator derives a key based its unique physical characteristics caused by inherent process variations to differentiate itself from others that are produced even from a same fabrication process. Generally, such key is referred to as a “PUF signature” (i.e., digital fingerprint). Using the manufacturing variability of each bit cell across a memory-based PUF generator to generate a PUF signature, intrinsic tendency of each bit cell caused by aforementioned variations in parameters through a fundamentally defective and non-uniform manufacturing process may be used to determine whether such a bit cell is suitable (i.e., strong tendency to generate a logical state either “1” or “0”) to provide a reliable PUF signature (‘669, col. 4, ll. 7-23). Each cross-coupled inverters 220/230 are intrinsically different due to the variations in manufacturing processes and small differences in the cross-coupled inverters 220/230 are amplified by the positive feedback of the cross-coupled inverters and eventually depending on the initial input difference on the SN/SNB 250/260 and the strength of the inverters, a logical “1” or “0” is generated for the bit cell 510. The PUF control circuit 114 uses the logical states of the bit cells 510 across the at least one bit cell block 520 to generate a PUF signature (‘669, col. 18, ll. 11-23). It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine O’Connell and Madurawe to modifying Madurawe ’s cross-coupling LUT to have O’Connell’s cross-coupled inverters to generate PUF signature to be unique, unclonable, and reliable during run-time (‘669, col. 1, ll. 38-47). As per claims 3 and 13: Madurawe and O’Connell teach wherein the controller is further programmed to: program each of the cross-coupled look up tables to function as a NAND gate (‘349, par. [00101]-[0011], the logic elements include NAND logic). As per claims 4 and 14: Madurawe and O’Connell teach wherein the controller is further programmed to: program each of the cross-coupled look up tables to function as a NOR gate (‘349, par. [0010]- [0011], the logic elements include NOR logic). As per claims 5 and 15: Madurawe and O’Connell teach wherein each memory cell has a random value upon startup of the integrated circuit (‘669, col. 19, ll. 18-23, a PUF signature, generated based on one or more intrinsic randomness of a plurality of bit cells in at least one bit cell block, is unique to the PUF cell array). As per claims 6 and 16: Madurawe and O’Connell wherein the cross-coupled look up tables of each memory cell have balanced feedback delay paths (‘669, col. 18, ll. 11-23, the cross-coupled inverters 220/230 are amplified by the positive feedback of the cross-coupled inverters and eventually depending on the initial input difference on the SN/SNB 250/260 and the strength of the inverters, a logical “1” or “0” is generated for the bit cell 510). As per claims 7 and 17: Madurawe and O’Connell teach wherein the controller is further programmed to: create a first memory cell by cross-coupling an output of a first look up table to a first input of a second look up table and an output of the second look up table to a first input of the first look up table (‘349, fig. 3, par. [0031]); and create a second memory cell by cross-coupling the output of the first look up table to a second input of the second look up table and the output of the second look up table to a second input of the first look up table (‘349, fig. 3, par. [0031]). Claim(s) 8, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Madurawe et al., (U.S. Pub. 2009/0167349) in view of in view of O’Connel (U.S. Pat. 11,005,669) and further in view of Kreft (U.S. Pub. 2016/0359636). As per claims 8, 11, and 18: Madurawe and O’Connell do not teach: (claims 8 and 18) wherein the controller is further programmed to: establish the connection with the integrated circuit through a JTAG port of the integrated circuit. (claim 11) wherein the controller is further programmed to: generate one or more error correction bits based on the digital fingerprint. Kreft teaches a new use of hardware providing a Physical Unclonable Function (PUF), and the use of a configuration fingerprint of a FPGA used within the tamper-resistant hardware and teach (claim 8) testing circuitry (including interfaces) like JTAG scan chain (‘636, the abstract, par. [0299] [0576]); and (claim 11) also teach the raw fingerprint will be transformed after its measuring into a long-term stable digital dataset by using e.g. error correcting measures to stabilize the fingerprint against small variations introduced by the analog nature of the memory (‘636, par. [0400] [0463]). It would have been obvious to one of ordinary skill in the art at the time of the effective filling date of claimed invention to combine Kreft and Madurawe and O’Connell to modify O’Connel’s PUF having Kreft’s JTAG port and error correction bits based on the digital fingerprint to improve tamper resistance and provided by the sensors and/or countermeasures may keep variations of the excitation in an acceptable range not critical to the uniqueness and stability of the generated fingerprint (‘636, par. [0299] and par. [0453]) Allowable Subject Matter Claims 9-10, and 19-20 are objected to as being dependent upon a rejected base claim but would be allowable if claim 9 or claim 19 is rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not teach the combination of limitations recited in claims 9 and/or 19, comprise: wherein the controller is further programmed to: measure output values of the plurality of memory cells after startup of the integrated circuit; and store the output values of the plurality of memory cells in association with the digital fingerprint. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGHIA M DOAN whose telephone number is (571)272-5973. The examiner can normally be reached Mon - Fri 7:00 AM - 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. NGHIA M. DOAN Primary Examiner Art Unit 2851 /NGHIA M DOAN/Primary Examiner, Art Unit 2851