DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 26 September 2024.
Claims 1-20 are pending and have been presented for examination.
Claims 21-25 have been cancelled.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 12 August 2021. It is noted, however, that applicant has not filed a certified copy of the 202110926716.4 application as required by 37 CFR 1.55.
Claim Objections
Claims 6, 15 and 18 are objected to because of the following informalities:
Claim 6 appears to contain a typo. The phrase “The method claim 1” should read “The method of claim 1”.
Claim 15 appears to contain a typo. The phrase “Receive hardware semaphore” should read “[[R]]receive a hardware semaphore”.
Claim 18 appears to contain a typo. The phrase “receiving a request” should read “receive a request”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the cluster" in line 6. There is insufficient antecedent basis for this limitation in the claim. The claim previously sets forth an SoC that comprises at least a plurality of clusters. The limitation of “the cluster” is indefinite as it is not clear which cluster, of the plurality of clusters, is being referred to.
Claims 2-11 are also rejected based on the dependency to claim 1.
Claims 2, 5, 6, 7, 8, 11 also contain the limitation “the cluster”. Claim 1 sets forth an SoC that comprises at least a plurality of clusters. The limitation of “the cluster” is indefinite as it is not clear which cluster, of the plurality of clusters, is being referred to.
Claim 12 recites the limitation "the cluster" in lines 5 and 6. There is insufficient antecedent basis for this limitation in the claim. The claim previously sets forth an SoC that comprises at least a plurality of clusters. The limitation of “the cluster” is indefinite as it is not clear which cluster, of the plurality of clusters, is being referred to.
Claims 13-20 are also rejected based on the dependency to claim 12.
Claims 16, 18, 19 and 20 also contain the limitation “the cluster”. Claim 12 sets forth an SoC that comprises at least a plurality of clusters. The limitation of “the cluster” is indefinite as it is not clear which cluster, of the plurality of clusters, is being referred to.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over WANG (U.S. Patent Application Publication #2017/0242797) in view of SANGHI (U.S. Patent Application Publication #2020/0065244).
Examiner note: the limitation of “using the cluster memory to perform operations of the cluster” is rather broad. A reference that uses the cluster memory to store data during normal operation would anticipate this limitation. WANG uses the shared cache memory to store data during operation and therefore this would be considered a cluster memory being used to perform operations of the cluster. Another interpretation would involve using the cluster memory for communication among clusters. SANGHI is introduced to provide an alternative rejection that relies on this interpretation.
1. WANG discloses A method used for an SoC (System on Chip) (see [0023]: system on a chip – 100), wherein the SoC comprises at least a plurality of clusters for performing operations (see [0023]-[0024]: processing cores are grouped into core clusters, each processor contains multiple core clusters) and a cache interconnected with the plurality of clusters (see [0023]-[0024]: L2 cache shared among cores in a cluster, L3 cache shared between the processors), wherein each cluster comprises a plurality of processor cores for performing the operations (see [0023]: each core cluster contains multiple cores), wherein the method comprises: using partial storage space of the cache as a cluster memory (see [0030]-[0031]: copies of data needed by the cores can be stored in the cache, the lines being used by the cores for an operation would be using partial space of the cache); and using the cluster memory to perform operations of the cluster (see [0031]: reading from the memory would occur during operations performed by the cores of the cluster, in the alternative see also SANGHI below regarding use of the cluster memory).
SANGHI discloses the following limitations that are not disclosed by WANG: using the cluster memory to perform operations of the cluster (see [0063]-[0064]: creating a buffer in memory used to temporarily store data; [0069]: data pipe that allows for inter-processor communication; [0074]: shared memory that allows for inter-processor communication). WANG already discloses shared cache memories that allow access by each core from the core clusters (see WANG [0024], [0030]: L2 and L3 cache). WANG also discloses the ability to communicate between processors (see [0028]: inter-processor connections). SANGHI discloses an implementation of inter-processor communication that allocates a portion of shared memory to facilitate communication between processors. This can improve the speed of operation between independently operable processors (see [0097]). SANGHI discloses the communication can utilize a memory for temporarily storing data. The cache in WANG is a memory that temporarily stores data. Therefore, a combination of WANG and SANGHI would result in using the shared cache memories already disclosed by WANG, to perform operations that include communication between the processors, as shown by SANGHI.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify WANG to use the cluster memory to perform operations, as disclosed by SANGHI. One of ordinary skill in the art would have been motivated to make such a modification to improve the speed of operation between independently operable processors, as taught by SANGHI. WANG and SANGHI are analogous/in the same field of endeavor as both references are directed to multi-processor systems.
2. The method of claim 1, wherein using the cluster memory to perform the operations of the cluster includes using the cluster memory for communication among clusters (see SANGHI [0069]: inter-processor communication; WANG [0028]: inter-processor communication, since each processor contains clusters of cores, communication between processors would necessarily involve communication between clusters).
3. The method of claim 2, wherein using the cluster memory for communication among clusters includes: using the cluster memory to implement peer-to-peer communication among clusters (see WANG [0028]: inter-processor communication would be considered peer-to-peer); or using the cluster memory to implement broadcast communication from one of a plurality of clusters to remaining clusters (see WANG [0038]: sending invalidation requests would be a broadcast type communication).
4. The method of claim 3, where using the cluster memory to implement peer-to- peer communication among clusters includes: receiving a write operation from a first cluster for written data (see SANGHI [0069]: data written by one processor); and sending the written data to a second cluster in response to a read operation from the second cluster (see SANGHI [0069]: the written data can be read by another processor).
5. The method of claim 1, wherein using the cluster memory to perform the operations of the cluster includes using the cluster memory to temporarily store data of the cluster (see WANG [0030]-[0031]: the different cache memory levels store data from main memory, the data is stored temporarily, until it is replaced).
6. The method claim 1, wherein using the cluster memory to perform the operations of the cluster includes using the cluster memory for sharing data among a plurality of clusters, allowing data of one cluster temporarily stored in the cluster memory to be shared with other clusters (see WANG [0034]-[0036]: data in a cache can be shared among cores in a cluster, among clusters in a processor, or among processors).
7. The method of claim 1, before using the cluster memory to perform the operations of the cluster, further comprising: receiving a request to use the cluster memory to perform the operations of the cluster (see WANG [0030]-[0031]: reads or writes during operation of the system would be considered a request to use the memory; SANGHI [0069]: creation of a data pipe to use memory for inter-processor communication); and performing a write-back operation (see WANG [0037]: a cache line in the modified state is written-back to main memory) and an invalidation operation (see WANG [0052]: invalidation request) on, in response to the request, cache lines of the partial storage space to an off-chip memory to use the partial storage space to perform the operations of the cluster (see WANG [0037]: write-back to main memory).
8. The method of claim 7, wherein before receiving the request and/or after completing the operations of the cluster, the method comprises using the partial storage space for a caching operation of the cache (see WANG [0030]-[0031]: data is stored in the cache to allow faster access than having to retrieve the data from main memory, this is a caching operation).
9. The method of claim 1, further comprising: receiving an allocation instruction to use the partial storage space as the cluster memory (see SANGHI [00801]: opening a data pipe); and allocating the partial storage space to be used as the cluster memory based on the allocation instruction (see SANGHI [0084]: allocation of a buffer to write data from the data pipe), where the allocation instruction includes an opcode and at least one operand, wherein the opcode is used to identify an allocation operation, and the at least one operand includes a starting address and/or a size of the partial storage space (see SANGHI [0081]: opening a data pipe includes parameters such as type, address, number of entries {size}, identification, etc.).
10. The method of claim 1, further comprising: receiving a release instruction to release the partial storage space (see SANGHI [0095]-[0096]: completion descriptor); and releasing the partial storage space based on the release instruction (see SANGHI [0095]-[0096]: buffer space is freed when the completion descriptor is processed), wherein the release instruction includes an opcode and at least one operand, wherein the opcode is used to identify a release operation, and the at least one operand includes a starting address and/or a size of the partial storage space to be released (see SANGHI [0096]: unique tag that identifies the allocated buffer).
11. The method of claim 10, wherein the operations of the cluster include executing a single job collaboratively by some or all of the clusters in a plurality of clusters (see WANG [0068]: multi-threading allows for dividing the workload of a single job among multiple cores and/or processors), and the method comprises: using the cluster memory, during the execution of the single job, to perform communication among some or all of the clusters (see SANGHI [0019]: shared memory space to pass messages between applications during execution of the system); and releasing the partial storage space based on the release instruction after the single job is executed (see SANGHI [0095]-[0096]: buffer space is freed when the completion descriptor is processed).
12. WANG discloses An SoC (see [0023]: system on a chip – 100), comprising: a plurality of clusters (see [0023]-[0024]: processing cores are grouped into core clusters, each processor contains multiple core clusters), wherein each cluster includes a plurality of processor cores for performing operations (see [0023]: each core cluster contains multiple cores); and a cache interconnected with the plurality of processor cores (see [0023]-[0024]: L2 cache shared among cores in a cluster, L3 cache shared between the processors) and configured to use partial storage space as a cluster memory based on an allocation from the cluster (see [0030]-[0031]: copies of data needed by the cores can be stored in the cache, the lines being used by the cores for an operation would be using partial space of the cache), and use the cluster memory to perform operations of the cluster (see [0031]: reading from the memory would occur during operations performed by the cores of the cluster, in the alternative see also SANGHI below regarding use of the cluster memory).
SANGHI discloses the following limitations that are not disclosed by WANG: using the cluster memory to perform operations of the cluster (see [0063]-[0064]: creating a buffer in memory used to temporarily store data; [0069]: data pipe that allows for inter-processor communication; [0074]: shared memory that allows for inter-processor communication). WANG already discloses shared cache memories that allow access by each core from the core clusters (see WANG [0024], [0030]: L2 and L3 cache). WANG also discloses the ability to communicate between processors (see [0028]: inter-processor connections). SANGHI discloses an implementation of inter-processor communication that allocates a portion of shared memory to facilitate communication between processors. This can improve the speed of operation between independently operable processors (see [0097]). SANGHI discloses the communication can utilize a memory for temporarily storing data. The cache in WANG is a memory that temporarily stores data. Therefore, a combination of WANG and SANGHI would result in using the shared cache memories already disclosed by WANG, to perform operations that include communication between the processors, as shown by SANGHI.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify WANG to use the cluster memory to perform operations, as disclosed by SANGHI. One of ordinary skill in the art would have been motivated to make such a modification to improve the speed of operation between independently operable processors, as taught by SANGHI. WANG and SANGHI are analogous/in the same field of endeavor as both references are directed to multi-processor systems.
13. The SoC of claim 12, wherein the cluster memory is used for broadcast communication among clusters (see WANG [0038]: sending invalidation requests would be a broadcast type communication) or peer-to-peer communication among clusters (see WANG [0028]: inter-processor communication would be considered peer-to-peer; SANGHI [0081]: data flows between processors using the shared memory to communicate).
14. The SoC of claim 13, wherein during the peer-to-peer communication, the cluster memory is configured to receive a write operation from a first cluster for written data (see SANGHI [0069]: data written by one processor); and send the written data to a second cluster in response to a read operation from the second cluster (see SANGHI [0069]: the written data can be read by another processor).
15. The SoC of claim 14, wherein the second cluster is configured to Receive hardware semaphore from the first cluster; and perform the read operation on the cluster memory in response to the received hardware semaphore (see SANGHI [0083]-[0084]: second processor accesses the written data using a read pointer).
16. The SoC of claim 12, wherein the cluster memory is configured to temporarily store data of the cluster (see WANG [0030]-[0031]: the different cache memory levels store data from main memory, the data is stored temporarily, until it is replaced).
17. The SoC of claim 12, wherein the cluster memory is configured to share data among a plurality of clusters, allowing data of one cluster temporarily stored in the cluster memory to be shared with other clusters (see WANG [0034]-[0036]: data in a cache can be shared among cores in a cluster, among clusters in a processor, or among processors).
18. The SoC of claim 12, wherein the cache is configured to receiving a request to use the cluster memory to perform the operations of the cluster (see WANG [0030]-[0031]: reads or writes during operation of the system would be considered a request to use the memory; SANGHI [0069]: creation of a data pipe to use memory for inter-processor communication); and perform a write-back operation (see WANG [0037]: a cache line in the modified state is written-back to main memory) and an invalidation operation (see WANG [0052]: invalidation request) on, in response to the request, cache lines of the partial storage space to an off-chip memory to use the partial storage space to perform the operations of the cluster (see WANG [0037]: write-back to main memory).
19. The SoC of claim 18, wherein before receiving the request and/or after completing the operations of the cluster, the cache is configured to use the partial storage space for a caching operation of the cache (see WANG [0030]-[0031]: data is stored in the cache to allow faster access than having to retrieve the data from main memory, this is a caching operation).
20. The SoC of claim 12, wherein the cluster memory is further configured to receive an allocation instruction from the cluster to use the partial storage space as the cluster memory (see SANGHI [00801]: opening a data pipe); allocate the partial storage space to be used as the cluster memory based on the allocation instruction (see SANGHI [0084]: allocation of a buffer to write data from the data pipe), where the allocation instruction includes a starting address, a size, and/or an identification for identifying an allocation operation of the partial storage space (see SANGHI [0081]: opening a data pipe includes parameters such as type, address, number of entries {size}, identification, etc.); receive a release instruction from the cluster to release the partial storage space (see SANGHI [0095]-[0096]: completion descriptor); and release the partial storage space based on the release instruction (see SANGHI [0095]-[0096]: buffer space is freed when the completion descriptor is processed), wherein the release instruction includes a starting address, a size, and/or an identification for identifying a release operation of the partial storage space to be released (see SANGHI [0096]: unique tag that identifies the allocated buffer).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CHIKKALA – 2024/0147217 – discloses processor cores, grouping of cores, private cache for each core, shared cache for core groups and shared cache for all cores to access. See [0050]
ARCHER – 2015/0081985 – discloses inter-core communication using a shared memory. See abstract
KOUGIOURIS – 5,881,286 – discloses deallocating a buffer used for message passing. See abstract
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/EDWARD J DUDEK JR/ Primary Examiner, Art Unit 2136