DETAILED ACTION
Claims 11 – 20 are pending in the present application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-12 and 17-19 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Jansen (US 20090167414).
Regarding claim 11, Jansen teaches a method (abstract; [0009]) for ascertaining a junction temperature (abstract) of a semiconductor component (semiconductor component 3) including an insulated gate (abstract; [0024] teaching an IGBT specifically – IGBT is an insulated gate transistor; see also figs. 2 and 3), the method comprising the following steps:
recharging an input capacitance (C.sub.int; 7; see fig. 3) of the semiconductor component using a current-controlled gate driver at a predefined first time ([0049] teaches that the gate capacitance (7) is charged, discharged, recharged; this is via a pulse through the “pulse generator 14 connected to a driver output stage 11 of a driver circuit 10 which drives the control terminal 6” [0019]; “gate capacitor 7” / “intrinsic gate capacitance 7” [0040-41]; see fig. 3 and [0044] “The intrinsic gate capacitor C.sub.int is the differential capacitance between the gate and the emitter of an IGBT (or between the gate and the source of an MOSFET)”; see also [0026]; [0033]; and [0035] all teaching regarding this charging/recharging of the gate capacitor via actuation at times defined by pulsed 25 and 26); and
ascertaining a junction temperature of the semiconductor component (abstract; [0040] “the junction temperature of the semiconductor component 9 can also be monitored with the help of the temperature detection circuit 1”) based on information about a voltage-dependent behavior of the input capacitance of the semiconductor component and based on a level of an internal gate resistor of the semiconductor component (R.sub.Gint; see fig. 3) at a second time which follows the first time ([0030-33] teaches that the times are defined by exemplary pulses 25 and then 26 where the current across R.sub.Gint is measured as voltage U.sub.B), the second time being a time at which a current build-up phase of a gate current generated by the gate driver for recharging the input capacitance has ended and at which a substantially constant gate current is present ([0030] teaches that the measurement is while “the gate voltage is maintained above the Miller Plateau” which is when a substantially constant gate current is maintained).
Regarding claim 12, Jansen teaches that the second time is a predefined time (26), and the level of the internal gate resistor of the semiconductor component is ascertained based on an external gate voltage present at the second time and a gate current present at the second time (pulse 26 is predefined such that “The driver output stage 11 and the pulse generator 14 are employed for generating a measuring signal during brief measuring pulses 25, 26.” [0019]; [0024] “the measurement current to the internal gate resistor 5, the driver output stage 11 is sequenced off for a short period of time defined by the pulses 25, 26 of pulse generator 14 during the on-state of the semiconductor switch (e.g., IGBT, MOSFET, etc.)”; U.sub.B is evaluated during pulses 25 and 26 – see [0024-26]; see also [0033] “the IGBT slightly discharges through the resistors of the bridge circuit for the short time period of a pulse 25, 26. The high discharge current, which flows through the bridge circuit 4, generates a voltage signal U.sub.B”).
Regarding claim 17, Jansen teaches that ascertaining the junction temperature is carried out: (i) during a switching-on process and/or a switching-off process of the semiconductor component, and/or (ii) in a switched-on and/or a switched-off state of the semiconductor component ([0024]; [0025-26]; [0033]), wherein a predefined pulse-shaped alternating signal, is generated by the gate driver at the gate of the semiconductor component (via 14; [0034-35]; see fig. 3).
Regarding claim 18, Jansen teaches that when ascertaining the junction temperature, an influence of an amount of charge that is recharged during the current build-up phase with respect to the input capacitance of the semiconductor component is taken into account as well ([0033]; [0042-45] teaches regarding the calculation using the input capacitance and reference capacitance both being used in the evaluation).
Regarding claim 19, Jansen teaches a circuit arrangement (fig. 3) for ascertaining a junction temperature of a semiconductor component (abstract; see figs. 2 and 3), comprising:
a semiconductor component (3) including an insulated gate (see [0024] teaching an IGBT specifically – IGBT is an insulated gate transistor; see also figs. 2 and 3);
a current-controlled gate driver ([0019] “driver circuit 10 which drives the control terminal 6” with at least components gate circuit 15 and driver output-stage 11 – see [0024]; see figs. 2 and 3);
a voltage measuring unit (bridge circuit 4 measuring voltage U.sub.B; [0019-20]); and
an evaluation unit (evaluation circuit 8; see fig. 2 and 3; see [0025] “For the temperature detection the resulting voltage U.sub.B is evaluated at the bridge diagonal”; see also [0033] “The bridge diagonal signal U.sub.B is supplied to an evaluation circuit 8”);
wherein
the current-controlled gate driver is configured to recharge an input capacitance of the semiconductor component at a first predefined time via an actuation of the gate of the semiconductor component ([0049] teaches that the gate capacitance (7) is charged, discharged, recharged; this is via a pulse through the “pulse generator 14 connected to a driver output stage 11 of a driver circuit 10 which drives the control terminal 6” [0019]; “gate capacitor 7” / “intrinsic gate capacitance 7” [0040-41]; see fig. 3 and [0044] “The intrinsic gate capacitor C.sub.int is the differential capacitance between the gate and the emitter of an IGBT (or between the gate and the source of an MOSFET)”; see also [0026]; [0033]; and [0035] all teaching regarding this charging/recharging of the gate capacitor via actuation),
the voltage measuring unit is configured to acquire an external gate voltage of the semiconductor component (U.sub.B; [0025]; [0042-45]), and
the evaluation unit is configured to ascertain a junction temperature of the semiconductor component (abstract; [0040] “the junction temperature of the semiconductor component 9 can also be monitored with the help of the temperature detection circuit 1”) based on information about a voltage-dependent behavior of the input capacitance of the semiconductor component and based on a level of an internal gate resistor (R.sub.Gint; see fig. 3) of the semiconductor component at a second time which follows the first time ([0030-33] teaches that the times are defined by exemplary pulses 25 and then 26 where the current across R.sub.Gint is measured as voltage U.sub.B), the second time being a time at which a current build-up phase of a gate current generated by the gate driver for recharging the input capacitance has ended and at which a substantially constant gate current present ([0030] teaches that the measurement is while “the gate voltage is maintained above the Miller Plateau” which is when a substantially constant gate current is maintained).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jansen (US 20090167414) in view of Schuler (DE 102011083679 – of record in IDS of 02/07/2024).
Regarding claim 13, Jansen lacks teaching that the second time is reached when the external gate voltage reaches a predefined threshold value, and the level of the internal gate resistor is ascertained based on a time difference between the second time and the first time.
However, Schuler teaches that the second time is reached when the external gate voltage reaches a predefined threshold value (U2; see abstract), and the level of the internal gate resistor is ascertained based on a time difference between the second time and the first time (dt; see at least abstract).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the method for ascertaining a junction temperature of Jansen with the specific knowledge of using the voltage threshold-based time difference for determining the temperature of a semiconductor switch of Schuler. This is because such a determining allows for the temperature of a semiconductor switch to be determined in a highly dynamic manner (Schuler at abstract). This is important in order to provide a responsive temperature measurement for an end user.
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jansen (US 20090167414) in view of Strzalkowski (US 20200132557).
Regarding claim 14, Jansen lacks teaching regarding a calibration procedure comprising: ascertaining deviations of temperature-related parameters of the semiconductor component from respective target values, including based on an additional temperature measurement by a temperature sensor, ascertaining compensation values for compensating for the deviations of the temperature-related parameters from respective target values.
However, Strzalkowski teaches regarding techniques for determining a temperature measurement of a junction of a power switch (abstract) with calibration ([0017-19]) using a temperature sensor (114; see fig. 1) for the calibration ([0019]; [0024]) and historical comparisons ([0032-33]).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the method for ascertaining a junction temperature of Jansen with the specific knowledge of using the calibration for a technique for measuring a junction temperature of Strzalkowski. This is because such calibration with a temperature sensor allows for “any scattering of the internal gate resistance R.sub.GINT during power switch assembly can be erased” ([0024] of Strzalkowski). This is important in order to improve measurement accuracy.
Regarding claim 15, Jansen lacks teaching regarding storing results of a plurality of temporally successive calibration procedures, and ascertaining a degradation state of the semiconductor element based on deviations between respective stored results of the calibration procedures.
However, Strzalkowski teaches regarding techniques for determining a temperature measurement of a junction of a power switch (abstract) with calibration ([0017-19]) using a temperature sensor (114; see fig. 1) for the calibration ([0019]; [0024]) and historical / temporal comparisons ([0032-33]).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the method for ascertaining a junction temperature of Jansen with the specific knowledge of using the calibration for a technique for measuring a junction temperature of Strzalkowski. This is because such calibration with a temperature sensor allows for “any scattering of the internal gate resistance R.sub.GINT during power switch assembly can be erased” ([0024] of Strzalkowski). This is important in order to improve measurement accuracy.
Regarding claim 16, Jansen lacks teaching that the calibration procedure: (i) provides ascertaining a temperature coefficient for the semiconductor component based on at least two measurements which differ from one another in term of time, and/or (ii) provides ascertaining a temperature dependence of the gate driver; and wherein the temperature coefficient and/or information about the temperature dependence of the gate driver are taken into account when ascertaining the junction temperature.
However, Strzalkowski teaches regarding techniques for determining a temperature measurement of a junction of a power switch (abstract) with calibration ([0017-19]) using a temperature sensor (114; see fig. 1) for the calibration ([0019]; [0024]) and historical / time differing comparisons ([0032-33]).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the method for ascertaining a junction temperature of Jansen with the specific knowledge of using the calibration for a technique for measuring a junction temperature of Strzalkowski. This is because such calibration with a temperature sensor allows for “any scattering of the internal gate resistance R.sub.GINT during power switch assembly can be erased” ([0024] of Strzalkowski). This is important in order to improve measurement accuracy.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jansen (US 20090167414) in view of Fursin et al. (US 20170213908; hereinafter Fursin).
Regarding claim 20, Jansen lacks teaching that the internal gate resistor of the semiconductor component includes a bidirectionally conductive, non-linear component, configured of two diodes connected in antiparallel.
However, Fursin does disclose an IGBT device (abstract) for semiconductor-based power switching (abstract) and the knowledge that “As one skilled in the art would appreciate, the built-in body diode of a MOSFET can eliminate the need for an external anti-parallel diode in practical power conversion circuits. The optional external anti-parallel diode may nevertheless be implemented based on specific circuit requirements.” (emphasis added; [0083]).
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the circuit arrangement of Jansen with the knowledge of anti-parallel diode structures in semiconductor-based power switching of Fursin. This is because one of ordinary skill in the art would have known to use anti-parallel diode structures in a design indicated manner because such structures are known to be a design choice to eliminate or reduce diode recovery related switching losses (see [0080] of Fursin).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHILIP COTEY whose telephone number is (571)270-1029. The examiner can normally be reached M-F 9-5.
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/PHILIP L COTEY/ Examiner, Art Unit 2855
/LAURA MARTIN/ SPE, Art Unit 2855