DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,2,3,4,7,13 and 14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Daisuke (WO 2020170392 cited by applicants.)
Re claims 1 and 7:The reference to Daisuke shows
a quantum circuit (see figure 11, UL1) is shown with a plurality of superconducting lines (L1a, L1b) that form quantum bits in accordance with an electromagnetic state thereof, and that interact with each other via a coupler(C2); a plurality of first lines (including W1 as shown in figure and noted below)that are electromagnetically coupled, respectively, to the plurality of superconducting lines(L1a,b), each of the first line(W1…) being configured to be capable of receiving an input signal individually, i.e., separate. These circuits form part of an array(quantum computing element)
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See ¶(0061-62)
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A plurality of second lines that are electromagnetically coupled, respectively, to the plurality of superconducting lines;
As shown in figure 6, multiple lattice quantum circuit arrays with the same config as above allow for the plurality of second EM coupled lines, similar to W1, etc., provide the EM coupled signals.
As noted below: see ¶(0042-0043)
The plurality of readout circuits (see figure below)that are electromagnetically coupled, respectively, to the plurality of superconducting lines, each of the readout circuit being configured to be capable of outputting a readout signal based on the state of the quantum bits of the corresponding superconducting line.
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The method steps of claim 7 are inherent.
Re claim 2: A quantum computing element(lattice array) comprising the quantum circuit (UL1) are described in the reference.
Re claim 3: The quantum computing element according to claim 2, further comprising a different quantum circuit to the quantum circuit, that is, the array has different circuits UL1,2,3,4(see figure 6)
Re claim 4: The quantum computing system shows W1 signal lines that are inherently connected to a control device(not shown) to supply the input signal(magnetic field) to the quantum computing element and acquire the readout signal(via readout SQUIDs) from the quantum computing element.
Re claim 13:
The input signal via W1 is applied to the quantum circuit L1a,b and the readout is provided for by a READout SQUID associated with the L1a,b superconducting cell lines forming quantum bits.
Re claim 14:
bias signals(adjustment signal) are applied to each of a plurality of second lines (W2,3) and are electromagnetically coupled to the superconducting lines L1a,b.
Allowable Subject Matter
Claim 5, 6 and 8-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2836
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