Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This communication is in response to Application No. 18/683,592 filed on February 14, 2024 and amendment presented on February 06, 2026 which amends claims 1, 6, 12, 14-17 and 20 and presents arguments, is hereby acknowledged. Claims 1-20 are pending and subject to examination.
Examiner Interview
The Examiner conducted interview with Applicant’s representative on January 16, 2026. Applicant's assigned Attorney argued that prior art reference Wang et al. (US 2017/0024346 A1) and Chen et al. (US 2017/0272059 A1) fails to teach proposed amendment "wherein the second bypass signal indicates to turn the packet in a third computing node of the array of computing nodes to route the packet along a second direction orthogonal to the first direction".
The examiner agreed that prior art reference Wang et al. (US 2017/0024346 A1) and Chen et al. (US 2017/0272059 A1) fails to teach proposed amendment "wherein the second bypass signal indicates to turn the packet in a third computing node of the array of computing nodes to route the packet along a second direction orthogonal to the first direction;".
However, the examiner explained that the cited prior art of record reference Lovell et al. (US 2008/0082786 A1) still teaches the above proposed amendment "wherein the second bypass signal indicates to turn the packet in a third computing node of the array of computing nodes to route the packet along a second direction orthogonal to the first direction;" (lovell: [fig 1, paragraph 0143, 0214, 0223]). However, no agreement was reached in regards to Lovell teaches the above argued proposed amended claimed subject matter.
5. Drawing Objections
Applicant’s drawing amendment and arguments, filed in the response dated February 06, 2026 regarding the objection of drawings have been fully considered and are persuasive. All outstanding objections of drawings are hereby withdrawn.
6. Claim Rejections Under 35 U.S.C. § 103
On pages 8-11 of the response filed February 06, 2026, Applicant addresses the 35 U.S.C. §103 rejection made on the December 31, 2025 Non-Final Rejection. Applicant's arguments, regarding the rejections under 35 U.S.C. §103, have been fully considered.
Applicant argues at pages 9-10 of the remarks, as filed that cited references, individually or collectively are not disclosed "wherein the second bypass signal indicates to turn the packet in a third computing node of the array of computing nodes to route the packet along a second direction orthogonal to the first direction" as recited by amended claim 1 have been fully considered and they are persuasive. Therefore, previously-made rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as discussed below.
Applicant argues claim 12 based on the arguments presented for Claim 1 at page 10 of the remarks. The same explanation is applicable to claim 12 as mentioned above with respect to claim 1.
Dependent claims 2-11 and 13-20
Applicant argues these claims conditionally based upon arguments presented for their parent claim(s). Applicant’s arguments are persuasive. However, a new ground of rejections may appear below. See the detailed explanation and rejection below.
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 10-14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2017/0024346 A1); in view of Anders et al. (US 2015/0071282 A1); and further in view of Chen et al. (US 2017/0272059 A1).
Regarding claim 1, Wang teaches a method of routing a packet in a computing system ([paragraph 0016-0017] describes routing a packet data in a network switch (e.g. a computing system), the method comprising:
outputting a first bypass signal and a second bypass signal from a first computing node of an array of computing nodes ([paragraph 0018-0022] describes forward control signals (e.g. a first bypass signal and a second bypass signal) from a switching node (e.g. computing node) of group of switching nodes (e.g. array of computing nodes)),
wherein the first bypass signal indicates to route a packet through a second computing node of the array of computing nodes ([paragraph 0022-0024] describe the forward control signal (e.g. the first bypass signal) from a switching node (e.g. computing node) to route packet data through next switching node (e.g. second computing node)), and
wherein the packet is routed from the first computing node through the second computing node in a single clock cycle ([paragraph 0018-0022] describes the packet data is routed from the switching node (e.g. first computing node) through the next switching node (e.g. second computing node) in each clock cycle (e.g. a single clock cycle)),
Wang fails to teach wherein the second bypass signal indicates to turn the packet in a third computing node of the array of computing nodes to route the packet along a second direction orthogonal to the first direction; routing the packet along the first direction through the second computing node based on the first bypass signal from the first computing node; routing the packet through the second computing node based on the first bypass signal from the first computing node, and wherein the second computing node receives the first bypass signal by way of a faster route than the second computing node receives the packet; and turning the packet in the third computing node based on the second bypass signal to route the packet along the second direction, wherein the packet is received by the third computing node from the second computing node.
However, Anders teaches wherein the second bypass signal indicates to turn the packet in a third computing node of the array of computing nodes to route the packet along a second direction orthogonal to the first direction ([paragraph 0026-0027, 0042-0046, 0075] describes another packet forward control signal (e.g. second bypass signal) indicates to send packet in third router node (e.g. a third computing node0 of the nodes of routers to route the packet along a different direction than first direction perpendicular (e.g. orthogonal) to the first direction);
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang to include wherein the second signal indicates to turn the packet in a third computing node of the array of computing nodes to route the packet along a second direction orthogonal to the first direction as taught by Anders. One ordinary skill in the art would be motivated to utilize the teachings of Wang in the Anders system in order to provide communication between the routers and their associated cores ([paragraph 0028] in Anders).
Wang and Chen fails to teach routing the packet along the first direction through the second computing node based on the first bypass signal from the first computing node; routing the packet through the second computing node based on the first bypass signal from the first computing node, and wherein the second computing node receives the first bypass signal by way of a faster route than the second computing node receives the packet; and turning the packet in the third computing node based on the second bypass signal to route the packet along the second direction, wherein the packet is received by the third computing node from the second computing node.
However, Chen teaches routing the packet along the first direction through the second computing node based on the first bypass signal from the first computing node ([paragraph 0023-0024] describes the bypass unit 130 has an input terminal and an output terminal. The input terminal of the bypass unit 130 is coupled to the output terminal of the input unit 120 through the node N, and the output terminal of the bypass unit 130 is coupled to the output terminal OUT of the active circuit 100. The bypass unit 130 can turn on or off a signal bypassing path according to a second control signal SIG.sub.ctr12 (e.g. second bypass signal). The signal bypassing path can be formed by the signal path from the node N through the bypass unit 130 to the output terminal OUT of the active circuit 100. The bypass unit 130 includes a second switch SW2. The second switch SW2 has a first terminal, a second terminal, and a control terminal. The control terminal of the second switch SW2 can receive the second control signal SIG.sub.ctr12. In some embodiments of the present invention, the first switch SW1 and the second switch SW2 can both be metal-oxide-semiconductor field-effect transistors),
and wherein the second computing node receives the first bypass signal by way of a faster route than the second computing node receives the packet; and turning the packet in the third computing node based on the second bypass signal to route the packet along the second direction, wherein the packet is received by the third computing node from the second computing node ([paragraph 0023-0024, 0028-0030] describes in the active mode of the active circuit 100, the first control signal SIG.sub.ctr11 can turn on the first switch SW1, and the second control signal SIG.sub.ctr12 can turn off the second switch SW2. In this case, the active element 110 can amplify the radio frequency signal SIG.sub.RF. In the bypass mode of the active circuit 100, the first control signal SIG.sub.ctr12 can turn off the first switch SW1 so as to make the first switch SW1 become an equivalent capacitor C.sub.e, and the second control signal SIG.sub.ctr12 can turn on the second switch SW2. In this case, the radio frequency signal SIG.sub.RF can be outputted to the output terminal OUT of the active circuit 100 through the bypass unit 130 directly without passing through the active element 110 while the equivalent capacitor C.sub.e can compensate the loading effect caused by the active element 110).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/Anders to include routing the packet along the first direction through the second computing node based on the first bypass signal from the first computing node; routing the packet through the second computing node based on the first bypass signal from the first computing node, and wherein the second computing node receives the first bypass signal by way of a faster route than the second computing node receives the packet; and turning the packet in the third computing node based on the second bypass signal to route the packet along the second direction, wherein the packet is received by the third computing node from the second computing node as taught by Chen. One ordinary skill in the art would be motivated to utilize the teachings of Wang/Anders in the Chen system in order to avoid deteriorating the quality or the intensity of the output signals ([paragraph 0004] in Chen).
Regarding claim 2, the combination of Wang, Anders and Chen teaches the method, wherein the third computing node receives a third bypass signal that is based on the second bypass signal by way of a faster route than the third computing node receives the packet (Wang: [paragraph 0018-0022] describes group of switching nodes N (e.g. array of computing nodes) and switching node after next switching node (e.g. third computing node) receiving next forward control signal (e.g. third bypass signal) after first forward signal and another forward control signal according to another forward control signal (e.g. second bypass signal) immediately (e.g. faster) than switching node after next switching node (e.g. third computing node) receiving the packet data).
Regarding claim 3, the combination of Wang, Anders and Chen teaches the method, wherein the packet is routed through the third computing node in two clock cycles (Wang: [paragraph 0016-0018] describes packet data is routed through switching node after next switching node (e.g. third computing node) in two clock cycles).
Regarding claim 10, the combination of Wang, Anders and Chen teaches the method, further comprising outputting a third bypass signal from the second computing node, where in the third bypass signal indicates to route another packet through a fourth computing node of the array of computing nodes (Wang: [paragraph 0016-0018, 0022-0024] describes next forward control signal (e.g. third bypass signal) from the next switching node (e.g. second computing node) from the group of computing nodes indicates that to route next packet through different computing node (e.g. forth computing node) from the group of computing nodes).
Regarding claim 11, the combination of Wang, Anders and Chen teaches the method, wherein when the first bypass signal indicates that the packet can bypass the second computing node, routing the packet from the first computing node to the second computing node comprises routing the packet on a connection that does not allow the packet to turn at the second computing node (Chen: [paragraph 0023-0024, 0028-0030] describes] the first control signal SIG.sub.ctr11 for bypassing path indicates that bypass the SW2(e.g. second computing node) and routing the data from the SW1 (e.g. the first computing node) to the SW2 (e.g. second computing node) includes as turn off signal bypassing path at the SW2 (e.g. second computing node) so routing data will not flow to the SW2 (e.g. second computing node)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/ Anders to include wherein when the first bypass signal indicates that the packet can bypass the second computing node, routing the packet from the first computing node to the second computing node comprises routing the packet on a connection that does not allow the packet to turn at the second computing node as taught by Chen. One ordinary skill in the art would be motivated to utilize the teachings of Wang/ Anders in the Chen system in order to avoid deteriorating the quality or the intensity of the output signals ([paragraph 0004] in Chen).
Regarding claim 12, Wang teaches a computing system comprising: a first computing node; and a second computing node, wherein the first and second computing nodes are included in a computing node array ([paragraph 0016-0022] describes a network switch (e.g. a computing system) comprising switching nodes (e.g. a first computing node; and a second computing node) in a group of switching nodes),
wherein the first computing node is configured to route a bypass signal on a first route to the second computing node and to route packet data to the second computing node on a second route([paragraph 0022-0024] describe the forward control signal (e.g. the first bypass signal) from a switching node (e.g. computing node) to route packet data through next switching node (e.g. second computing node)),
Wang fails to teach wherein the first route is faster than the second route, and wherein the bypass signal is indicative of whether to turn the packet data from a first routing direction to a second routing direction that is orthogonal to the first routing direction in the second computing node.
However, Anders teaches wherein the bypass signal is indicative of whether to turn the packet data from a first routing direction to a second routing direction that is orthogonal to the first routing direction in the second computing node ([paragraph 0026-0027, 0042-0046, 0075] describes another packet forward control signal (e.g. second bypass signal) indicates to send packet in third router node (e.g. a third computing node0 of the nodes of routers to route the packet along a different direction than first direction perpendicular (e.g. orthogonal) to the first direction);
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang to include wherein the bypass signal is indicative of whether to turn the packet data from a first routing direction to a second routing direction that is orthogonal to the first routing direction in the second computing node as taught by Anders. One ordinary skill in the art would be motivated to utilize the teachings of Wang in the Anders system in order to provide communication between the routers and their associated cores ([paragraph 0028] in Anders).
Wang and Anders fails to teach wherein the first route is faster than the second route
However, Chen teaches wherein the first route is faster than the second route ([paragraph 0023-0024, 0028-0030] describes in the active mode of the active circuit 100, the first control signal SIG.sub.ctr11 can turn on the first switch SW1, and the second control signal SIG.sub.ctr12 can turn off the second switch SW2. In this case, the active element 110 can amplify the radio frequency signal SIG.sub.RF. In the bypass mode of the active circuit 100, the first control signal SIG.sub.ctr12 can turn off the first switch SW1 so as to make the first switch SW1 become an equivalent capacitor C.sub.e, and the second control signal SIG.sub.ctr12 can turn on the second switch SW2. In this case, the radio frequency signal SIG.sub.RF can be outputted to the output terminal OUT of the active circuit 100 through the bypass unit 130 directly without passing through the active element 110 while the equivalent capacitor C.sub.e can compensate the loading effect caused by the active element 110).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/Anders to include wherein the first route is faster than the second route as taught by Chen. One ordinary skill in the art would be motivated to utilize the teachings of Wang/Anders in the Chen system in order to avoid deteriorating the quality or the intensity of the output signals ([paragraph 0004] in Chen).
Regarding claim 13, the combination of Wang, Anders and Chen teaches the system, further comprising a third computing node, wherein the first, second, and third computing nodes are included in a same row or column of the computing node array, and wherein the first computing node is configured to output a second bypass signal indicative of whether to turn the packet data at the third computing node (Chen: [0023-0024, 0028-0033] describes SW1, SW2 AND SW3 (e.g. first, second, and third computing nodes) are connected in series (e.g. in same row) of group of switching nodes and SW1 (e.g. first computing node) is configured to output a second control bypass signal indicative of whether to turn the packet data at the SW3 (e.g. third computing node) or not).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/ Anders to include wherein the first, second, and third computing nodes are included in a same row or column of the computing node array, and wherein the first computing node is configured to output a second bypass signal indicative of whether to turn the packet data at the third computing node as taught by Chen. One ordinary skill in the art would be motivated to utilize the teachings of Wang/ Anders in the Chen system in order to avoid deteriorating the quality or the intensity of the output signals ([paragraph 0004] in Chen).
Regarding claim 14, this claim contains limitations found within that of claim 3 and the same rationale to rejection is used.
Regarding claim 17, the combination of Wang, Anders and Chen teaches the system, wherein the computing system is configured to route the packet data through the second computing node in path between the first computing node and the third computing node in a single clock cycle (Wang: [paragraph 0018-0022] describes the packet data is routed from the next switching node (e.g. second computing node) through the different switching node (e.g. third computing node) in each clock cycle (e.g. a single clock cycle)).
9. Claims 4-6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2017/0024346 A1); in view of Anders et al. (US 20150071282 A1); further in view of Chen et al. (US 2017/0272059 A1); and further in view of Ramey et al. (US 2014/0122560 A1).
Regarding claim 4, Wang, Anders and Chen fails to teach the method, wherein the packet comprises a header portion and a data portion, and the header portion is routed one cycle ahead of the data portion.
However, Ramey teaches the method, wherein the packet comprises a header portion and a data portion ([paragraph 0041-0042] describes packet includes a header and data),
and the header portion is routed one cycle ahead of the data portion ([paragraph 0004, 0034] describes compute nodes and clock cycles [paragraph 0034-0036, 0041-0042] describes the header is routed one cycle before the data).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/ Anders/ Chen to include wherein the packet comprises a header portion and a data portion, and the header portion is routed one cycle ahead of the data portion as taught by Ramey. One ordinary skill in the art would be motivated to utilize the teachings of Wang/ Anders/ Chen in the Ramey system in order to provide network switching functions within the plurality of tiled compute nodes ([paragraph 0004] in Ramey).
Regarding claim 5, the combination of Wang, Anders, Chen and Ramey teaches the method, wherein routing the packet through the second computing node (Wang: [paragraph 0022-0024] describe the forward control signal (e.g. the first bypass signal) from a switching node (e.g. computing node) to route packet data through next switching node (e.g. second computing node)) comprises:
routing the header portion in a first clock cycle; and routing the data portion in a second clock cycle (Ramey: [paragraph 0034-0036, 0041-0042] describes routing the header of the packet in a clock cycle and routing the data of the packet in another clock cycle (e.g. second clock cycle)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/ Anders/ Chen to include routing the header portion in a first clock cycle; and routing the data portion in a second clock cycle as taught by Ramey. One ordinary skill in the art would be motivated to utilize the teachings of Wang/ Anders/ Chen in the Ramey system in order to provide network switching functions within the plurality of tiled compute nodes ([paragraph 0004] in Ramey).
Regarding claim 6, the combination of Wang, Anders, Chen and Ramey teaches the method, wherein routing the packet through the second computing node (Wang: [paragraph 0022-0024] describe the forward control signal (e.g. the first bypass signal) from a switching node (e.g. computing node) to route packet data through next switching node (e.g. second computing node)) comprises:
storing the first bypass signal in a state element of the second computing node (Chen: [paragraph 0020-0024] describes storing the signal bypassing path according to the first control signal (e.g. first bypass signal) in an active element of next node (e.g. second computing node));
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/ Anders to include storing the first bypass signal in a state element of the second computing node as taught by Chen. One ordinary skill in the art would be motivated to utilize the teachings of Wang/ Anders in the Chen system in order to avoid deteriorating the quality or the intensity of the output signals ([paragraph 0004] in Chen).
routing the header portion from the first computing node to the second computing node based at least in part on the first bypass signal; and after routing the header portion from the first computing node to the second computing node, routing the data portion from the first computing node to the second computing node based at least in part on the first bypass signal (Ramey: [paragraph 0034-0036, 0040-0042] describes routing the header of the packet from computing node to next computing node according to signal in bypass path (e.g. first bypass signal) and after routing header routing the data of the packet from computing node to next computing node according to signal in bypass path (e.g. first bypass signal)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/ Anders/ Chen to include routing the header portion from the first computing node to the second computing node based at least in part on the first bypass signal and after routing the header portion from the first computing node to the second computing node, routing the data portion from the first computing node to the second computing node based at least in part on the first bypass signal as taught by Ramey. One ordinary skill in the art would be motivated to utilize the teachings of Wang/ Anders/ Chen in the Ramey system in order to provide network switching functions within the plurality of tiled compute nodes ([paragraph 0004] in Ramey).
Regarding claim 15, Wang, Anders and Chen fails to teach wherein a packet comprises a header and a data portion, and the second computing node is configured to route the header to the third computing node at least one clock cycle before routing the data portion to the third computing node, and the data portion comprises the packet data.
However, Ramey teaches wherein the packet comprises a header and a data portion([paragraph 0041-0042] describes packet includes a header and data),
and the second computing node is configured to route the header to the third computing node at least one clock cycle before routing the data portion to the third computing node, and the data portion comprises the packet data (Ramey: [paragraph 0034-0036, 0041-0044] describes next switching node (e.g. second computing node) is configured to routing the header of the packet in a clock cycle to different switching node (e.g. third computing node) before routing the data of the packet to the different switching node (e.g. third computing node)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/ Anders/Chen to include wherein the packet comprises a header and a data portion, and the second computing node is configured to route the header to the third computing node at least one clock cycle before routing the data portion to the third computing node, and the data portion comprises the packet data as taught by Ramey. One ordinary skill in the art would be motivated to utilize the teachings of Wang/ Anders/ Chen in the Ramey system in order to provide network switching functions within the plurality of tiled compute nodes ([paragraph 0004] in Ramey).
10. Claims 7-8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2017/0024346 A1); in view of Anders et al. (US 20150071282 A1); further in view of Chen et al. (US 2017/0272059 A1); and further in view of Kovacevic et al. (US 2006/0209709 A1).
Regarding claim 7, the combination of Wang, Anders and Chen teaches the method, wherein routing the packet through the second computing node (Wang: [paragraph 0022-0024] describe the forward control signal (e.g. the first bypass signal) from a switching node (e.g. computing node) to route packet data through next switching node (e.g. second computing node))said routing the packet through the second computing node ),
Wang, Anders and Chen fails to teach wherein the packet comprises a plurality of sub-packets, each sub-packet comprises a header and a data portion comprises: routing the plurality of sub-packets from the first computing node to the second computing node; and comparing at least a portion of each header of each of the plurality of sub- packets.
However, Kovacevic teaches wherein the packet comprises a plurality of sub-packets, each sub-packet comprises a header and a data portion ([paragraph 0003-0005, 0010, 0086-0087] describes the packet is subdivided into multiple sub packets and each sub packet comprises a header potion and a data portion),
comprises: routing the plurality of sub-packets from the first computing node to the second computing node; and comparing at least a portion of each header of each of the plurality of sub- packets ([paragraph 0086-0087, 0208, 0393-0395] describes routing multiple sub packets from one node to another node (e.g. the first computing node to the second computing node) comparing header of each of multiple sub packets).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/ Anders/ Chen to include wherein the packet comprises a plurality of sub-packets, each sub-packet comprises a header and a data portion comprises: routing the plurality of sub-packets from the first computing node to the second computing node; and comparing at least a portion of each header of each of the plurality of sub- packets as taught by Kovacevic. One ordinary skill in the art would be motivated to utilize the teachings of Wang/Chen/ Anders in the Kovacevic system in order to assure that the data stream continues to be a valid data stream ([paragraph 0102] in Kovacevic).
Regarding claim 8, the combination of Wang, Anders , Chen and Kovacevic teaches the method, further comprising: determining that there is a header mismatch based on said comparing; and providing an error signal responsive to said determining (Kovacevic: [paragraph 0086-0087, 0393-0395] describes determining that there is a header mismatch based on comparing and generating signal error based on comparison).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/ Anders/ Chen to include determining that there is a header mismatch based on said comparing; and providing an error signal responsive to said determining as taught by Kovacevic. One ordinary skill in the art would be motivated to utilize the teachings of Wang/ Anders/ Chen in the Kovacevic system in order to indicate that the data being received may be corrupted due to a potential error in the data path ([paragraph 0090] in Kovacevic).
Regarding claim 16, this claim contains limitations found within that of claim 7 and the same rationale to rejection is used.
11. Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2017/0024346 A1); in view of Anders et al. (US 20150071282 A1); further in view of Chen et al. (US 2017/0272059 A1); and further in view of Aybay et al. (US 8724628 B1).
Regarding claim 9, Wang, Anders and Chen fails to teach the method, wherein routing the packet through the second computing node is further based one or more other packets waiting to exit the second computing node and an available capacity of a destination queue of the packet.
However, Aybay teaches the method, wherein routing the packet through the second computing node is further based one or more other packets waiting to exit the second computing node and an available capacity of a destination queue of the packet ([col 10 lines 5-49, col 15 lines 18-42] describes routing the packet through second module based on data packet waiting to leave second module and available capacity of a queue for destination of the data packet).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/ Anders/ Chen to include wherein routing the packet through the second computing node is further based one or more other packets waiting to exit the second computing node and an available capacity of a destination queue of the packet as taught by Aybay. One ordinary skill in the art would be motivated to utilize the teachings of Wang/ Anders / Chen in the Aybay system in order to provide load balancing within a switch fabric ([col 1 lines 6-7 ] in Aybay).
Regarding claim 20, Wang, Anders and Chen fails to teach the computing system, wherein the computing system is configured to determine the first route partly on at least one of a number of other packets waiting to exit the second computing node or an available capacity of a destination queue for the packet data.
However, Aybay teaches the computing system, wherein the computing system is configured to determine the first route partly on at least one of a number of other packets waiting to exit the second computing node or an available capacity of a destination queue for the packet ([col 10 lines 5-49, col 15 lines 18-42] describes routing the packet through second module based on data packet waiting to leave second module and available capacity of a queue for destination of the data packet).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/ Anders/ Chen to include wherein the computing system is configured to determine the first route partly on at least one of a number of other packets waiting to exit the second computing node or an available capacity of a destination queue for the packet data as taught by Aybay. One ordinary skill in the art would be motivated to utilize the teachings of Wang/ Anders/ Chen in the Aybay system in order to provide load balancing within a switch fabric ([col 1 lines 6-7 ] in Aybay).
12. Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2017/0024346 A1); in view of Anders et al. (US 2015/0071282 A1); further in view of Chen et al. (US 2017/0272059 A1); and further in view of Lovell et al. (US 2008/0082786 A1).
Regarding claim 18, Wang, Anders and Chen fails to teach the computing system, wherein the computing system is configured to perform neural network training.
However, Lovell teaches the computing system, wherein the computing system is configured to perform neural network training ([paragraph 0047, 0050, 0190] describes computing system is configured to perform artificial neural network training).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/ Anders/ Chen to include wherein the computing system is configured to perform neural network training as taught by Lovell. One ordinary skill in the art would be motivated to utilize the teachings of Wang/ Anders/ Chen in the Lovell system in order to provide neural networks actually being only one of a large number of different kinds of problems such as expert system knowledge bases that the Connectionist Machines can address ([paragraph 0190 ] in Lovell).
Regarding claim 19, Wang, Anders and Chen fails to teach the computing system, wherein a system on a wafer comprises the computing node array.
However, Lovell teaches the computing system, wherein a system on a wafer comprises the computing node array ([paragraph 0105, 0108, 0114] describes a system on a wafer comprises array of computing nodes).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Wang/ Anders / Chen to include wherein a system on a wafer comprises the computing node array as taught by Lovell. One ordinary skill in the art would be motivated to utilize the teachings of Wang/ Anders/ Chen in the Lovell system in order to establish their own fabrication protocols ([paragraph 0786 ] in Lovell).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
- Gratz et al., US 20140219097 A1, The present disclosure relates to an example of a method for a first router to adaptively determine status within a network
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEHULKUMAR J SHAH whose telephone number is (571)272-1072. The examiner can normally be reached Mon-Fri, 6:05 am-3:55 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TONIA DOLLINGER can be reached at 571-272-4170. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.J.S/Examiner, Art Unit 2459 /TONIA L DOLLINGER/Supervisory Patent Examiner, Art Unit 2459
Prosecution Insights