DETAILED ACTION
This Communication is a First Action on the Merits (FAOM). Claims 1-21, as originally filed, are pending and have been considered as follows.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 and 10-19 are rejected under 35 U.S.C. 103 as being unpatentable over Law et al (2016/0211241 A1) in view of Lu et al (2024/0078041 A1).
As per Claim 1, Law teaches a method of dead die bypass routing, the method comprising: routing a packet from a source die to an intermediate die via a first route (Figures 16A and 16B; Figure 22 – Reference 2200; Page 10, Paragraphs [0124] – [0127]), the first route comprising turning the packet from a first channel of a plurality of first channels (Figure 16B – References 1602, 1612 and 1614; Page 7, Paragraph [0100]) to a second channel of the plurality of second channels (Figure 16B – References 1604, 1618 and 1620; Page 7, Paragraph [0100]).
(Note: In paragraphs [0124], Law describes Figure 22 which illustrates a switching process occurring within a three-dimensional [3D] integrated circuit [IC] as depicted in any of Figures 1, 5, 6, or 9-21; at least partially by a processing circuit [See Figure 21 – Reference 2110] in a suitable apparatus. In paragraph [0125], Law describes receiving a signal via a first signal path [i.e. a first route: See Figure 22 – Reference 2202; first signal path: Figure 16 – Reference 1612: See paragraph 0100] at a first switch circuit on a first die [i.e. source die] lying within a geometric plane)
(Note: In paragraph [0127], Law describes the first switch circuit being controlled to route the signal to a second switch circuit; where the first circuit is on a first die and the second circuit is on a second die lying within a second geometric plane [i.e. an intermediate die] where the second geometric plane is different from the first geometric plane]. In paragraph [0100], Law describes Figure 16 which illustrates a first and a second signal path locates on a first layer [i.e. first die]; as well as a third and a fourth signal path locates on a second layer [i.e. second die])
Law also teaches the first channel being orthogonal to the second channel (Figures 19 and 22; Page 8, Paragraph [0105]; Page 10, Paragraph [0130]); and routing the packet from the intermediate die to a destination die via a second route (Page 10, Paragraph [0131]), the second route comprising turning the packet from the second channel to a third channel that is orthogonal to the second channel (Figure 19; Page , Paragraph [0105]; Page 10, Paragraphs [0130] and [0131]).
(Note: In paragraph [0130], Law describes Figure 22 and indicates the first and second die may be oriented to one another in various ways. In some cases, the second die is stacked on top of the first die. In some cases, the first and second geometric planes are parallel, while in other cases they may not be. In paragraph [0105], Law describes Figure 19 and also indicates that said dies are disposed in different geometric planes to one another, in particular the first die [Reference 1902] being at a right angle to the second die [Reference 1904])
(Note: In paragraph [0131], Law describes signals being routed to at least one other die as described in process 2200 shown in Figure 22 where the second switch circuit is controlled via the second logic circuit to route signals to a third switch circuit, where the third switch circuit is located on a third die lying within a third geometric plane that is different from the first and second geometric planes [i.e. destination die]. The process 2200 also includes controlling the third switch circuit via a third logic to route the signal to a third signal path [i.e. a second route] where the third logic circuit is on the third die)
Law further teaches wherein a system on a wafer includes a die array comprising the source die, the intermediate die, the destination die, and at least one dead die (Figure 23; Page 4, Paragraph [0047]; Page 5, Paragraph [0077]; Page 10, Paragraphs [0132] – [0134]), and wherein the first route and the second route bypass the at least one dead die (Figure 23; Page4 , Paragraph [0047]; Page 5, Paragraph [0077]; Page 10, Paragraphs [0132] – [0134]).
(Note: Figure 23, which may take place within a 3D-IC illustrates a process for handling a fault condition. A fault condition may be identified on a first die by means of a diagnostic test which returns as a failure condition [See Reference 2302]. As a result, routing of the signal to a second signal path is triggered as a result of the identified fault condition [See Reference 2304])
Law does not teach one or more routing rules, the one or more routing rules allowing the first channel to route the packet to a subset of the plurality of second channels that includes the second channel. However, Lu teaches one or more routing rules, the one or more routing rules allowing the first channel to route the packet to a subset of the plurality of second channels that includes the second channel (Figures 41 – 46; Figure 7 – References 702, 704 and 706; Page 12, Paragraphs [0086] – [0089]; Page 14, Paragraphs [0102] – [0104]).
(Note: In paragraphs [0101] and [0102], Lu describes a die-based rank management method illustrated in Figure 7 where a controller maps rank selections of a device/module to ranks of usable/functional dies. So as shown in Figure 45 there are two controllers [i.e. C0 and C1] with four channels with each channel having an initial rank/priority [0-3 with 0 being highest priority and 3 being lowest priority] so between the two controllers there are a total of 8 channels. [e.g. Initial ranking C0 with 4 channels ranked 0-3 and C1 with 4 channels ranked 0-3])
(Note: In paragraph [0102], Lu describes testing or evaluating the dies to determine if all dies are functional or if any are dead/unusable [i.e. unsuitable for use]. Dies determined to be dead or unsuitable for use are shown in Figure 45 as having a value of 0 [e.g. value 414-0 of die 410-0, additional dead dies are 410-2 and 410-6. A revised mapped ranking is reflected in Figure 46 with storage elements located within each controller indicating an initial rank with a corresponding mapped rank which reflects the removal dead dies)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Law with the method taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
As per Claim 2, the combination of Law and Lu teaches wherein the at least one dead die comprises two dead dies, and the first route and the second route bypass the two dead dies as described in Claim 1. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Law with the method taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
As per Claim 3, the combination of Law and Lu teaches a method dead die bypass routing as described in Claim 1. (Note: The recited first die in Claim 3 is recited at the source die in Claim 1. The recited second die in Claim 3 is recited at the intermediate die in Claim 1. The recited first channel in Claim 3 is recited at the first route in Claim 1. The recited third die in Claim 3 is recited at the destination die in Claim 1. A plurality of channels is taught as illustrated in Figures 45 and 46 of Lu. An array is taught by the field programmable gate array [FPGA: See paragraph 0117 of Law and paragraph 0020 of Lu])
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Law with the method taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
As per Claims 4 and 19, the combination of Law and Lu teaches querying a routing table based at least in part on an address of the third die, wherein the routing table complies with the one or more routing rules (Lu: Page 4, Paragraph [0036]; Page 6, Paragraph [0048]). (Note: In paragraphs [0036] and [0048]; Lu describes the use of lookup tables [i.e. routing table storing information] and mapping subsequently. Lookup tables and mapping techniques store precomputed data and map specific inputs to corresponding outputs by using a key-value pair to return a value which is found to read on the claimed recitation)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method and system taught by Law with the method and system taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
As per Claims 5 and 18, the combination of Law and Lu teaches wherein the one or more routing rules prevent the packet from being routed in a loop as described in Claim 1. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method and system taught by Law with the method and system taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
As per Claim 6, the combination of Law and Lu teaches wherein each channel of the plurality of first channels and each channel of the plurality of second channels is assigned a priority, and wherein the one or more routing rules disallows turns from a lower priority channel of the plurality of first channels to a higher priority channel of the plurality of second channels as described in Claim 1. (Note: The mapped ranking illustrated in in Figure 46 is an illustration of how priority ranking is used to combat potential congestion)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Law with the method taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
As per Claim 7, the combination of Law and Lu teaches wherein a route from the first die to the third die is configured to end at a lowest priority first channel of the plurality of first channels or a lowest priority second channel of the plurality of second channels (Lu: Page 4, Paragraph [0033]). (Note: In paragraph [0033], Lu indicates that a controller or another entity [e.g. external die tester/rank manager can configure the rank portion of the entry]. The Examiner is considering the configuration of rank [physical or functional] as the configuration of priority)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Law with the method taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
As per Claim 10, the combination of Law and Lu teaches wherein the routing table includes a default route, the default route to be used if there is not a defined route from the first die to the second die (Lu: Page 4, Paragraph [0035]). (Note: In paragraph [0035], Lu indicates that the controller seeks to verify the rank selection is present and if not then it may rely on default routing for rank selection [i.e. using a default route if there is not a defined route from the first die to the second die])
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Law with the method taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
As per Claims 11 and 12, the combination of Law and Lu teaches wherein the method routes the packet around at least two dead dies; and routing the packet with multiple turns as described in Claims 1 and 3 above. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Law with the method taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
As per Claim 13, the combination of Law and Lu teaches wherein a system on a wafer includes the array as described in Claim 3 (Note: [FPGA: See paragraph 0117 of Law and paragraph 0020 of Lu]) It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Law with the method taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
As per Claim 14, the combination of Law and Lu teaches routing the packet from the third die to a die outside of the array (Lu: Page 2, Paragraph [0018]). (Note: In paragraph [0018], Lu indicates that the operating environment my includes apparatus including among other things Internet of Things [IoT] devices, tablets, smartphones, notebook computers, vehicles, servers, server clusters, wearable devices [i.e. smartwatch], entertainment devices, desktop computers, motherboards, sensors, etc. The combination of prior art supports an interpretation where an IoT device is in communication with a sensor or a server and a packet is routed from the third die to a die outside of the array)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Law with the method taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
As per Claim 15, the combination of Law and Lu teaches a method of dead die bypass routing as described in Claims 1 and 3, The combination of Law and Lu also teaches a die array comprising a first die, a second die, a third die, and a dead die as described in Claims 1 and 3 above.
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method and system taught by Law with the method and system taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
As per Claim 16, the combination of Law and Lu teaches wherein the processing system is configured to route the packet from the first die to the third die by way of multiple turns as described in Claims 9 and 12. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method and system taught by Law with the method and system taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
As per Claim 17, the combination of Law and Lu teaches wherein the die array comprises a second dead die, and the processing system is configured to bypass the second dead die when routing the packet from the first die to the third die as described in Claims 1 and 11. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method and system taught by Law with the method and system taught by Lu to enable the routing of packets around failed dies to ensure a system maintains consistent communication reducing the likelihood of traffic bottlenecks instead of discarding an expensive multi-die package thereby increasing the yield of usable chips and lowering production costs.
Claim(s) 8, 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Law et al (2016/0211241 A1) in view of Lu et al (2024/0078041 A1) as applied to Claims 6 and 19 above, and further in view of Wu et al (2022/0413719 A1).
As per Claim 8, the combination of Law and Lu teaches the method of Claim 6; but does not teach wherein the one or more routing rules allow the packet to be routed to an escape channel, the escape channel configured to allow the packet to move to a channel with a higher priority. However, Wu teaches wherein the one or more routing rules allow the packet to be routed to an escape channel, the escape channel configured to allow the packet to move to a channel with a higher priority (Figure 4 – References 420, 435 and 440; Page 8, Paragraphs [0078] and [0079]).
(Note: In paragraph [0078], Wu describes a memory die manager responsible for issuing commands associated with various priority commands [e.g. normal priority and high priority]. In paragraph [0079], Wu indicates high priority commands are issued based on associated priority level or a threshold being reached [i.e. a lower priority message becoming a high priority message dues to the crossing of some threshold – routing to an escape channel])
(Note: In paragraph [0079], Wu indicates if a command is received and entered into a first priority queue while commands are being issued from the intermediate priority queue the memory die manager can designate the newly-received command as a high priority command. Accordingly, the controller issues the command before issuing any other command)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Law and Lu with the method and taught by Wu to prioritize critical packets (e.g. coherence messages) so that they do not get stuck in low priority queues which helps avoid protocol-level deadlocks ensuring time-critical packets (i.e. directory-based coherence requests) reach their destination faster.
As per Claims 9 and 20, the combination of Law, Lu and Wu teaches wherein a route from the first die to the third die includes a second turn from the second channel to a third channel, wherein the third channel has a lower priority than the second channel, and wherein second channel has a lower priority than the first channel.
(Note: In paragraph [0078], Wu describes messages as being high priority and normal priority. In paragraph [0079], Wu describes a priority queue and an intermediate priority queue. The teachings of Wu support an interpretation of a minimum of three types of message queues – normal priority, intermediate priority and high priority in increasing priority order)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method and system taught by Law and Lu with the method and system taught by Wu to prioritize critical packets (e.g. coherence messages) so that they do not get stuck in low priority queues which helps avoid protocol-level deadlocks ensuring time-critical packets (i.e. directory-based coherence requests) reach their destination faster.
Claim(s) 21 is rejected under 35 U.S.C. 103 as being unpatentable over Law et al (2016/0211241 A1) in view of Lu et al (2024/0078041 A1) as applied to Claim 15 above, and further in view of Nowatzyk et al (2021/0216853 A1).
As per Claim 21, the combination of Law and Lu teaches the processing system of Claim 15; but does not teach wherein the processing system is configured to generate neural network training data. However, Nowatzyk teaches wherein the processing system is configured to generate neural network training data (Page 2, Paragraphs [0019] and [0022]). (Note: In paragraphs [0019] and [0022], Nowatzyk describes a neural network accelerator using provided inputs to train the neural network to adjust the parameters of the neural network)
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the system taught by Law and Lu with the system taught by Nowatzyk to enable a network system to learn and adapt to new dead dies on the fly, allowing the routing algorithm to reroute around damaged areas dynamically, thus increasing the lifespan and reliability of the chip.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Peterson et al (9,026,714 B2), Pandya et al (2017/0123994 A1), Thottethodi et al (9,065,722 B2), VISWANATH et al (2024/0143890 A1) and Roberts et al (2018/0300265 A1). Each of these describes systems and methods of routing packets within modules and between system elements.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHARYE POPE whose telephone number is (571)270-5587. The examiner can normally be reached Monday - Friday 8AM - 4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ahmad Matar can be reached at 571-272-7488. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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KHARYE POPE
Primary Examiner
Art Unit 2693
/KHARYE POPE/Primary Examiner, Art Unit 2693
Prosecution Insights