DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on February 16, 2024. These drawings are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication 2008/0160252 to Leon et al. (hereinafter Leon).
Claim 1
Leon (FIG. 1-4, 7) discloses a wiring substrate for an electronic control device, comprising:
an electronic component (paragraph 11) mounted on a multilayer substrate (102, paragraph 36);
a signal wire (106) of a surface layer (104F) or an inner layer (104B-E) of the multilayer substrate (102), the signal wire (106) being electrically connected to the electronic component (paragraph 36); and
a conductor pad (126) for contact with an inspection probe (paragraph 36), the conductor pad (126) being provided to the signal wire (106) and exposed on a surface (110) of the multilayer substrate (102),
wherein the conductor pad (126) is composed of:
a via (110) provided to the multilayer substrate (102) along a lamination direction of the multilayer substrate (102) and connected to the signal wire (106, paragraph 36); and
a solder (300, paragraph 41) filled in an opening portion (116) of the via (110).
Claim 2
Leon discloses the wiring substrate for the electronic control device according to claim 1, wherein the solder (300) filled in the opening portion (116) is formed in a shape in which a middle part is recessed compared to a peripheral edge portion of the solder (300, as shown in FIG. 3, paragraph 41).
Claim 3
Leon discloses the wiring substrate for the electronic control device according to claim 1, wherein the via (100) is connected to a signal wire (106) provided to the inner layer (104B-E) of the multilayer substrate (102) and is provided independently from another signal wire (106) on the surface (110) of the multilayer substrate (102; paragraph 36).
Claim 4
Leon discloses the wiring substrate for the electronic control device according to claim 1, wherein the via (100) connects a signal wire (106) on the surface layer (104F) of the multilayer substrate (102) with a signal wire (106) on the inner layer (104B-E) of the multilayer substrate (102) in the lamination direction of the multilayer substrate (102; paragraph 36).
Claim 6
Leon discloses the wiring substrate for the electronic control device according to claim 1, wherein the via (110) has a taper shape (paragraph 52) in which an opening portion side (110) in which the solder (300) is filled has a relatively large diameter (FIG. 7, paragraph 53).
Claim 7
Leon (FIG. 1-4) discloses a method for manufacturing a wiring substrate for an electronic control device, comprising:
forming a multilayer substrate (102, paragraph 36) provided with a signal wire (106, paragraph 36);
forming a via (100, paragraph 36) along a lamination direction of the multilayer substrate (102) so as to be electrically connected to a signal wire (106) of a surface layer (104F) or an inner layer (104B-E) of the multilayer substrate (102);
disposing a solder material (300) in an opening portion (116) of the via (100); and
heating and cooling the solder material (300; paragraph 39-41).
Claims 1-5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication 2009/0058445 to Leon (hereinafter ‘445).
Claim 1
‘445 (FIG. 7-13) discloses a wiring substrate for an electronic control device, comprising:
an electronic component (paragraph 2, 4) mounted on a multilayer substrate (21, paragraph 69);
a signal wire (paragraph 69) of a surface layer or an inner layer of the multilayer substrate (21), the signal wire (paragraph 69) being electrically connected to the electronic component (paragraph 69); and
a conductor pad (120, paragraph 69) for contact with an inspection probe (paragraph 77), the conductor pad (120) being provided to the signal wire (paragraph 69) and exposed on a surface of the multilayer substrate (21),
wherein the conductor pad (120) is composed of:
a via (100, paragraph 69) provided to the multilayer substrate (21) along a lamination direction of the multilayer substrate (21) and connected to the signal wire (paragraph 69); and
a solder (60, paragraph 74) filled in an opening portion of the via (100).
Claim 2
‘445 discloses the wiring substrate (21) for the electronic control device according to claim 1, wherein the solder (60) filled in the opening portion is formed in a shape in which a middle part is recessed compared to a peripheral edge portion of the solder (60; as shown in FIG. 11A-B, 12A-B, 13A-C).
Claim 3
‘445 discloses the wiring substrate (21) for the electronic control device according to claim 1, wherein the via (100) is connected to a signal wire (paragraph 69) provided to the inner layer of the multilayer substrate (21) and is provided independently from another signal wire (paragraph 69) on the surface of the multilayer substrate (21; paragraph 69).
Claim 4
‘445 discloses the wiring substrate (21) for the electronic control device according to claim 1, wherein the via (100) connects a signal wire (paragraph 69) on the surface layer of the multilayer substrate (21) with a signal wire (paragraph 69) on the inner layer of the multilayer substrate (21) in the lamination direction of the multilayer substrate (21; paragraph 69).
Claim 5
‘445 discloses the wiring substrate (21) for the electronic control device according to claim 1, wherein the via (100) is a blind via (100; paragraph 69).
Claim 7
‘445 discloses a method for manufacturing a wiring substrate (21) for an electronic control device, comprising:
forming a multilayer substrate (21, paragraph 69) provided with a signal wire (paragraph 69);
forming a via (100) along a lamination direction of the multilayer substrate (21) so as to be electrically connected to a signal wire (paragraph 69) of a surface layer or an inner layer of the multilayer substrate (21; paragraph 69);
disposing a solder (60; paragraph 74) material in an opening portion of the via (100); and
heating and cooling (paragraph 74-75) the solder (60) material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN MILAKOVICH whose telephone number is (571) 270-3087. The examiner can normally be reached Monday - Friday 9:00 AM - 5:00 PM EST.
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/NATHAN MILAKOVICH/Primary Examiner, Art Unit 2848