DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application and preliminary amendment filed 2/20/2024. In the amendment, claims 1, 4-6 and 9 were amended, claims 8 and 10 were cancelled, and claims 11-16 were added. As such, claims 1-7, 9 and 11-16 are pending and have been examined. Claims 1-7, 9 and 11-16 are rejected.
Priority
The present application is a national stage entry (under 35 U.S.C. § 371) of international application no. PCT/JP2021/032453 filed 9/03/2021.
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed 2/20/2024 and 10/24/2024, which comply with 37 CFR 1.97. As such, the information disclosure statements have been placed in the application file and the information referred to therein has been considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(3) because Figures 3A, 3D, 4, 5A and 8A-D include letters which do not measure at least .32 cm. (1/8 inch) in height (i.e., most of the subscript characters in FIGs. 3A, 3D, 4, 5A and 8A-C, and lowercase characters in FIG. 8D).
The drawings are also objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description:
2001 (see, e.g., paragraphs 46-61 describing FIG. 4).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure2 is objected to because of the following informalities:
Reference character 2003 shown in Figure 4 is not described in applicant’s specification (see, e.g., paragraphs 46-61 describing FIG. 4). Appropriate correction is required.
The title of the invention is objected to as not being descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. In particular, the title of the invention is “COMPUTING DEVICE, NEURAL NETWORK SYSTEM, NEURON MODEL DEVICE, COMPUTATION METHOD, AND TRAINED MODEL GENERATION METHOD”; however the title includes grammatical errors and is not clearly indicative of the claimed invention. In particular, it appears that the articles “A” are missing prior to the recitations of “COMPUTING DEVICE” and “NEURON MODEL DEVICE”. The examiner suggests that one way to address this objection would be to amend the title to read “A COMPUTING DEVICE[[,]] INCLUDING A SPIKING NEURAL NETWORK SYSTEM, A SPIKING NEURON MODEL DEVICE, AND COMPUTATION METHOD FOR CONTROLLING A COMPUTING DEIVCE INCLUDING A SPIKING NEURAL NETWORK
A descriptive title indicative of the invention will help in proper indexing, classifying, searching, etc. See, MPEP § 606.01. However, the title of the invention should be limited to 500 characters. The examiner suggests including the aspect(s) of the claims which Applicant believes to be novel or nonobvious over the prior art.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
an accumulation phase that adds currents and a decoding phase that converts a voltage in claims 1 and 7.
Regarding claims 1 and 7 and the above-noted three-prong test, the recited accumulation phase is a generic placeholder, that adds currents is functional language, and there is no recitation in claims 1 or 7 of sufficient structure to perform the adding. Also in claims 1 and 7, the recited decoding phase is a generic placeholder, that converts a voltage is functional language, and there is no recitation in claims 1 or 7 of sufficient structure to perform the decoding.
A review of the specification shows that the corresponding structure is not described in the specification for the 35 U.S.C. 112(f) limitations:
Regarding the above-noted phases recited in claims 1 and 7, although the phases are depicted in the black box block diagrams of FIGs. 3B-C, 3E and 4 and generally mentioned in paragraphs 6-10 and 143 (which merely repeat the claim language) and 40, 42-43, 45, 57 and 61 (which generally describe the aforementioned figures), the corresponding structure of the claimed phases capable of performing the claimed functions is not described in applicant’s specification.
The drawings merely show black-boxes designed to perform the entire claimed function (see, e.g., “Ph-Acc” and “Ph-Dec” shown in FIGs. 3B-C and 3E).
As such, the specification either fails to describe the claimed phases as noted above, or, at best, describes the claimed phases by their respective functions without disclosing any specific structure performing the claimed functions.
Accordingly, for these claim limitations, the written description fails to disclose both an algorithm(s) and special-purpose computer hardware to perform the algorithm(s). For more information, see MPEP § 2181.
If applicant wishes to provide further explanation or dispute the examiner's interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-7 and 11-16 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
Independent claims 1 and 7 both contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
In particular, and as previously noted, the claim limitations an accumulation phase that adds currents and a decoding phase that converts a voltage in independent claims 1 and 7 invoke 35 U.S.C. 112(f).
However, as noted above, the written description of the current application fails to disclose the corresponding structure, material, or acts for performing each of the above-identified claimed functions and to clearly link the structure, material, or acts to the function. In particular, for each of the claimed functions, the written description fails to disclose both an algorithm(s) and special-purpose computer hardware to perform the algorithm. For more information, see MPEP § 2181.
Accordingly, claims 1 and 7 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
Also, claims 2-6 and 11-16 which each depend directly or indirectly from claim 1, are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement under the same rationale as claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-7, 9 and 11-16 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Independent claims 1, 7 and 9 each recite “a voltage resulting from the addition” and “the current that flows into or out of an own neuron” (see, e.g., lines 3 and 5 of claim 1, lines 2-3 and 4-5 of claim 7, and lines 7 and 9-10 of claim 9). There is insufficient antecedent basis for these limitations in these claims. Applicant did not previously introduce any “addition” or any “current that flows into or out of an own neuron” in these claims. Applicant previously introduced “an accumulation phase that adds currents” in lines 1-2 of claims 1 and 7 and “adding current in the accumulation phase” in line 6 of claim 9. However, it is unclear if the subsequently-recited “voltage resulting from the addition” refers to a voltage value or amount (i.e., volts) corresponding to the “accumulation phase that adds currents” or the “adding current in the accumulation phase” (i.e., an amount of amps or amperage), or to some other voltage value or amount resulting from some other addition/adding. For the purposes of determining patent eligibility and comparison with the prior art, the Examiner is interpreting the recitations of “a voltage resulting from the addition” as any voltage value or amount corresponding to the “accumulation phase that adds currents” or the “adding current in the accumulation phase” and is interpreting “the current that flows into or out of an own neuron” as any current value or amount (i.e., a number of amps or amperage) that flows into or out of a neuron. Appropriate correction is required.
Lines 1-2 of claim 2 recite “wherein current flows to the current adding portion by the output of a preceding neuron provided in front of the own neuron”. This recitation is unclear for multiple reasons discussed below.
First, there is insufficient antecedent basis for the limitation “the output” in claim 2. Applicant did not previously introduce any “output of a preceding neuron” or any “output” of any neuron in this claim, or in its base claim, claim 1. As noted above, applicant previously introduced “current that flows into or out of an own neuron” in line 5 of claim 1. However, as also noted above, there is insufficient antecedent basis for that term in claim 1. Thus, it is unclear what “the output of a preceding neuron” refers to.
Second, the recitation in claim 2 of “wherein current flows to the current adding portion by the output of a preceding neuron provided in front of the own neuron” is also grammatically incorrect and unclear. In particular, it is unclear what is meant by “current flows to the current adding portion by the output of a preceding neuron”. That is, it is unclear if current flows into “the current adding portion” as output current from a preceding neuron, or if the current flows from another, unrecited component, “by” or via the preceding neuron.
Third, the recitation in claim 2 of “a preceding neuron provided in front of the own neuron” is unclear because the claim does not recite any arrangement of neurons (i.e., neurons in the claimed “spiking neural network”) that includes any arrangement or sequence of neurons. That is, claim 2, base claim 1 and the other claims are silent regarding any layers, hierarchy or sequence in which the recited “own neuron” is positioned, provided, placed or arranged. Applicant’s specification merely repeats the claim language in paragraph 144 and provides examples in 145-147 without defining what is meant by this term. As such, it is unclear what is meant by “a preceding neuron provided in front of the own neuron”. For examination purposes, “wherein current flows to the current adding portion by the output of a preceding neuron provided in front of the own neuron” is being interpreted as any current value or amount (i.e., amps or amperage) that flows or is provided/transmitted to the current adding portion as an output of any neuron in the spiking neural network that is before, previous to, precedes or comes before the own neuron, such as, but not limited to, any neuron that is in a layer of the spiking neural network that is before, previous to, precedes or comes before a layer that includes the own neuron. Appropriate correction is required.
Lines 4-6 of claim 2 recite “the current that the preceding neuron sends to the current adding portion depends on the potential difference between the reference voltage of the preceding neuron and the membrane potential of the own neuron.” There is insufficient antecedent basis for this limitation in this claim. Applicant did not previously introduce any “current that the preceding neuron sends”, any “potential difference” or any “reference voltage” in this claim, or in its base claim, claim 1. Applicant previously introduced “current flows to the current adding portion by the output of a preceding neuron provided in front of the own neuron” in lines 1-2 of claim 2. However, as discussed above, this recitation is unclear and also lacks antecedent basis. It is unclear if the subsequently-recited “the current that the preceding neuron sends to the current adding portion depends on the potential difference between the reference voltage of the preceding neuron4 and the membrane potential of the own neuron” refers to a current value or amount (i.e., a number of amps or amperage) that a previous or preceding neuron transmits or sends that depends upon a potential difference between a reference voltage of the previous or preceding neuron and the membrane potential of the own neuron or to some other current value or amount resulting from some other current sent or transmitted from the previous or preceding neuron. For examination purposes, the Examiner is interpreting the recitation of “the current that the preceding neuron sends to the current adding portion depends on the potential difference between the reference voltage of the preceding neuron and the membrane potential of the own neuron” as any current value or amount (i.e., a number of amps or amperage) that a previous or preceding neuron transmits or sends to the current adding portion, where the current depends upon any potential difference between any reference voltage of the previous or preceding neuron and the membrane potential of the own neuron. Appropriate correction is required.
As discussed above, the claim limitations an accumulation phase that adds currents and a decoding phase that converts a voltage in independent claims 1 and 7 invoke 35 U.S.C. 112(f).
As further noted above, there is insufficient disclosure in the specification of algorithms and specific computer hardware for implementing the above-noted, claimed phases. As such, the above-noted limitations recited in claims 1 and 7 are indefinite. Therefore, claims 1 and 7 are indefinite and are rejected under 35 U.S.C. 112(b). For the purposes of determining patent eligibility and comparison with the prior art, the examiner is interpreting the above-listed phases as any combination of software (i.e., a set of instructions, code, one or more functions or software modules) and/or hardware (i.e., circuitry and/or hardware logic components/modules) capable of performing the claimed functions.
Claims 3-5 and 11-16, which each depend directly or indirectly from claim 2, are rejected under 35 U.S.C. 112(b) as being indefinite under the same rationale as claim 2.
Also, claims 2-6 and 11-16, which each depend directly or indirectly from independent claim 1, are rejected under 35 U.S.C. 112(b) as being indefinite under the same rationale as claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Morie et al (U.S. Patent Application Pub. No. 2021/0294573 A1, hereinafter “Morie”) in view of Morie et al. (U.S. Patent Application Pub. No. 2021/0081176 A1, hereinafter “Morie ‘176”) and further in view of Zhang et al. (U.S. Patent Application Pub. No. 2009/0307165 A1, hereinafter “Zhang”).
Regarding claim 1, Morie discloses the invention as claimed including a computing device comprising a … neural network (see, e.g., paragraphs 61 and 73, “a neural network or the like implemented by the arithmetic logic unit” and “By configuring the layer structure of the multiply-accumulate operation devices 3, for example, a multi-layer perceptron type neural network or the like is constructed.”) that includes an accumulation phase that adds currents5 (see, e.g., FIGs. 11 and 12 – depicting a multiply-accumulate operation device and a calculation/adding of current by a multiply-accumulate signal by the multiply-accumulate operation device, and paragraphs 196-198, "The input signals (PMW signals) in2, in4, and in5 are input to the discharge circuit”, “the input signal line for inputting the input signals (PMW signals) in2, in4, and in5 to the discharge circuit or the like is a signal line included in the plurality of input lines” and “the input period T shown in FIG. 12, a switch 216a is turned OFF and a switch 216b is turned ON. Then, an input signal is input within the input period T" [i.e., switch 216b of FIG. 11 is turned on, switch 216a is turned off, and the charge corresponding to the current obtained by adding all the currents flowing through in1, in2, ... , and in6 in FIG. 11 is accumulated in the capacitor 213 and in FIG. 11 the current flowing through in1, in3, and in6 is current flowing in and the current flowing through in2, in4, and in5 is current flowing out, signal addition is carried out. The "input period T" corresponds to the "accumulation phase that adds currents"]) and a decoding phase that converts a voltage6 resulting from the addition7 to a voltage pulse timing (see, e.g., FIG. 12 –showing that there is an "output period" after the "input period" and paragraphs 186 and 198-199, “output result of the multiply-accumulate operation are converted into the pulse timing within the pulse output period T”, “At the start timing of the input period T shown in FIG. 12, a switch 216a is turned OFF and a switch 216b is turned ON.” [i.e., during the "output period" and “Positive weight charges corresponding to the input signals in1 and in3 are accumulated in the capacitor 213, and negative weight charges corresponding to the input signal in2 is discharged. … the capacitor 213 is charged in advance until the capacitor voltage reaches a predetermined preset value … cope with accumulation and discharging of charges and hold the charges (V+ -V-).” [i.e., the output pulse timing of FIG. 12 is determined based on the voltage held by the charge accumulated in the capacitor 213 during the "input period" and a threshold value θ, the "output period" corresponds to the "decoding phase that converts a voltage resulting from the addition to a voltage pulse timing"/V+ V-]),
wherein the spiking neural network comprises a current adding portion (see, e.g., see, e.g., FIG. 1 –showing a neural network with layers, neurons and signals/pulses/spikes and FIG. 11 - the neural network obtained by combining the neuron models shown corresponds to the "spiking neural network" with an adding portion - a multiply-accumulate operation device that calculates/adds current from a multiply-accumulate signal, and paragraphs 59, “The arithmetic logic unit 100 includes a plurality of signal lines 1, a plurality of input units 2, and a plurality of multiply-accumulate operation devices 3. Each of the signal lines 1 is a line that transmits an electrical signal of a predetermined method. As the electrical signal, for example, an analog signal representing a signal value using an analog amount such as the timing and width of the pulse is used. The directions in which electrical signals are transmitted are schematically illustrated in FIG. 1”, 63, “in FIG. 1, a plurality of input signal line is connected to one multiply-accumulate operation device 3 to provide a plurality of electrical signals”, 187, “accumulating an electronic signal (spike timing signal) whose pulse rises at timing corresponding to the signal value x, in a capacitor and calculating the multiply-accumulate signal on the basis of the timing when the accumulated electronic signal has become larger than a threshold voltage” [i.e., a spiking neural network] and 222, “value of charges corresponding to the sum of multiplication values accumulated by the accumulation unit" [i.e., switch 216b of FIG. 11 is turned on, switch 216a is turned off, and the charge corresponding to the current obtained by adding all the currents flowing through in1, in2, ... , and in6 in FIG. 11 is accumulated in the capacitor 213 and the current flowing through in1, in3, and in6 is current flowing in and the current flowing through in2, in4, and in5 is current flowing out, signal addition -a current adding portion]) wherein the current that flows into or out of an own neuron8 in the accumulation phase depends on … potential of that neuron (see, FIG. 11 - depicting electric potential of the terminal from among the two terminals of the capacitor 213 that is connected to the switch 216b and FIGs. 11-12 depicting a multiply-accumulate operation device and calculation/adding of current by a multiply-accumulate signal by the multiply-accumulate operation device, and paragraphs 196-198, "input signals (PMW signals) in2, in4, and in5 are input to the discharge circuit”, “the input signal line for inputting the input signals (PMW signals) in2, in4, and in5 to the discharge circuit or the like is a signal line included in the plurality of input lines” and “the input period T shown in FIG. 12, a switch 216a is turned OFF and a switch 216b is turned ON. Then, an input signal is input within the input period T" [i.e., switch 216b of FIG. 11 is turned on, switch 216a is turned off, and the charge corresponding to the current obtained by adding all the currents flowing through in1, in2, ... , and in6 in FIG. 11 is accumulated in the capacitor 213 and in FIG. 11 the current flowing through in1, in3, and in6 is current flowing in and the current flowing through in2, in4, and in5 is current flowing out, signal addition is carried out where current that flows in or out of a neuron in the accumulator/accumulation phase depends on the potential of the neuron]).
Although Morie substantially discloses the claimed invention and Morie discloses “a neural network is constructed using the arithmetic logic unit 100 using the multiply-accumulate operation devices” and “a method of accumulating an electronic signal (spike timing signal) whose pulse rises at timing corresponding to the signal value x, in a capacitor and calculating the multiply-accumulate signal on the basis of the timing when the accumulated electronic signal has become larger than a threshold voltage” in paragraphs 163 and 187, Morie is not relied on for explicitly disclosing a computing device comprising a spiking neural network.
In the same field, analogous art Morie ‘176 teaches a computing device comprising a spiking neural network (see, e.g., paragraph 96, “the present invention may be applied to a spiking neural network model showing information by spike pulses. … a multiply-accumulate operation device … that is applicable to a spiking neural network model” [i.e., a computing device including a spiking neural network]).
Morie and Morie ‘176 are analogous art because they are both directed to techniques and systems for using and implementing spiking neural networks/SNNs (see, e.g., Morie, paragraphs 163 and 187, and Morie ‘176, paragraph 96).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the disclosed system of Morie to incorporate the teachings of Morie ‘176 to provide “a spiking neural network model showing information by spike pulses” by using “a multiply-accumulate operation device … that is applicable to a spiking neural network model” (see, e.g., Morie ‘176 paragraph 96). One of ordinary skill in the art would have been motived to combine the device of Morie with the spiking neural network with the multiply-accumulate operation device of Morie ‘176 because the “multiply-accumulate operation device” of Morie ‘176 “may perform a multiply-accumulate operation in which positive loads and negative loads coexist with each other by an analog method” where “the analog circuit has a simpler structure. … the multiply-accumulate operation device independently executes each of multiply-accumulate operations about the positive loads and the negative loads in the same-type circuit respectively, and a movement of each of the electric charges is only in one direction. As a result, decreasing electric energy consumption of each of circuit operations may be realized”, “and the analog circuit has an advantage of not needing the diodes”, as suggested by Morie ‘176. (see, e.g., Morie ‘176, paragraphs 30 and 95).
Although Morie in view of Morie ‘176 substantially teaches the claimed invention Morie in view of Morie ‘176 is not relied on to explicitly teach membrane potential of that neuron.
In the same field, analogous art Zhang teaches membrane potential of that neuron (see, e.g., paragraph 39, “a nerve cell body equivalent circuit [i.e., a neuron] … the capacitor Cm corresponds to the electric capacitance of the cell membrane and the potential difference of the capacitor Cm corresponds to the membrane potential of the cell membrane.” [i.e., the electric potential of a capacitor is the membrane potential, where the cell membrane of a neuron is simulated using the capacitor]).
Morie, Morie ‘176 and Zhang are analogous art because they are each directed to techniques and systems for using and implementing neural networks (see, e.g., Morie, paragraphs 163 and 187, Morie ‘176, paragraph 96 and Zhang, paragraphs 8, 19, 28 and 39).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morie in view of Morie ‘176 to incorporate the teachings of Zhang to provide “a nerve cell body equivalent circuit [i.e., a neuron that] may be constituted by connecting, in parallel between the output terminal and a reference potential terminal, a circuit where a capacitor corresponding to the cell membrane capacitance, a circuit where a power source corresponding to the resting membrane potential” where in the “nerve cell body equivalent circuit … the capacitor Cm corresponds to the electric capacitance of the cell membrane and the potential difference of the capacitor Cm corresponds to the membrane potential of the cell membrane.” (see, e.g., Zhang paragraphs 19 and 39). One of ordinary skill in the art would have been motived to combine Morie in view of Morie ‘176 with Zhang’s nerve cell body equivalent circuit/neuron because the “nerve equivalent circuit, a synapse equivalent circuit and a nerve cell body equivalent circuit … have an advantage that they can faithfully reproduce the electric characteristics in accordance with the physiological functions and the physical structures of nerve cells.” and Zhang’s neuron and synapse/synaptic circuits “can process information and transmit signals on a stable basis” so that “new neural networks and artificial intelligence algorithms can be realized. Furthermore, a large scale parallel arithmetic operation typically involving tens of thousands of additions, subtractions, integrations and proportionality computations can be conducted by means of a single nerve equivalent circuit by simultaneously carrying out those computations”, as suggested by Zhang (see, e.g., Zhang, paragraph 28).
With respect to independent claim 7, claim 7 is substantially similar to claim 1 and therefore is rejected on the same ground as claim 1, discussed above. In particular, claim 7 is a system claim with operations that correspond to the device operations of claim 1.
In addition, Morie further discloses a neural network system comprising a … neural network (see, e.g., paragraphs 61, 63 and 73, “a neural network or the like implemented by the arithmetic logic unit”, “The multiply-accumulate operation device 3 is a multiply-accumulate operation circuit using an analog system” and “By configuring the layer structure of the multiply-accumulate operation devices 3, for example, a multi-layer perceptron type neural network or the like is constructed.” [i.e., a neural network system including a neural network]).
Although Morie substantially discloses the claimed invention and Morie discloses “a neural network is constructed using the arithmetic logic unit 100 using the multiply-accumulate operation devices” and “a method of accumulating an electronic signal (spike timing signal) whose pulse rises at timing corresponding to the signal value x, in a capacitor and calculating the multiply-accumulate signal on the basis of the timing when the accumulated electronic signal has become larger than a threshold voltage” in paragraphs 163 and 187, Morie is not relied on for explicitly disclosing a spiking neural network.
In the same field, analogous art Morie ‘176 teaches a spiking neural network (see, e.g., paragraph 96, “the present invention may be applied to a spiking neural network model showing information by spike pulses. … a multiply-accumulate operation device … that is applicable to a spiking neural network model” [i.e., a spiking neural network]).
Morie and Morie ‘176 are analogous art because they are both directed to techniques and systems for using and implementing spiking neural networks/SNNs (see, e.g., Morie, paragraphs 163 and 187, and Morie ‘176, paragraph 96).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the disclosed system of Morie to incorporate the teachings of Morie ‘176 to provide “a spiking neural network model showing information by spike pulses” by using “a multiply-accumulate operation device … that is applicable to a spiking neural network model” (see, e.g., Morie ‘176 paragraph 96). One of ordinary skill in the art would have been motived to combine the device of Morie with the spiking neural network with the multiply-accumulate operation device of Morie ‘176 because the “multiply-accumulate operation device” of Morie ‘176 “may perform a multiply-accumulate operation in which positive loads and negative loads coexist with each other by an analog method” where “the analog circuit has a simpler structure. … the multiply-accumulate operation device independently executes each of multiply-accumulate operations about the positive loads and the negative loads in the same-type circuit respectively, and a movement of each of the electric charges is only in one direction. As a result, decreasing electric energy consumption of each of circuit operations may be realized”, “and the analog circuit has an advantage of not needing the diodes”, as suggested by Morie ‘176. (see, e.g., Morie ‘176, paragraphs 30 and 95).
With respect to independent claim 9, claim 9 is substantially similar to claim 1 and therefore is rejected on the same ground as claim 1, discussed above. In particular, claim 9 is a method claim with steps that correspond to the device operations of claim 1.
In addition, Morie further discloses a computation method of controlling a computing device including an accumulation phase and a decoding phase9 of a … neural network (see, e.g., FIGs. 11 and 12 – depicting a multiply-accumulate operation device and a calculation/adding of current by a multiply-accumulate signal by the multiply-accumulate operation device – accumulation and decoding phases, and paragraphs 31, “A multiply-accumulate operation method” and 61, 63, 68, 73, 186 and 197, “a neural network or the like implemented by the arithmetic logic unit”, “The multiply-accumulate operation device 3 is a multiply-accumulate operation circuit using an analog system”, “By configuring the layer structure of the multiply-accumulate operation devices 3, for example, a multi-layer perceptron type neural network or the like is constructed.”, “In a neural network or the like, a method”, “output result of the multiply-accumulate operation are converted into the pulse timing within the pulse output period T" and “the input period T shown in FIG. 12, a switch 216a is turned OFF and a switch 216b is turned ON. Then, an input signal is input within the input period T" [i.e., a method of controlling a computing device including phases of a neural network where the "input period T" corresponds to the "accumulation phase” and the output pulse timing of FIG. 12 is determined based on the voltage held by the charge accumulated in the capacitor 213 during the "input period" and a threshold value θ, the "output period" corresponds to the "decoding phase]).
Although Morie substantially discloses the claimed invention and Morie discloses “a neural network is constructed using the arithmetic logic unit 100 using the multiply-accumulate operation devices” and “a method of accumulating an electronic signal (spike timing signal) whose pulse rises at timing corresponding to the signal value x, in a capacitor and calculating the multiply-accumulate signal on the basis of the timing when the accumulated electronic signal has become larger than a threshold voltage” in paragraphs 163 and 187, Morie is not relied on for explicitly disclosing a spiking neural network.
In the same field, analogous art Morie ‘176 teaches a spiking neural network (see, e.g., paragraph 96, “the present invention may be applied to a spiking neural network model showing information by spike pulses. … a multiply-accumulate operation device … that is applicable to a spiking neural network model” [i.e., a spiking neural network]).
Morie and Morie ‘176 are analogous art because they are both directed to techniques and systems for using and implementing spiking neural networks/SNNs (see, e.g., Morie, paragraphs 163 and 187, and Morie ‘176, paragraph 96).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the disclosed system of Morie to incorporate the teachings of Morie ‘176 to provide “a spiking neural network model showing information by spike pulses” by using “a multiply-accumulate operation device … that is applicable to a spiking neural network model” (see, e.g., Morie ‘176 paragraph 96). One of ordinary skill in the art would have been motived to combine the device of Morie with the spiking neural network with the multiply-accumulate operation device of Morie ‘176 because the “multiply-accumulate operation device” of Morie ‘176 “may perform a multiply-accumulate operation in which positive loads and negative loads coexist with each other by an analog method” where “the analog circuit has a simpler structure. … the multiply-accumulate operation device independently executes each of multiply-accumulate operations about the positive loads and the negative loads in the same-type circuit respectively, and a movement of each of the electric charges is only in one direction. As a result, decreasing electric energy consumption of each of circuit operations may be realized”, “and the analog circuit has an advantage of not needing the diodes”, as suggested by Morie ‘176. (see, e.g., Morie ‘176, paragraphs 30 and 95).
Conclusion
The claims have been searched insofar as they can be understood. The prior art made of record, listed on form PTO-892, and not relied upon, is considered pertinent to applicant's disclosure; and all references listed generally relate to techniques, methods and systems for implementing and using neural networks such as spiking neural networks/SNNs for machine learning tasks.
For example, Kendall et al. (U.S. Patent Application Pub. No. 2023/0297839 A1, hereinafter “Kendall”) discloses using a "memristor" [i.e., a variable resistor] as an "artificial synapse with a weight equivalent to its conductance” “In a memristive neural network” and changing the conductance of the memristor to achieve “The goal of learning in such a memristive neural network is to change the conductances of the memristors in order to minimize some cost or error function.” (see, paragraphs 2-5 and 23-24).
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the reference cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111 (c).
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/RANDALL K. BALDWIN/Primary Examiner, Art Unit 2125
1 FIG. 4 includes a “CONT” element with reference character 200, which is not included in the description of this Figure. Examiner notes that with reference to “FIGS. 8A through 8D” paragraph 118 of the specification states “the number of neuron models 100 in the first and second layers was set to 200 each”. However, this “200” describes a number of models for “The results of the experiments using the neural network device 10, shown in FIGS. 8A through 8D” (see, paragraph 117) and not FIG. 4.
2 References to the specification herein are to the specification as amended in the 2/20/2024 preliminary amendment.
3 As noted above, FIG. 4 includes reference character 200, which is not included in the description of this Figure.
4 As discussed in the section 112(b) rejection of this claim above, the “preceding neuron” recitation is also indefinite and unclear.
5 As indicated above in the section 112(b) rejections of this claim, the above-listed phases have been interpreted as any combination of software and/or hardware capable of performing the claimed functions.
6 As indicated above in the section 112(b) rejections of this claim, the above-listed phases have been interpreted as any combination of software and/or hardware capable of performing the claimed functions.
7 As indicated above in the section 112(b) rejections of this claim, “a voltage resulting from the addition” has been interpreted as any voltage value or amount corresponding to the “accumulation phase that adds currents”.
8 As indicated above in the section 112(b) rejections of this claim, “the current that flows into or out of an own neuron” has been interpreted as any current value or amount (i.e., a number of amps or amperage) that flows into or out of a neuron.
9 As indicated above in the section 112(b) rejections of this claim, the above-listed phases have been interpreted as any combination of software and/or hardware capable of performing the claimed functions.
Prosecution Insights