NON-FINAL REJECTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), fourth paragraph:
Subject to the [fifth paragraph of 35 U.S.C. 112 (pre-AIA )], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 13 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 13 is not further limiting claim 1 since all the limitation are already in claim 1. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 13 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Park et al. (US 2006/119419 A1 cited by Applicants, “Park”).
Regarding Claim 1, Park teaches a voltage boost circuit (“DC conversion device”, fig.4) comprising: an input node (contact point between 130 and Vr/Vd) configured to receive, from a reference signal source (implicitly present in Vref), a reference signal defined by a reference voltage (Vr); a voltage booster (charge pump circuit 110) configured to boost an input voltage (Vdd) to deliver an output voltage (Vout); a voltage divider (voltage distribution unit 120) configured to divide the output voltage (Vout) into a fractional voltage (Vd) to generate a fractional voltage signal defined by the fractional voltage (Voltage Distribution unit 120 outputs Vd which may be considered as the fractional voltage Vd); a comparator unit (Comparing Unit 130) configured to compare the reference signal (Vr) and the fractional voltage signal (Vd) with each other to generate a comparison signal (Vc); and a voltage boost controller (clock signal generation unit 140) configured to control, in accordance with the comparison signal, operation of the voltage booster to narrow a difference between the reference voltage (Vr) and the fractional voltage (Vd) ([0050]-[0055]; Fig.4. Para. [0053] discloses that the comparing unit 130 receives the fractional/distribution voltage Vd and a reference voltage Vr and compares the reference voltage Vr with the fractional/distribution voltage Vd and generates a comparison signal Vc corresponding to the comparison result to the clock signal generator (140). Utilizing the element (140), one of ordinary skill in the art may operate of the voltage booster (110) to narrow a difference between the reference voltage (Vr) and the fractional voltage (Vd) whenever required. Thus, the limitation is implicitly taught by Park.).
Regarding Claim 13, the voltage boost circuit of claim 1 is taught by Park.
Park further teaches the voltage boost circuit further comprising the reference signal source (implicitly present in Vref of fig.4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and further in view of Otaka (JP 2006074925 A, cited by the applicants).
Regarding Claim 2, the voltage boost circuit of claim 1 is taught by Park.
Park does not explicitly teach wherein the voltage booster includes: an input port onfigured to receive the input voltage; an output port configured to deliver the output voltage; a first switch, a second switch, and a third switch, which are connected in series in this order between the input port and the output port such that the first switch is located closer to the input port than the second switch or the third switch; a first capacitive element having a first terminal and a second terminal, the first terminal of the first capacitive element being connected to a connection node between the first switch and the second switch, the second terminal of the first capacitive element being connected to the voltage boost controller; and a second capacitive element having a first terminal and a second terminal, the first terminal of the second capacitive element being connected to a connection node between the second switch and the third switch, the second terminal of the second capacitive element being connected to the voltage boost controller, and the voltage boost controller is configured to control, in accordance with the comparison signal, ON/OFF states of the first switch, the second switch, and the third switch, a potential at the second terminal of the first capacitive element, and a potential at the second terminal of the second capacitive element.
However, Otaka teaches a charge pump circuit mounted on a portable device [0001] wherein the voltage booster (Fig.2) includes: an input port configured to receive the input voltage (shown in fig.2 and discussed in [0007]); an output port configured to deliver the output voltage shown in fig.2 and discussed in [0007]); a first switch (1-1), a second switch, (1-2) and a third switch (1-3), which are connected in series in this order between the input port and the output port such that the first switch is located closer to the input port than the second switch or the third switch (shown in fig.2); a first capacitive element (3-1) having a first terminal and a second terminal, the first terminal of the first capacitive element being connected to a connection node between the first switch and the second switch, the second terminal of the first capacitive element being connected to the voltage boost controller (shown in fig.2); and a second capacitive element (3-2) having a first terminal and a second terminal, the first terminal of the second capacitive element being connected to a connection node between the second switch and the third switch, the second terminal of the second capacitive element being connected to the voltage boost controller (shown in fig.2), and the voltage boost controller is configured to control, in accordance with the comparison signal, ON/OFF states of the first switch, the second switch, and the third switch, a potential at the second terminal of the first capacitive element, and a potential at the second terminal of the second capacitive element (shown in fig.2 and discussed in [0007]-[0009]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s circuit by incorporating Otaka teaching regarding charge pump circuit since this is known structure which would boost the power supply voltage as requirement.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Otaka as applied to claim 2 above, and further in view of Nakai (JP 2005117773 A, cited by the applicants).
Regarding Claim 3, the voltage boost circuit of claim 2 is taught by Park in view of Otaka.
Modified Park does not teach wherein at least one of the first capacitive element or the second capacitive element is a variable capacitance capacitive element.
However, Nakai teaches a semiconductor device, and more particularly to a booster circuit, particularly a booster circuit used in a flash memory [0001], wherein at least one of the first capacitive element or the second capacitive element is a variable capacitance capacitive element ([0128]-[0130], fig.15-16 disclose regarding using variable capacitance circuit 312 in a voltage boosting unit or voltage boosting circuit 310).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s circuit with the teaching of Nakai since this is known in the art to use variable capacitance circuit in a voltage boosting unit or voltage boosting circuit.
Regarding Claim 4, the voltage boost circuit of claim 3 is taught by Park in view of Otaka and Nakai.
Nakai further teaches wherein each of the first capacitive element and the second capacitive element is a variable capacitance capacitive element ([0128]-[0130], fig.15-16 disclose regarding using variable capacitance circuit 312 in a voltage boosting unit or voltage boosting circuit 310).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and further in view of Suzuki (5,173,847, cited by the applicants).
Regarding Claim 10, the voltage boost circuit of claim 1 is taught by Park.
Park does not explicitly teach wherein the reference signal is a sinusoidal wave signal in which the reference voltage varies in a sinusoidal wave.
However, Suzuki teaches a power supply device having a transformer including primary and secondary windings, for generating in said secondary winding a high voltage output corresponding to power supplied to said primary winding [Abstract] wherein the reference signal is a sinusoidal wave signal in which the reference voltage varies in a sinusoidal wave (col.10; lines 46-50, fig.18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s circuit with the teaching of Suzuki since this is known in the art to use sinusoidal wave as a reference signal in a voltage boosting unit or voltage boosting circuit.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and further in view of Miyazaki (US 2010/0207929 Al, cited by the applicants).
Regarding Claim 11, the voltage boost circuit of claim 1 is taught by Park.
Park does not explicitly teach wherein the voltage divider includes: a first port connected to the output port of the voltage booster, the output voltage being delivered through the output port; a second port configured to output the fractional voltage signal therethrough; and a third port connected to a reference potential node, a route connecting the first port to the third port includes: a first path connecting the first port to the second port; and a second path connecting the second port to the third port, the fractional voltage signal is based on a resistance ratio that is a ratio between a resistance value of the first path and a resistance value of the second path, and the resistance ratio of the voltage divider is variable.
However, Miyazaki teaches in (Fig.1-2,6A) a booster circuit (voltage boosting circuit) wherein the voltage divider (voltage dividing circuit unit 24) includes: a first port connected to the output port of the voltage booster (charge pump 10), the output voltage being delivered through the output port (VOUT); a second port configured to output the fractional voltage signal therethrough; and a third port connected to a reference potential node, a route connecting the first port to the third port includes: a first path connecting the first port to the second port; and a second path connecting the second port to the third port, the fractional voltage signal is based on a resistance ratio that is a ratio between a resistance value of the first path and a resistance value of the second path, and the resistance ratio of the voltage divider is variable (([0003]-[0022], [0052], fig.1-2, 6A) disclose a voltage boosting circuit (voltage boosting circuit) comprising: a reference signal source (reference voltage source 220); an input unit (obvious) that receives a reference signal specified by a reference voltage from the reference signal source; a voltage boosting unit (charge pump 10) that boosts an input voltage (VIN) and outputs an output voltage (VOUT); a voltage dividing unit (voltage dividing circuit unit 24) that generates a voltage division signal (VFB) specified by a divided voltage obtained by dividing the output voltage; a comparison unit (comparison circuit unit 21) that generates a comparison signal (EN) by comparing the reference signal with the voltage division signal; and a voltage boosting control unit (logic circuit unit 30) that controls the operation of the voltage boosting unit such that the difference between the reference voltage and the divided voltage decreases, on the basis of the comparison signal. The voltage dividing unit (fig. 6A) comprises a variable resistor (variable resistor 243), and the resistance ratio is variable).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s circuit with the teaching of Miyazaki since these are known connections which would provide a power source having a higher efficiency and lower power consumption being used more frequently for a built-in power source.
Regarding Claim 12, the voltage boost circuit of claim 11 is taught by Mark in view of Miyazaki.
Miyazaki further teaches wherein the voltage divider further includes a variable resistor provided on the second path (variable resistor 243).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s circuit with the teaching of Miyazaki since this would provide a power source having a higher efficiency and lower power consumption being used more frequently for a built-in power source.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and further in view of Fukuda (JP 2014225953 A, cited by the applicants).
Regarding Claim 14, the voltage boost circuit of claim 1 is taught by Park.
Park does not explicitly teach a failure diagnosis circuit configured to determine, by comparing the fractional voltage signal with a predetermined diagnosis signal, whether any failure has occurred in the voltage boost circuit.
However, Fukuda discloses in (fig.1) a failure diagnosis circuit (diagnosis circuit 60) that diagnoses occurrence of a failure (open failure, short failure) in a voltage boosting circuit (in particular, at capacitor 20) on the basis of comparison between the output voltage (Vout) and a predetermined diagnosis signal (the output voltage of multiplexer 50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s circuit with the teaching of Fukuda since this would detect the amount of change in the output voltage of the capacitor and determines whether or not the capacitor is abnormal based on the amount of change detected.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, and further in view of Okami (JP 2015137883 A, cited by the applicants).
Regarding Claim 15, a sensor device comprising: the voltage boost circuit of claim 1 is taught by Park.
Park does not explicitly teach an inertial sensor to which the output voltage is applied from the voltage booster of the voltage boost circuit.
Okami teaches teach a CV conversion circuit that outputs a voltage corresponding to a change in capacitance wherein an inertial sensor [0002] to which the output voltage is applied from the voltage booster of the voltage boost circuit [0002].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s circuit with the teaching of Okami since this would ensure that the vibrator self-oscillates properly.
Allowable Subject Matter
Claims 5-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
With regard to Claim 5, the prior arts of the record do not teach or fairly suggest a voltage boost circuit comprising, in combination with the other recited elements, a capacitance controller configured to control capacitance of the variable capacitance capacitive element, wherein the capacitance controller is configured to control the capacitance in response to the reference signal.
Claims 6-9 are allowed by virtue of their dependence from Claim 5.
Conclusion
The following prior arts made of record and not relied upon, are considered pertinent to applicant's disclosure:
Usami (US 8,897,043 B2) teaches a power conversion apparatus includes a converter and a controller. A converter receives an AC power as an input, and outputs a DC voltage by turning on and off a first switching element which operates when the AC power is positive, and a second switching element which operates when the AC power is negative. A controller receives an AC input voltage and alternating input current to the converter, and a DC output voltage from the converter, as an input, determines a pulse width of a first pulse signal to turn on the first switching element and a pulse width of a second pulse signal to turn on the second switching element, and outputs the first pulse signal and second pulse signal to the converter [Abstract].
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUMAN NATH whose telephone number is (571)270-1443. The examiner can normally be reached on M to F 9:00 am to 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOHN BREENE can be reached on 571-272-4107. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUMAN K NATH/Primary Examiner, Art Unit 2855