DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 11, 14, 18, 20, and 24 are objected to because of the following informalities:
Claim 11 line 2 recites “has a first transfer unit is configured”. The word “is” should be deleted.
Claim 14 line 3 recites “has a first discharge unit is configured”. The word “is” should be deleted.
Claim 20 line 2 recites “has a conversion unit is configured”. The word “is” should be deleted.
Claim 24 line 2 recites “has a transfer unit is configured”. The word “is” should be deleted.
Appropriate correction is required.
Applicant is advised that should claim 18 be found allowable, claim 29 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 and 10-29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shishido (U.S. Pub. No. 20200366860).
Regarding claim 1, Shishido discloses:
An imaging element, comprising:
a first semiconductor substrate having a plurality of pixels arranged in a row direction (two-dimensionally arranged pixel array (array with rows and columns) 310 is provided on a first substrate 101, par. 133, 137, 142, and Figs. 1 and 4); and
a second semiconductor substrate (second substrate 102, where the constant current source circuits 330, the column signal processing circuits 340, the vertical scanning circuit 350, and the horizontal signal reading circuit 360, which are included in the peripheral circuitry, are provided on a second substrate 102, and bias control circuits 320, the constant current source circuits 330, and the column signal processing circuits 340 are arranged for the respective columns, par. 142-143 and Figs. 1 and 4) having a first load current source configured to supply a current to a first pixel among the plurality of pixels (constant current source 434 of constant current source circuit 330, where constant current source circuit 330 supplies current to the amplifying transistor 4121A of pixel 411A (or amplifying transistor 4121B of pixel 411B) through the output signal line 314, par. 142-143, 156, 159, 166, 167, and Figs. 1 and 4), a second load current source configured to supply a current to a second pixel among the plurality of pixels (being connected to another output signal line 314 (another column) of pixel array 310, constant current source 434 of constant current source circuit 330, where constant current source circuit 330 supplies current to the amplifying transistor 4121A of pixel 411A (or amplifying transistor 4121B of pixel 411B) through the output signal line 314, par. 142-143, 156, 159, 166, 167, and Figs. 1 and 4), a first pixel control unit configured to control supply of the current to the first pixel by the first load current source (signal line that provides control signal S1 to switching element 432 (or signal line that provides control signal S1b to switch element 431), where control signal S1 is set to a high level to put the switching element 432 in the constant current source circuit 330 into an on state and the amplifying transistor 4121 of pixel 411 and the constant current source 434 form a source follower circuit, where system controller 603 controls the entire camera system including the part providing the control signals, par. 173, 175, 400, and Fig. 4), and a second pixel control unit configured to control supply of the current to the second pixel by the second load current source (being connected to another output signal line 314 (another column) of pixel array 310, signal line that provides control signal S1 to switching element 432 (or signal line that provides control signal S1b to switch element 431), where control signal S1 is set to a high level to put the switching element 432 in the constant current source circuit 330 into an on state and the amplifying transistor 4121 of pixel 411 and the constant current source 434 form a source follower circuit, where system controller 603 controls the entire camera system including the part providing the control signals, par. 173, 175, 400, and Fig. 4).
Regarding claim 2, Shishido further discloses:
first pixel control unit is configured to control a connection between the first pixel and the first load current source (signal line that provides control signal S1 to switching element 432 (or signal line that provides control signal S1b to switch element 431), where control signal S1 is set to a high level to put the switching element 432 in the constant current source circuit 330 into an on state and the amplifying transistor 4121A and the constant current source 434 form a source follower circuit, where system controller 603 controls the entire camera system, par. 173, 175, 400, and Fig. 4), and
wherein the second pixel control unit is configured to control a connection between the second pixel and the second load current source (being connected to another output signal line 314 (another column) of pixel array 310, signal line that provides control signal S1 to switching element 432 (or signal line that provides control signal S1b to switch element 431), where control signal S1 is set to a high level to put the switching element 432 in the constant current source circuit 330 into an on state and the amplifying transistor 4121A and the constant current source 434 form a source follower circuit, where system controller 603 controls the entire camera system, par. 173, 175, 400, and Fig. 4).
Regarding claim 3, Shishido further discloses:
a first adjustment unit configured to adjust the current supplied to the first pixel by the first load current source (switching element 432 that when put into an on state, using control signal S1, causes the amplifying transistor 4121A and the constant current source 434 form a source follower circuit, par. 173, 175, 400, and Fig. 4); and
a second adjustment unit configured to adjust the current supplied to the second pixel by the second load current source (being connected to another output signal line 314 (another column) of pixel array 310, switching element 432 that when put into an on state, using control signal S1, causes the amplifying transistor 4121A and the constant current source 434 form a source follower circuit, par. 173, 175, 400, and Fig. 4),
wherein the first pixel control unit is configured to control the first adjustment unit (control signal S1 is set to a high or low level to put the switching element 432 in the constant current source circuit 330 into an on state, par. 173, 175, 400, and Fig. 4), and
wherein the second pixel control unit is configured to control the second adjustment unit (being connected to another output signal line 314 (another column) of pixel array 310, control signal S1 is set to a high or low level to put the switching element 432 in the constant current source circuit 330 into an on state, par. 173, 175, 400, and Fig. 4).
Regarding claim 4, Shishido further discloses:
the first adjustment unit is configured to adjust the current supplied to the first pixel by the first load current source on the basis of a signal from the first pixel control unit (when put into an on state, using control signal S1, switching element 432 causes the amplifying transistor 4121A and the constant current source 434 form a source follower circuit, par. 173, 175, 400, and Fig. 4), and
wherein the second adjustment unit is configured to adjust the current supplied to the second pixel by the second load current source on the basis of a signal from the second pixel control unit (being connected to another output signal line 314 (another column) of pixel array 310, when put into an on state, using control signal S1, switching element 432 causes the amplifying transistor 4121A and the constant current source 434 form a source follower circuit, par. 173, 175, 400, and Fig. 4).
Regarding claim 5, Shishido further discloses:
first adjustment unit is connected to the first pixel and the first load current source (switching element 432 is connected to amplifying transistor 4121A of pixel 411A and constant current source 434, par. 173, 175, 400, and Fig. 4), and
wherein the second adjustment unit is connected to the second pixel and the second load current source (being connected to another output signal line 314 (another column) of pixel array 310, switching element 432 is connected to amplifying transistor 4121A of pixel 411A and constant current source 434, par. 173, 175, 400, and Fig. 4).
Regarding claim 6, Shishido further discloses:
a first conversion unit configured to convert a first signal read from the first pixel to a digital signal (column signal processing circuit 340, where pixels 311 arranged in each column are electrically connected to the corresponding column signal processing circuit 340 through the corresponding output signal line 314, and column signal processing circuit 340 performs analog-to-digital conversion, par. 140); and
a second conversion unit configured to convert a second signal read from the second pixel to a digital signal (being connected to another output signal line 314 (another column) of pixel array 310, column signal processing circuit 340, where pixels 311 arranged in each column are electrically connected to the corresponding column signal processing circuit 340 through the corresponding output signal line 314, and column signal processing circuit 340 performs analog-to-digital conversion, par. 140).
Regarding claim 7, Shishido further discloses:
wherein the first pixel control unit is configured to control the supply of the current to the first conversion unit (when control signal S1 is set to a high level to put the switching element 432 in the constant current source circuit 330 into an on state the amplifying transistor 4121A and the constant current source 434 form a source follower circuit through output signal line 314, where output signal line 314 is also connected to column signal processing circuit 340, par. 173, 175, 400, and Fig. 4), and
wherein the second pixel control unit is configured to control the supply of the current to the second conversion unit (being connected to another output signal line 314 (another column) of pixel array 310, when control signal S1 is set to a high level to put the switching element 432 in the constant current source circuit 330 into an on state the amplifying transistor 4121A and the constant current source 434 form a source follower circuit through output signal line 314, where output signal line 314 is also connected to column signal processing circuit 340, par. 173, 175, 400, and Fig. 4).
Regarding claim 10, Shishido further discloses:
the first pixel has a first photoelectric conversion unit configured to convert light to an electric charge (photoelectric converter 4112A detects light and generates charge, par. 158),
wherein the second pixel has a second photoelectric conversion unit configured to convert light to an electric charge (in another column, photoelectric converter 4112A detects light and generates charge, par. 158),
wherein the first pixel control unit is configured to control the supply of the current to the first pixel on the basis of a control signal that controls an accumulation time over which the electric charge obtained by conversion by the first photoelectric conversion unit accumulates (in the Signal-Charge Reading Period (after accumulation) at time t1 the voltage in the selection control signal line Vsel(A) is set to a high level to turn on the selecting transistor 4122A, control signal S1 is set to a high level to put the switching element 432 in the constant current source circuit 330 into an on state and the amplifying transistor 4121A and the constant current source 434 form a source follower circuit, and the potential in the output signal line 314 reaches a voltage VSIG(A) corresponding to the signal charge accumulated in the charge accumulation region FD, par. 175), and
wherein the second pixel control unit is configured to control the supply of the current to the second pixel on the basis of a control signal that controls an accumulation time over which the electric charge obtained by conversion by the second photoelectric conversion unit accumulates (in another column, in the Signal-Charge Reading Period (after accumulation) at time t1 the voltage in the selection control signal line Vsel(A) is set to a high level to turn on the selecting transistor 4122A, control signal S1 is set to a high level to put the switching element 432 in the constant current source circuit 330 into an on state and the amplifying transistor 4121A and the constant current source 434 form a source follower circuit, and the potential in the output signal line 314 reaches a voltage VSIG(A) corresponding to the signal charge accumulated in the charge accumulation region FD, par. 175).
Regarding claim 11, Shishido further discloses:
the first pixel has a first transfer unit is configured to transfer the electric charge obtained by conversion by the first photoelectric conversion unit (transfer transistor TX is connected to the photoelectric converter 4112A which allows signal charge generated in the photoelectric converter 4112A to be transferred to a charge accumulation region FD, par. 150, 377, and Fig. 52),
wherein the second pixel has a second transfer unit configured to transfer the electric charge obtained by conversion by the second photoelectric conversion unit (in another column, transfer transistor TX is connected to the photoelectric converter 4112A which allows signal charge generated in the photoelectric converter 4112A to be transferred to a charge accumulation region FD, par. 150, 377, and Fig. 52),
wherein the first pixel control unit is configured to control the supply of the current to the first pixel on the basis of a control signal that controls the first transfer unit (when charge accumulation region FD accumulates signal charge generated by the photoelectric converter 4112A (necessitating that the transfer transistor TX is turned on using a signal applied to the gate), at time t1 the voltage in the selection control signal line Vsel(A) is set to a high level to turn on the selecting transistor 4122A, control signal S1 is set to a high level to put the switching element 432 in the constant current source circuit 330 into an on state and the amplifying transistor 4121A and the constant current source 434 form a source follower circuit, and the potential in the output signal line 314 reaches a voltage VSIG(A) corresponding to the signal charge accumulated in the charge accumulation region FD, par. 150, 175, and 377), and
wherein the second pixel control unit is configured to control the supply of the current to the second pixel on the basis of a control signal that controls the second transfer unit (in another column, when charge accumulation region FD accumulates signal charge generated by the photoelectric converter 4112A (necessitating that the transfer transistor TX is turned on using a signal applied to the gate), at time t1 the voltage in the selection control signal line Vsel(A) is set to a high level to turn on the selecting transistor 4122A, control signal S1 is set to a high level to put the switching element 432 in the constant current source circuit 330 into an on state and the amplifying transistor 4121A and the constant current source 434 form a source follower circuit, and the potential in the output signal line 314 reaches a voltage VSIG(A) corresponding to the signal charge accumulated in the charge accumulation region FD, par. 150, 175, and 377).
Regarding claim 12, Shishido further discloses:
the first transfer unit is connected to a first transfer control line to which a first transfer control signal for transferring the electric charge obtained by conversion by the first photoelectric conversion unit is outputted (transfer transistor TX is connected to the photoelectric converter 4112A which allows signal charge generated in the photoelectric converter 4112A to be transferred to a charge accumulation region FD, where a gate of the transistor controls the connection between the photoelectric converter and charge accumulation region FD, par. 150, 377, and Fig. 52), and
wherein the second transfer unit is connected to a second transfer control line to which a second transfer control signal for transferring the electric charge obtained by conversion by the second photoelectric conversion unit is outputted (in another column, transfer transistor TX is connected to the photoelectric converter 4112A which allows signal charge generated in the photoelectric converter 4112A to be transferred to a charge accumulation region FD, where a gate of the transistor controls the connection between the photoelectric converter and charge accumulation region FD, par. 150, 377, and Fig. 52).
Regarding claim 13, Shishido further discloses:
first transfer control signal is outputted from the first pixel control unit (part of system controller 603 providing the control signals, par. 173, 175, 400, and Fig. 4), and
wherein the second transfer control signal is outputted from the second pixel control unit (part of system controller 603 providing the control signals, par. 173, 175, 400, and Fig. 4).
Regarding claim 14, Shishido further discloses:
first pixel has a first discharge unit is configured to discharge the electric charge of the first photoelectric conversion unit (using band control transistor 4111A, at time t2, the voltage in the band control signal line Vfb(A) is set to a high level to put the band control transistor 4111A into an on state, the control signal R1 is set to a high level, and as a result, the switching element 421 in the bias control circuit 320 enters an on state, so that the voltage of the voltage source Va1 is applied to the other of the source and the drain of the amplifying transistor 4121A, the switching element 431 in the constant current source circuit 330 enters an on state, so that the constant current source 433 is connected to the one of the source and the drain of the selecting transistor 4122A, and the selecting transistor 4122A, the amplifying transistor 4121A, and the constant current source 433 form a source-grounded amplifier circuit, and since the band control transistor 4111A is in the on state, input/output ends of the source-grounded amplifier circuit enter a short-circuited state, and the voltage at the charge accumulation region FD is reset to the reset voltage VRST, par. 177),
wherein the second pixel has a second discharge unit configured to discharge the electric charge of the second photoelectric conversion unit (in another column, using band control transistor 4111A, at time t2, the voltage in the band control signal line Vfb(A) is set to a high level to put the band control transistor 4111A into an on state, the control signal R1 is set to a high level, and as a result, the switching element 421 in the bias control circuit 320 enters an on state, so that the voltage of the voltage source Va1 is applied to the other of the source and the drain of the amplifying transistor 4121A, the switching element 431 in the constant current source circuit 330 enters an on state, so that the constant current source 433 is connected to the one of the source and the drain of the selecting transistor 4122A, and the selecting transistor 4122A, the amplifying transistor 4121A, and the constant current source 433 form a source-grounded amplifier circuit, and since the band control transistor 4111A is in the on state, input/output ends of the source-grounded amplifier circuit enter a short-circuited state, and the voltage at the charge accumulation region FD is reset to the reset voltage VRST, par. 177),
wherein the first pixel control unit is configured to control the supply of the current to the first pixel on the basis of a control signal that controls the first discharge unit (part of system controller 603 providing the control signals, par. 173, 175, 400, and Fig. 4), and
wherein the second pixel control unit is configured to control the supply of the current to the second pixel on the basis of a control signal that controls the second discharge unit (in another column, part of system controller 603 providing the control signals, par. 173, 175, 400, and Fig. 4).
Regarding claim 15, Shishido further discloses:
the first discharge unit is connected to a first discharge control line to which a first discharge control signal for discharging the electric charge of the first photoelectric conversion unit is outputted (band control transistor 4111A has signal Vfb input at the transistor gate for controlling the transistor, par. 177 and Fig. 4), and
wherein the second discharge unit is connected to a second discharge control line to which a second discharge control signal for discharging the electric charge of the second photoelectric conversion unit is outputted (in another column, band control transistor 4111A has signal Vfb input at the transistor gate for controlling the transistor, par. 177 and Fig. 4).
Regarding claim 16, Shishido further discloses:
the first discharge control signal is outputted from the first pixel control unit (part of system controller 603 providing the control signals, par. 173, 175, 400, and Fig. 4), and
wherein the second discharge control signal is outputted from the second pixel control unit (in another column, part of system controller 603 providing the control signals, par. 173, 175, 400, and Fig. 4).
Regarding claim 17, Shishido further discloses:
first pixel is disposed in a first pixel block in the first semiconductor substrate (a pixel in a column of the two-dimensionally arranged pixel array (array with rows and columns) 310 is provided on a first substrate 101, par. 133, 137, 142, and Figs. 1 and 4),
wherein the second pixel is disposed in a second pixel block in the first semiconductor substrate (in another column a pixel of the two-dimensionally arranged pixel array (array with rows and columns) 310 is provided on a first substrate 101, par. 133, 137, 142, and Figs. 1 and 4),
wherein the first pixel control unit is disposed in a first control block in the second semiconductor substrate (signal line that provides control signal S1 to switching element 432 (or signal line that provides control signal S1b to switch element 431) within constant current source circuit 330 is in second substrate 102, par. 173, 175, 400, and Fig. 4),
wherein the second pixel control unit is disposed in a second control block in the second semiconductor substrate (in another column, signal line that provides control signal S1 to switching element 432 (or signal line that provides control signal S1b to switch element 431) within constant current source circuit 330 is in second substrate 102, par. 173, 175, 400, and Fig. 4),
wherein the first pixel block and the first control block oppose each other (in a same column pixel 411 and constant current source circuit 330 are correspondingly arranged, Fig. 4), and
wherein the second pixel block and the second control block oppose each other (in another column, pixel 411 and constant current source circuit 330 are correspondingly arranged, Fig. 4).
Regarding claim 18, Shishido further discloses:
An imaging device, comprising:
the imaging element according to claim 1 (imaging device 100, par. 131, Figs. 1, 2, and 4, and see rejection of claim 1).
Regarding claim 19, Shishido discloses: An imaging element, comprising:
a first semiconductor substrate having a plurality of pixel blocks including at least one pixel (two-dimensionally arranged pixel array (array with rows and columns) 310 with pixels 411 (411A, 411B) is provided on a first substrate 101, par. 133, 137, 142, and Figs. 1 and 4); and
a second semiconductor substrate (second substrate 102, where the constant current source circuits 330, the column signal processing circuits 340, the vertical scanning circuit 350, and the horizontal signal reading circuit 360, which are included in the peripheral circuitry, are provided on a second substrate 102, and bias control circuits 320, the constant current source circuits 330, and the column signal processing circuits 340 are arranged for the respective columns, par. 142-143 and Figs. 1 and 4) having a control block disposed for each of the pixel blocks, wherein the control block has a pixel control unit is configured to control a load current source that supplies a current to the pixel included in a corresponding pixel block among the plurality of pixel blocks (in each column, signal line that provides control signal S1 to switching element 432 (or signal line that provides control signal S1b to switch element 431), where control signal S1 is set to a high level to put the switching element 432 in the constant current source circuit 330 into an on state and the amplifying transistor 4121A and the constant current source 434 form a source follower circuit, where system controller 603 controls the entire camera system including the part providing the control signals, par. 173, 175, 400, and Fig. 4).
Regarding claim 20, see the rejection of claims 19 and 6 and note that the limitations of claim 20 were shown.
Regarding claim 21, Shishido further discloses:
the second semiconductor substrate has a conversion unit configured to convert the signal read from the pixel to a digital signal (column signal processing circuit 340 in each column, where pixels 311 arranged in each column are electrically connected to the corresponding column signal processing circuit 340 through the corresponding output signal line 314, and column signal processing circuit 340 performs analog-to-digital conversion, par. 140), and
wherein the conversion unit is disposed on the second semiconductor substrate outside of a control circuit unit in which the plurality of control blocks are disposed (column signal processing circuit 340 is outside of the signal line that provides control signal S1b to switch element 431, Fig. 4).
Regarding claim 22, see the rejection of claims 19 and 2 and note that the limitations of claim 22 were shown.
Regarding claim 23, see the rejection of claims 19 and 10 and note that the limitations of claim 23 were shown.
Regarding claim 24, see the rejection of claims 23 and 11 and note that the limitations of claim 24 were shown.
Regarding claim 25, see the rejection of claims 24 and 12 and note that the limitations of claim 25 were shown.
Regarding claim 26, see the rejection of claims 23 and 14 and note that the limitations of claim 26 were shown.
Regarding claim 27, see the rejection of claims 26 and 15 and note that the limitations of claim 27 were shown.
Regarding claim 28, see the rejection of claims 27 and 16 and note that the limitations of claim 28 were shown.
Regarding claim 29, Shishido further discloses:
An imaging device, comprising:
the imaging element according to claim 1 (imaging device 100, par. 131, Figs. 1, 2, and 4, and see rejection of claim 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shishido (U.S. Pub. No. 20200366860) in view of Kurose (U.S. Pub. No. 20150189214).
Regarding claim 8, Shishido further discloses the first conversion unit has a first input to which the first signal is inputted (column signal processing circuit 340 is electrically connected through the corresponding output signal line 314 to the pixels 311, par. 140, 167, and Fig. 4), wherein the second conversion unit has a second input to which the second signal is inputted (in another column, column signal processing circuit 340 is electrically connected through the corresponding output signal line 314 to the pixels 311, par. 140, 167, and Fig. 4), wherein the first pixel control unit is configured to control the supply of the current to the first input (part of system controller 603 providing the control signals, par. 173, 175, 400, and Fig. 4), and wherein the second pixel control unit is configured to control the supply of the current to the second input (in another column, part of system controller 603 providing the control signals, par. 173, 175, 400, and Fig. 4). Shishido is silent with regards to the input being a comparator. Kurose discloses this in par. 91-93 and Fig. 2 where comparator (COMP) 51 takes the analog signal (the signal level V.sub.Sig and the reset level V.sub.Reset) which is read out from each sensor 40 of the sensor portion 21 through the signal line 26 as a comparison input, and takes the reference voltage V.sub.ref having the ramp waveform supplied from the reference voltage generator 54 as a reference input, thereby comparing both of the inputs, where current source 35 having the load MOS circuit supplies the constant current to amplification transistor 44 of the sensor 40 included in the selected row (and connected to comparator 51), thereby operating the amplification transistor 44 as a source follower. As can be seen in par. 94 this is advantageous in that it is possible to realize the processing of the correlated double sampling (CDS) to eliminate noise. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the input being a comparator.
Regarding claim 9, Shishido is silent with regards to the first conversion unit has a first latch circuit to which a first clock signal is inputted, wherein the second conversion unit has a second latch circuit to which a second clock signal is inputted, wherein the first pixel control unit is configured to control input of the first clock signal to the first latch circuit, and wherein the second pixel control unit is configured to control input of the second clock signal to the second latch circuit. Kurose discloses the first conversion unit has a first latch circuit to which a first clock signal is inputted (counter portion 52 and data latch portion 55 (of data latch portions 55), where the counter portion 52 to which a clock CK is supplied from the clock supply portion (not illustrated) provided in the control portion 34 and operates based on an output signal of the comparator 51, par. 78, 79, 110-111, and Figs. 2 and 7), wherein the second conversion unit has a second latch circuit to which a second clock signal is inputted (in another column counter portion 52 and data latch portion 55 (of data latch portions 55), where the counter portion 52 to which a clock CK is supplied from the clock supply portion (not illustrated) provided in the control portion 34 and operates based on an output signal of the comparator 51, par. 78, 79, 110-111, and Figs. 2 and 7), wherein the first pixel control unit is configured to control input of the first clock signal to the first latch circuit (portion of control portion 34 (including the clock supply portion and the timing control circuit connected to the AD converter 50) that provides the clock and timing control signals to the AD converter of signal processing portion 31, par. 78, 79, and Fig. 2), and wherein the second pixel control unit is configured to control input of the second clock signal to the second latch circuit (in another column the portion of control portion 34 (including the clock supply portion and the timing control circuit connected to the AD converter 50) that provides the clock and timing control signals to the AD converter of signal processing portion 31, par. 78, 79, and Fig. 2). As can be seen in par. 90 this is advantageous in that a predetermined signal processing including digitization (AD conversion) in parallel (column parallel) can be performed by sensor column as a unit with respect to an analog signal which is read out from each sensor 40 of the sensor portion 21 for each sensor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the first conversion unit has a first latch circuit to which a first clock signal is inputted, wherein the second conversion unit has a second latch circuit to which a second clock signal is inputted, wherein the first pixel control unit is configured to control input of the first clock signal to the first latch circuit, and wherein the second pixel control unit is configured to control input of the second clock signal to the second latch circuit.
Conclusion
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/NICHOLAS G GILES/ Primary Examiner, Art Unit 2639