DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Amendment on 02/06/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, 13 and 14 rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Hiroki (JP 2020/167882; rejection based on English translation).
Regarding claim 1, Hiroki discloses (see figures 1-2) a power supply control device (figure 1, part 50) comprising: a first switch (figure 1, part 2a); and a processing unit (figure 1, part 40) configured to execute processing (figure 1, part 40) (page 7; lines 38-40; The control unit 40 is a control unit that controls on and off of the semiconductor switches 11a, 12a, and 13a based on an instruction signal from the host controller 30. For example, the control unit 40 includes a microcomputer including a CPU, a ROM, a RAM, and the like), wherein the processing unit (figure 1, part 40) causes a state of each of a plurality of second switches (figure 1, parts 11a, 12a and 13a) to which current is input from the first switch (figure 1, part 2a) to transition from an off state (figure 1, parts 11a, 12a and 13a; off state) to a current conduction state in which current can flow therethrough (figure 1, parts 11a, 12a and 13a; current conduction state) (page 5; lines 4-60; The distribution unit 10 supplies or cuts off the electric power of the power source 1 to the loads 21 to 23 according to the operation of the semiconductor devices 11 to 13. Examples of the semiconductor devices 11 to 13 include semiconductor switches 11a, 12a, 13a, freewheeling diodes 11b, 12b, 13b, current sensors 11c, 12c, 13c, voltage sensors 11d, 12d, 13d, and multiplexers 11e, 12e, 13e, which will be described later. Examples include ICs such as IPDs. The IC such as IPD has a temperature detection circuit and a control circuit (both are not shown), and is protected from overcurrent, overvoltage, or temperature abnormality by the self-diagnosis function of the control circuit), and the processing unit (figure 1, part 40) is configured to transmit a signal (figure 1, part 7) to change a duty ratio of at least one of the second switches (figure 1, parts 11a, 12a and 13a at current limiting function wherein the control unit 40 execute PWM control [change duty ratio]) so as to adjust an average value of current flowing per unit time for a corresponding one of the at least one of the second switches (figure 1, part average value of current flowing per unit time for 11a, 12a and 13a at current limiting function wherein the control unit 40 execute PWM control [change duty ratio]) (page 12, lines 35-46; You may limit the current flowing through. For example, the control unit 40 may execute PWM (Pulse Width Modulation) control on a plurality of semiconductor switches when the resistance value of the wire harness 3 is larger than the reference resistance value. In this case, the storage unit 42 stores in advance the duty ratio corresponding to the priority of the loads 21 to 23 shown in FIG. 1, and the control unit 40 stores the duty ratio corresponding to each load from the storage unit 42. get. Then, the control unit 40 generates a pulse-shaped drive signal according to the duty ratio corresponding to each load, and outputs the pulse-shaped drive signal to each of the semiconductor switches corresponding to each load. When the PWM control is executed by the control unit 40, the semiconductor switches 11a to 13a shown in FIG. 1 perform a switching operation. As a result, the current flowing to each load is repeatedly supplied or cut off, so that the current flowing through each load is substantially reduced, and the current flowing through the wire harness 3 is also reduced), according to one or more second switches that are in the current conduction state (figure 1, parts 11a, 12a and 13a at current conduction state; based on the detection results from 11a-13a [when 11a-13a are in current conduction state] used to calculate the resistance of wire 3) (page 8; lines 50-56; The control unit 44 calculates the resistance value of the wire harness 3 when the loads 21 to 23 are driven by the semiconductor device control function… The resistance value of the wire harness 3 is calculated based on the output results from the semiconductor devices 11 to 13), and thereby sets (figure 1, parts 11a, 12a and 13a; through current limiting function wherein the control unit 40 execute PWM control at second switches 11a-13a) an average value of current flowing per unit time through the first switch (figure 1, part average value of current flowing per unit time through 2a) to less than a sum value of current flowing each of the second switches when the first switch is fixed in an on state (figure 1, part average value of current flowing per unit time through 2a; when 2a and 11a-13a are fixed in on-state) (pages 9-10, lines 53-60 and 1-5; page 12, lines 35-46; the control unit 44 determines that the current flowing through the wire harness 3 needs to be limited, that is, when the calculated resistance value is larger than the reference resistance value… the control unit 44 turns off the semiconductor switches 12a and 13a corresponding to the lower priority loads 22 and 23. The power supply to the loads 22 and 23 is stopped. Further, the control unit 44 keeps the semiconductor switch 11a on, which corresponds to the load 21 having a high priority, and keeps supplying electric power to the load 21. When the semiconductor switches 12a and 13a change from the on state to the off state, the power supply to the loads 22 and 23 is stopped. Therefore, the current flowing through the wire harness 3 is smaller than that when the semiconductor switches 11a to 13a are in the on state. It is reduced by the amount of current required to drive the loads 22 and 23… You may limit the current flowing through. For example, the control unit 40 may execute PWM (Pulse Width Modulation) control on a plurality of semiconductor switches when the resistance value of the wire harness 3 is larger than the reference resistance value. In this case, the storage unit 42 stores in advance the duty ratio corresponding to the priority of the loads 21 to 23 shown in FIG. 1, and the control unit 40 stores the duty ratio corresponding to each load from the storage unit 42. get. Then, the control unit 40 generates a pulse-shaped drive signal according to the duty ratio corresponding to each load, and outputs the pulse-shaped drive signal to each of the semiconductor switches corresponding to each load. When the PWM control is executed by the control unit 40, the semiconductor switches 11a to 13a shown in FIG. 1 perform a switching operation. As a result, the current flowing to each load is repeatedly supplied or cut off, so that the current flowing through each load is substantially reduced, and the current flowing through the wire harness 3 is also reduced).
Regarding claim 3, Hiroki discloses everything claimed as applied above (see claim 1). Hiroki discloses (see figures 1-2) when the state of the second switch is fixed in an on state (figure 1, part 11a, 12a and 13a; at normal fixed on state) or PWM control of the second switch is performed (figure 1, part 11a, 12a and 13a; through current limiting function wherein the control unit 40 execute PWM control at second switches 11a-13a, when calculated resistance of wire 3 is larger than reference resistance value), the state of the second switch (figure 1, part 11a, 12a and 13a) is caused to transition to the current flow state (figure 1, part current flow through 11a, 12a and 13a; at normal fixed on-state or PWM control) (pages 9-10, lines 53-60 and 1-5; page 12, lines 35-46; the control unit 44 determines that the current flowing through the wire harness 3 needs to be limited, that is, when the calculated resistance value is larger than the reference resistance value… the control unit 44 turns off the semiconductor switches 12a and 13a corresponding to the lower priority loads 22 and 23. The power supply to the loads 22 and 23 is stopped. Further, the control unit 44 keeps the semiconductor switch 11a on, which corresponds to the load 21 having a high priority, and keeps supplying electric power to the load 21. When the semiconductor switches 12a and 13a change from the on state to the off state, the power supply to the loads 22 and 23 is stopped. Therefore, the current flowing through the wire harness 3 is smaller than that when the semiconductor switches 11a to 13a are in the on state. It is reduced by the amount of current required to drive the loads 22 and 23… You may limit the current flowing through. For example, the control unit 40 may execute PWM (Pulse Width Modulation) control on a plurality of semiconductor switches when the resistance value of the wire harness 3 is larger than the reference resistance value. In this case, the storage unit 42 stores in advance the duty ratio corresponding to the priority of the loads 21 to 23 shown in FIG. 1, and the control unit 40 stores the duty ratio corresponding to each load from the storage unit 42. get. Then, the control unit 40 generates a pulse-shaped drive signal according to the duty ratio corresponding to each load, and outputs the pulse-shaped drive signal to each of the semiconductor switches corresponding to each load. When the PWM control is executed by the control unit 40, the semiconductor switches 11a to 13a shown in FIG. 1 perform a switching operation. As a result, the current flowing to each load is repeatedly supplied or cut off, so that the current flowing through each load is substantially reduced, and the current flowing through the wire harness 3 is also reduced).
Regarding claim 4, Hiroki discloses everything claimed as applied above (see claim 1). Hiroki discloses (see figures 1-2) a switching circuit (figure 1, part 43) configured to switch the state of the first switch (figure 1, part 2a) to an on state or an off state (figure 1, part 2a; on or off state) (page 3; lines 16-31; the gate electrode of the semiconductor switch 2a is connected to the drive unit 43 of the control unit 40 via the wiring 6. The wiring 6 is a wiring independent of the wirings 7a to 7c described later. The gate electrode of the semiconductor switch 2a is controlled by a drive signal output from the drive unit 43), wherein the switching circuit (figure 1, part 43) switches the state of the first switch to the off state (figure 1, part 43; off state) if the value of the current flowing through the first switch (figure 1, part current flow through 2a) reaches a value greater than or equal to a current threshold value (figure 1, part 2a; current threshold at overcurrent detection) (page 3; lines 39-47; when the semiconductor switch 2a is off, the drain electrode and the source electrode are cut off, so that the power supply 1 and the distribution unit 10 are electrically cut off. Therefore, when the semiconductor switch 2a is off, no current flows from the power supply 1 in the direction of the distribution unit 10. That is, even if an overcurrent flows from the power supply 1 to the semiconductor device 2 for some reason, it is possible to prevent the overcurrent from flowing into the distribution unit 10 by turning off the semiconductor switch 2a).
Regarding claim 13, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Regarding claim 14, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Hiroki (JP 2020/167882; rejection based on English translation), in view of Froeschl et al. (US 2022/0255312), hereinafter Froeschl, and further in view of Sawano et al. (US 2019/0165561), hereinafter Sawano.
Regarding claim 5, Hiroki discloses everything claimed as applied above (see claim 1). Hiroki discloses (see figures 1-2) the processing unit (figure 1, part 40) instructs switching of the second switch to the off state (figure 1, part 11a, 12a or 13; off state) (pages 9-10, lines 53-60 and 1-5; page 12, lines 35-46; the control unit 44 determines that the current flowing through the wire harness 3 needs to be limited, that is, when the calculated resistance value is larger than the reference resistance value… the control unit 44 turns off the semiconductor switches 12a and 13a corresponding to the lower priority loads 22 and 23. The power supply to the loads 22 and 23 is stopped. Further, the control unit 44 keeps the semiconductor switch 11a on, which corresponds to the load 21 having a high priority, and keeps supplying electric power to the load 21. When the semiconductor switches 12a and 13a change from the on state to the off state, the power supply to the loads 22 and 23 is stopped), and if a period during which a value of a voltage between both ends of the second switch (figure 1, part voltage between both ends of 11a, 12a or 13; through 11d-13d) is maintained at a value within a predetermined range (figure 1, part voltage between both ends of 11a, 12a or 13; a predetermined range at overvoltage detection) (page 5; lines 19-29; the semiconductor devices 11 to 13 include semiconductor switches 11a, 12a, 13a, freewheeling diodes 11b, 12b, 13b, current sensors 11c, 12c, 13c, voltage sensors 11d, 12d, 13d, and multiplexers 11e, 12e, 13e, which will be described later. Examples include ICs such as IPDs. The IC such as IPD has a temperature detection circuit and a control circuit (both are not shown), and is protected from overcurrent, overvoltage, or temperature abnormality by the self-diagnosis function of the control circuit). However, Hiroki does not expressly disclose if a period during which a value of a voltage between both ends of the second switch is maintained at a value within a predetermined range reaches a value greater than or equal to a predetermined period when switching of the second switch to the off state has been instructed, the processing unit instructs switching of the first switch to the off state.
Froeschl teaches (see figures 1-4) the processing unit (figures 2a and 2b, part 201) instructs switching of the second switch to the off state (figure 2b, part 204; instructs to off state at event 214), and if a period during which a value of current flowing through the second switch (figure 2b, part current flowing through 204) is maintained at value within a second predetermined range (figure 2b, part current flowing through 204; predetermined range at the event 214) when switching of the second switch to the off state has been instructed (figure 2b, part 204; instructs to off state at event 214) (paragraph [0044]; an event 214 may be detected, for example, at the first switching element 204, the event 214 adversely affecting the switching of the first switching element 204. In particular, it is possible to detect that the first switching element 204 does not open and therefore the first line 154 cannot be disconnected even though a specified first current threshold value is exceeded), the processing unit (figures 2a and 2b, part 201) instructs switching of the first switch to the off state (figure 2b, part 205; off state through 211) (paragraph [0047]; the failure of a semiconductor switch unit 204 of the current distributor 152 and the transmission of the detected event 214 to the semiconductor switch unit 205 of the current distributor 152 with the command 211 to interrupt or to deactivate the power supply).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure power supply control device of Hiroki with the control features as taught Froeschl, because it provides more reliable and efficient control with diagnostics, fault localization and where necessary an emergency operation may also be assigned to individual components of the on-board electrical system in order to obtain better protection (paragraph [0060]).
Sawano teaches (see figures 1-10) if a period (figures 3, part period determined at S16) during which a value of a voltage between both ends of the second switch (figures 1, part 20) is maintained at a value within a predetermined range reaches a value (figures 1, part a voltage between both ends of 20) greater than or equal to a predetermined period (figures 3, part first reference time period at S16; to Yes) when switching of the second switch (figures 1, part 20) (paragraphs [0069]-[0070]; the control unit 39 determines whether the counted time period that is being counted by the first timer 36 is longer than or equal to a first reference time period (step S16). The first reference time period is a constant time period, and is predetermined. If the control unit 39 determines that the counted time period is shorter than the first reference time period (NO in S16), the control unit 39 executes step S14… If the control unit 39 determines that the counted time period is longer than the first reference time period (YES in S16), the control unit 39 instructs the output unit 33 to switch to a low level voltage (step S17). In this manner, the output unit 33 switches the voltage that is output to the driving circuit 22 from a high level voltage to a low level voltage. As a result, the driving circuit 22 switches OFF the semiconductor switch 20, and power supply to the load 13 is stopped).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Hiroki and Froeschl with the time control features as taught Sawano and obtain the processing unit instructs switching of the second switch to the off state, and if a period during which a value of a voltage between both ends of the second switch is maintained at a value within a predetermined range reaches a value greater than or equal to a predetermined period when switching of the second switch to the off state has been instructed, the processing unit instructs switching of the first switch to the off state, because it provides more robust and complete protection for the circuit (paragraph [0007]).
Regarding claim 6, Hiroki discloses everything claimed as applied above (see claim 1). Hiroki discloses (see figures 1-2) the processing unit (figure 1, part 40) instructs switching of the second switch to the off state (figure 1, part 11a, 12a or 13; off state) (pages 9-10, lines 53-60 and 1-5; page 12, lines 35-46; the control unit 44 determines that the current flowing through the wire harness 3 needs to be limited, that is, when the calculated resistance value is larger than the reference resistance value… the control unit 44 turns off the semiconductor switches 12a and 13a corresponding to the lower priority loads 22 and 23. The power supply to the loads 22 and 23 is stopped. Further, the control unit 44 keeps the semiconductor switch 11a on, which corresponds to the load 21 having a high priority, and keeps supplying electric power to the load 21. When the semiconductor switches 12a and 13a change from the on state to the off state, the power supply to the loads 22 and 23 is stopped), and if a period during which a value of current flowing through the second switch (figure 1, part current flowing through 11a, 12a or 13; through 11c-13c) is maintained at a value within a second predetermined range (figure 1, part current flowing through 11a, 12a or 13; a predetermined range at overcurrent detection) (page 5; lines 19-29; the semiconductor devices 11 to 13 include semiconductor switches 11a, 12a, 13a, freewheeling diodes 11b, 12b, 13b, current sensors 11c, 12c, 13c, voltage sensors 11d, 12d, 13d, and multiplexers 11e, 12e, 13e, which will be described later. Examples include ICs such as IPDs. The IC such as IPD has a temperature detection circuit and a control circuit (both are not shown), and is protected from overcurrent, overvoltage, or temperature abnormality by the self-diagnosis function of the control circuit). However, Hiroki does not expressly disclose if a period during which a value of current flowing through the second switch is maintained at a value within a second predetermined range reaches a value greater than or equal to a second predetermined period when switching of the second switch to the off state has been instructed, the processing unit instructs switching of the first switch to the off state.
Froeschl teaches (see figures 1-4) the processing unit (figures 2a and 2b, part 201) instructs switching of the second switch to the off state (figure 2b, part 204; instructs to off state at event 214), and if a period during which a value of current flowing through the second switch (figure 2b, part current flowing through 204) is maintained at value within a second predetermined range (figure 2b, part current flowing through 204; predetermined range at the event 214) when switching of the second switch to the off state has been instructed (figure 2b, part 204; instructs to off state at event 214) (paragraph [0044]; an event 214 may be detected, for example, at the first switching element 204, the event 214 adversely affecting the switching of the first switching element 204. In particular, it is possible to detect that the first switching element 204 does not open and therefore the first line 154 cannot be disconnected even though a specified first current threshold value is exceeded), the processing unit (figures 2a and 2b, part 201) instructs switching of the first switch to the off state (figure 2b, part 205; off state through 211) (paragraph [0047]; the failure of a semiconductor switch unit 204 of the current distributor 152 and the transmission of the detected event 214 to the semiconductor switch unit 205 of the current distributor 152 with the command 211 to interrupt or to deactivate the power supply).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure power supply control device of Hiroki with the control features as taught Froeschl, because it provides more reliable and efficient control with diagnostics, fault localization and where necessary an emergency operation may also be assigned to individual components of the on-board electrical system in order to obtain better protection (paragraph [0060]).
Sawano teaches (see figures 1-10) if a period (figures 3, part period determined at S16) during which a value of current flowing through the second switch (figures 1, part 20) is maintained at a value within a second predetermined range reaches a value (figures 1, part a voltage between both ends of 20) greater than or equal to a second predetermined period (figures 3, part first reference time period at S16; to Yes) when switching of the second switch (figures 1, part 20) (paragraphs [0069]-[0070]; the control unit 39 determines whether the counted time period that is being counted by the first timer 36 is longer than or equal to a first reference time period (step S16). The first reference time period is a constant time period, and is predetermined. If the control unit 39 determines that the counted time period is shorter than the first reference time period (NO in S16), the control unit 39 executes step S14… If the control unit 39 determines that the counted time period is longer than the first reference time period (YES in S16), the control unit 39 instructs the output unit 33 to switch to a low level voltage (step S17). In this manner, the output unit 33 switches the voltage that is output to the driving circuit 22 from a high level voltage to a low level voltage. As a result, the driving circuit 22 switches OFF the semiconductor switch 20, and power supply to the load 13 is stopped).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Hiroki and Froeschl with the time control features as taught Sawano and obtain the processing unit instructs switching of the second switch to the off state, and if a period during which a value of current flowing through the second switch is maintained at a value within a second predetermined range reaches a value greater than or equal to a second predetermined period when switching of the second switch to the off state has been instructed, the processing unit instructs switching of the first switch to the off state, because it provides more robust and complete protection for the circuit (paragraph [0007]).
Claims 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hiroki (JP 2020/167882; rejection based on English translation), in view of Froeschl et al. (US 2022/0255312), hereinafter Froeschl.
Regarding claim 7, Hiroki discloses everything claimed as applied above (see claim 1). Hiroki discloses (see figures 1-2) the processing unit (figure 1, part 40) instructs switching of the second switch to the off state (figure 1, part 11a, 12a or 13; off state) (pages 9-10, lines 53-60 and 1-5; page 12, lines 35-46; the control unit 44 determines that the current flowing through the wire harness 3 needs to be limited, that is, when the calculated resistance value is larger than the reference resistance value… the control unit 44 turns off the semiconductor switches 12a and 13a corresponding to the lower priority loads 22 and 23. The power supply to the loads 22 and 23 is stopped. Further, the control unit 44 keeps the semiconductor switch 11a on, which corresponds to the load 21 having a high priority, and keeps supplying electric power to the load 21. When the semiconductor switches 12a and 13a change from the on state to the off state, the power supply to the loads 22 and 23 is stopped), and if a value of a voltage between both ends of the second switch (figure 1, part voltage between both ends of 11a, 12a or 13; through 11d-13d) is less than a predetermined voltage value (figure 1, part voltage between both ends of 11a, 12a or 13; a predetermined voltage at overcurrent detection) (page 5; lines 19-29; the semiconductor devices 11 to 13 include semiconductor switches 11a, 12a, 13a, freewheeling diodes 11b, 12b, 13b, current sensors 11c, 12c, 13c, voltage sensors 11d, 12d, 13d, and multiplexers 11e, 12e, 13e, which will be described later. Examples include ICs such as IPDs. The IC such as IPD has a temperature detection circuit and a control circuit (both are not shown), and is protected from overcurrent, overvoltage, or temperature abnormality by the self-diagnosis function of the control circuit). However, Hiroki does not expressly disclose when switching of the second switch to the off state has been instructed, the processing unit instructs switching of the first switch to the off state.
Froeschl teaches (see figures 1-4) the processing unit (figures 2a and 2b, part 201) instructs switching of the second switch to the off state (figure 2b, part 204; instructs to off state at event 214), and if a value of current flowing through the second switch (figure 2b, part current flowing through 204) is maintained at value within a second predetermined range (figure 2b, part current flowing through 204; predetermined range at the event 214) when switching of the second switch to the off state has been instructed (figure 2b, part 204; instructs to off state at event 214) (paragraph [0044]; an event 214 may be detected, for example, at the first switching element 204, the event 214 adversely affecting the switching of the first switching element 204. In particular, it is possible to detect that the first switching element 204 does not open and therefore the first line 154 cannot be disconnected even though a specified first current threshold value is exceeded), the processing unit (figures 2a and 2b, part 201) instructs switching of the first switch to the off state (figure 2b, part 205; off state through 211) (paragraph [0047]; the failure of a semiconductor switch unit 204 of the current distributor 152 and the transmission of the detected event 214 to the semiconductor switch unit 205 of the current distributor 152 with the command 211 to interrupt or to deactivate the power supply).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure power supply control device of Hiroki with the control features as taught Froeschl and obtain the processing unit instructs switching of the second switch to the off state, and if a value of a voltage between both ends of the second switch is less than a predetermined voltage value when switching of the second switch to the off state has been instructed, the processing unit instructs switching of the first switch to the off state, because it provides more reliable and efficient control with diagnostics, fault localization and where necessary an emergency operation may also be assigned to individual components of the on-board electrical system in order to obtain better protection (paragraph [0060]).
Regarding claim 8, Hiroki and Froeschl teach everything claimed as applied above (see claim 7). Hiroki discloses (see figures 1-2) when switching of the second switch to the off state has been instructed (figure 1, part 11a, 12a or 13; off state) (pages 9-10, lines 53-60 and 1-5; page 12, lines 35-46; the control unit 44 determines that the current flowing through the wire harness 3 needs to be limited, that is, when the calculated resistance value is larger than the reference resistance value… the control unit 44 turns off the semiconductor switches 12a and 13a corresponding to the lower priority loads 22 and 23. The power supply to the loads 22 and 23 is stopped. Further, the control unit 44 keeps the semiconductor switch 11a on, which corresponds to the load 21 having a high priority, and keeps supplying electric power to the load 21. When the semiconductor switches 12a and 13a change from the on state to the off state, the power supply to the loads 22 and 23 is stopped), if a value of a voltage between both ends of a specific switch determined in advance (figure 1, part voltage between both ends of 12a) among the plurality of second switches (figure 1, part 11a, 12a and 13) is less than a predetermined voltage value (figure 1, part voltage between both ends of 12a; a predetermined voltage at overcurrent detection) (page 5; lines 19-29; the semiconductor devices 11 to 13 include semiconductor switches 11a, 12a, 13a, freewheeling diodes 11b, 12b, 13b, current sensors 11c, 12c, 13c, voltage sensors 11d, 12d, 13d, and multiplexers 11e, 12e, 13e, which will be described later. Examples include ICs such as IPDs. The IC such as IPD has a temperature detection circuit and a control circuit (both are not shown), and is protected from overcurrent, overvoltage, or temperature abnormality by the self-diagnosis function of the control circuit). However, Hiroki does not expressly disclose the processing unit instructs switching of the first switch to the off state.
Froeschl teaches (see figures 1-4) when switching of the second switch to the off state has been instructed (figure 2b, part 204; instructs to off state at event 214), and if a value of current flowing through the second switch (figure 2b, part current flowing through 204) is maintained at value within a second predetermined range (figure 2b, part current flowing through 204; predetermined range at the event 214) when switching of the second switch to the off state has been instructed (figure 2b, part 204; instructs to off state at event 214) (paragraph [0044]; an event 214 may be detected, for example, at the first switching element 204, the event 214 adversely affecting the switching of the first switching element 204. In particular, it is possible to detect that the first switching element 204 does not open and therefore the first line 154 cannot be disconnected even though a specified first current threshold value is exceeded), the processing unit (figures 2a and 2b, part 201) instructs switching of the first switch to the off state (figure 2b, part 205; off state through 211) (paragraph [0047]; the failure of a semiconductor switch unit 204 of the current distributor 152 and the transmission of the detected event 214 to the semiconductor switch unit 205 of the current distributor 152 with the command 211 to interrupt or to deactivate the power supply).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure power supply control device of Hiroki with the control features as taught Froeschl and obtain when switching of the second switch to the off state has been instructed, if a value of a voltage between both ends of a specific switch determined in advance among the plurality of second switches is less than the predetermined voltage value, the processing unit instructs switching of the first switch to the off state, because it provides more reliable and efficient control with diagnostics, fault localization and where necessary an emergency operation may also be assigned to individual components of the on-board electrical system in order to obtain better protection (paragraph [0060]).
Regarding claim 9, Hiroki and Froeschl teach everything claimed as applied above (see claim 8). Hiroki discloses (see figures 1-2) when switching of the second switch to the off state has been instructed (figure 1, part 11a, 12a or 13; off state), if the value of the voltage between both ends of a second switch (figure 1, part voltage between both ends of 13a) that is not the specific switch (figure 1, part voltage between both ends of 12a) is less than the predetermined voltage value (figure 1, part voltage between both ends of 13a; a predetermined voltage at overcurrent detection) (page 5; lines 19-29; the semiconductor devices 11 to 13 include semiconductor switches 11a, 12a, 13a, freewheeling diodes 11b, 12b, 13b, current sensors 11c, 12c, 13c, voltage sensors 11d, 12d, 13d, and multiplexers 11e, 12e, 13e, which will be described later. Examples include ICs such as IPDs. The IC such as IPD has a temperature detection circuit and a control circuit (both are not shown), and is protected from overcurrent, overvoltage, or temperature abnormality by the self-diagnosis function of the control circuit), the processing unit (figure 1, part 40) lowers the average value of the current flowing per unit time through a second switch (figure 1, part average value of current flowing per unit time for 11a; through current limiting function wherein the control unit 40 execute PWM control at second switches 11a-13a, when calculated resistance of wire 3 is larger than reference resistance value) that is not the second switch (figure 1, part 13a) in which the value of the voltage between both ends is less than the predetermined voltage value (figure 1, part voltage between both ends of 13a; a predetermined voltage at overcurrent detection) (pages 9-10, lines 53-60 and 1-5; page 12, lines 35-46; the control unit 44 determines that the current flowing through the wire harness 3 needs to be limited, that is, when the calculated resistance value is larger than the reference resistance value… the control unit 44 turns off the semiconductor switches 12a and 13a corresponding to the lower priority loads 22 and 23. The power supply to the loads 22 and 23 is stopped. Further, the control unit 44 keeps the semiconductor switch 11a on, which corresponds to the load 21 having a high priority, and keeps supplying electric power to the load 21. When the semiconductor switches 12a and 13a change from the on state to the off state, the power supply to the loads 22 and 23 is stopped. Therefore, the current flowing through the wire harness 3 is smaller than that when the semiconductor switches 11a to 13a are in the on state. It is reduced by the amount of current required to drive the loads 22 and 23… You may limit the current flowing through. For example, the control unit 40 may execute PWM (Pulse Width Modulation) control on a plurality of semiconductor switches when the resistance value of the wire harness 3 is larger than the reference resistance value. In this case, the storage unit 42 stores in advance the duty ratio corresponding to the priority of the loads 21 to 23 shown in FIG. 1, and the control unit 40 stores the duty ratio corresponding to each load from the storage unit 42. get. Then, the control unit 40 generates a pulse-shaped drive signal according to the duty ratio corresponding to each load, and outputs the pulse-shaped drive signal to each of the semiconductor switches corresponding to each load. When the PWM control is executed by the control unit 40, the semiconductor switches 11a to 13a shown in FIG. 1 perform a switching operation. As a result, the current flowing to each load is repeatedly supplied or cut off, so that the current flowing through each load is substantially reduced, and the current flowing through the wire harness 3 is also reduced).
Regarding claim 10, Hiroki discloses everything claimed as applied above (see claim 1). Hiroki discloses (see figures 1-2) the processing unit (figure 1, part 40) instructs switching of the second switch to the off state (figure 1, part 11a, 12a or 13; off state) (pages 9-10, lines 53-60 and 1-5; page 12, lines 35-46; the control unit 44 determines that the current flowing through the wire harness 3 needs to be limited, that is, when the calculated resistance value is larger than the reference resistance value… the control unit 44 turns off the semiconductor switches 12a and 13a corresponding to the lower priority loads 22 and 23. The power supply to the loads 22 and 23 is stopped. Further, the control unit 44 keeps the semiconductor switch 11a on, which corresponds to the load 21 having a high priority, and keeps supplying electric power to the load 21. When the semiconductor switches 12a and 13a change from the on state to the off state, the power supply to the loads 22 and 23 is stopped). However, Hiroki does not expressly disclose if the value of the current flowing through the second switch exceeds a predetermined current value when switching of the second switch to the off state has been instructed, the processing unit instructs switching of the first switch to the off state.
Froeschl teaches (see figures 1-4) the processing unit (figures 2a and 2b, part 201) instructs switching of the second switch to the off state (figure 2b, part 204; instructs to off state at event 214), and if the value of the current flowing through the second switch (figure 2b, part current flowing through 204; instructs to off state) exceeds a predetermined current value (figure 2b, part current flowing through 204 exceed current threshold; based on the event) when switching of the second switch to the off state has been instructed (figure 2b, part 204; instructs to off state at event 214) (paragraph [0044]; an event 214 may be detected, for example, at the first switching element 204, the event 214 adversely affecting the switching of the first switching element 204. In particular, it is possible to detect that the first switching element 204 does not open and therefore the first line 154 cannot be disconnected even though a specified first current threshold value is exceeded), the processing unit (figures 2a and 2b, part 201) instructs switching of the first switch to the off state (figure 2b, part 205; off state through 211) (paragraph [0047]; the failure of a semiconductor switch unit 204 of the current distributor 152 and the transmission of the detected event 214 to the semiconductor switch unit 205 of the current distributor 152 with the command 211 to interrupt or to deactivate the power supply).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure power supply control device of Hiroki with the control features as taught Froeschl and obtain the processing unit instructs switching of the second switch to the off state, and if the value of the current flowing through the second switch exceeds a predetermined current value when switching of the second switch to the off state has been instructed, the processing unit instructs switching of the first switch to the off state, because it provides more reliable and efficient control with diagnostics, fault localization and where necessary an emergency operation may also be assigned to individual components of the on-board electrical system in order to obtain better protection (paragraph [0060]).
Regarding claim 11, Hiroki and Froeschl teach everything claimed as applied above (see claim 10). Hiroki discloses (see figures 1-2) when switching of the second switch to the off state has been instructed (figure 1, part 11a, 12a or 13; off state) (pages 9-10, lines 53-60 and 1-5; page 12, lines 35-46; the control unit 44 determines that the current flowing through the wire harness 3 needs to be limited, that is, when the calculated resistance value is larger than the reference resistance value… the control unit 44 turns off the semiconductor switches 12a and 13a corresponding to the lower priority loads 22 and 23. The power supply to the loads 22 and 23 is stopped. Further, the control unit 44 keeps the semiconductor switch 11a on, which corresponds to the load 21 having a high priority, and keeps supplying electric power to the load 21. When the semiconductor switches 12a and 13a change from the on state to the off state, the power supply to the loads 22 and 23 is stopped). However, Hiroki does not expressly disclose if a value of current flowing through a specific switch determined in advance among the plurality of second switches exceeds the predetermined current value, the processing unit instructs switching of the first switch to the off state.
Froeschl teaches (see figures 1-4) when switching of the second switch to the off state has been instructed (figure 2b, part 204; instructs to off state at event 214), if a value of current flowing through a specific switch determined in advance (figure 2b, part current flowing through specific first 204; instructs to off state) among the plurality of second switches (figure 2b, part plurality of 204) exceeds the predetermined current value (figure 2b, part current flowing through specific first 204 exceed current threshold; based on the event) (paragraph [0044]; an event 214 may be detected, for example, at the first switching element 204, the event 214 adversely affecting the switching of the first switching element 204. In particular, it is possible to detect that the first switching element 204 does not open and therefore the first line 154 cannot be disconnected even though a specified first current threshold value is exceeded), the processing unit (figures 2a and 2b, part 201) instructs switching of the first switch to the off state (figure 2b, part 205; off state through 211) (paragraph [0047]; the failure of a semiconductor switch unit 204 of the current distributor 152 and the transmission of the detected event 214 to the semiconductor switch unit 205 of the current distributor 152 with the command 211 to interrupt or to deactivate the power supply).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure power supply control device of Hiroki with the control features as taught Froeschl and obtain when switching of the second switch to the off state has been instructed, if a value of current flowing through a specific switch determined in advance among the plurality of second switches exceeds the predetermined current value, the processing unit instructs switching of the first switch to the off state, because it provides more reliable and efficient control with diagnostics, fault localization and where necessary an emergency operation may also be assigned to individual components of the on-board electrical system in order to obtain better protection (paragraph [0060]).
Regarding claim 12, Hiroki and Froeschl teach everything claimed as applied above (see claim 11). Hiroki discloses (see figures 1-2) when switching of the second switch to the off state has been instructed (figure 1, part 11a, 12a or 13; off state), the processing unit (figure 1, part 40) lowers the average value of the current flowing per unit time through a second switch (figure 1, part average value of current flowing per unit time for 11a; through current limiting function wherein the control unit 40 execute PWM control at second switches 11a-13a, when calculated resistance of wire 3 is larger than reference resistance value) (pages 9-10, lines 53-60 and 1-5; page 12, lines 35-46; the control unit 44 determines that the current flowing through the wire harness 3 needs to be limited, that is, when the calculated resistance value is larger than the reference resistance value… the control unit 44 turns off the semiconductor switches 12a and 13a corresponding to the lower priority loads 22 and 23. The power supply to the loads 22 and 23 is stopped. Further, the control unit 44 keeps the semiconductor switch 11a on, which corresponds to the load 21 having a high priority, and keeps supplying electric power to the load 21. When the semiconductor switches 12a and 13a change from the on state to the off state, the power supply to the loads 22 and 23 is stopped. Therefore, the current flowing through the wire harness 3 is smaller than that when the semiconductor switches 11a to 13a are in the on state. It is reduced by the amount of current required to drive the loads 22 and 23… You may limit the current flowing through. For example, the control unit 40 may execute PWM (Pulse Width Modulation) control on a plurality of semiconductor switches when the resistance value of the wire harness 3 is larger than the reference resistance value. In this case, the storage unit 42 stores in advance the duty ratio corresponding to the priority of the loads 21 to 23 shown in FIG. 1, and the control unit 40 stores the duty ratio corresponding to each load from the storage unit 42. get. Then, the control unit 40 generates a pulse-shaped drive signal according to the duty ratio corresponding to each load, and outputs the pulse-shaped drive signal to each of the semiconductor switches corresponding to each load. When the PWM control is executed by the control unit 40, the semiconductor switches 11a to 13a shown in FIG. 1 perform a switching operation. As a result, the current flowing to each load is repeatedly supplied or cut off, so that the current flowing through each load is substantially reduced, and the current flowing through the wire harness 3 is also reduced). However, Hiroki does not expressly disclose if the value of the current flowing through a second switch that is not the specific switch exceeds the predetermined voltage value, the processing unit lowers the average value of the current flowing per unit time through a second switch that is not the second switch in which the current with the value exceeding the predetermined current value flows.
Froeschl teaches (see figures 1-4) when switching of the second switch to the off state has been instructed (figure 2a, part 204; instructs to off state), if the value of the current flowing through a second switch that is not the specific switch (figure 2a, part current flowing through second 204) exceeds the predetermined voltage value (figure 2a, part current flowing through second 204 exceed current threshold), the processing unit (figure 2a, part 201) lowers the average value of the current flowing per unit time through a second switch (figure 2a, part lowers the average value of the current flowing per unit time through turn off third 204) that is not the second switch (figure 2a, part current flowing through second 204) in which the current with the value exceeding the predetermined current value flows (figure 2a, part current flowing through second 204 exceed current threshold) (paragraph [0044]; an event 214 may be detected, for example, at the first switching element 204, the event 214 adversely affecting the switching of the first switching element 204. In particular, it is possible to detect that the first switching element 204 does not open and therefore the first line 154 cannot be disconnected even though a specified first current threshold value is exceeded. The control unit 201 of the first switching element 204 may subsequently send a control signal 211 to the second switching element 204 (in particular a control module of the second switching element 204) in order to open the second switching element 204. The second switching element 204 may in this case be opened where appropriate even though the second current threshold value for the permissible current through the second switching element 205 has not yet been reached. It is thus possible to reliably protect the on-board electrical system 150 by disconnecting the current distributor 152).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure power supply control device of Hiroki with the control features as taught Froeschl and obtain when switching of the second switch to the off state has been instructed, if the value of the current flowing through a second switch that is not the specific switch exceeds the predetermined voltage value, the processing unit lowers the average value of the current flowing per unit time through a second switch that is not the second switch in which the current with the value exceeding the predetermined current value flows, because it provides more reliable and efficient control with diagnostics, fault localization and where necessary an emergency operation may also be assigned to individual components of the on-board electrical system in order to obtain better protection (paragraph [0060]).
Response to Arguments
Applicant's arguments filed 02/06/2026 have been fully considered but they are not persuasive.
Applicant’s argues on pages 6-8 of the Applicant's Response (“Applicant submits that the prior art fails to teach or suggest a power supply control device including a first switch; and a processing unit configured to execute processing, wherein the processing unit causes a state of each of a plurality of second switches to which current is input from the first switch to transition from an off state to a current conduction state, and the processing unit is configured to transmit a signal to change a duty ratio of at least one of the second switches so as to adjust an average value of current flowing per unit time for a corresponding one of the at least one of the second switches, according to one or more second switches that are in the current conduction state, and thereby sets an average value of current flowing per unit time through the first switch to less than a sum value of current flowing each of the second switches that is fixed in an on state when the first switch in combination with the other elements of claim 1. Similar arguments may be made with respect to claims 13 and 14”).
The Examiner respectfully disagrees with Applicant’s arguments, because Hiroki discloses a power supply control device (figure 1, part 50) comprising: a first switch (figure 1, part 2a); and a processing unit (figure 1, part 40) configured to execute processing (figure 1, part 40) (page 7; lines 38-40; The control unit 40 is a control unit that controls on and off of the semiconductor switches 11a, 12a, and 13a based on an instruction signal from the host controller 30. For example, the control unit 40 includes a microcomputer including a CPU, a ROM, a RAM, and the like), wherein the processing unit (figure 1, part 40) causes a state of each of a plurality of second switches (figure 1, parts 11a, 12a and 13a) to which current is input from the first switch (figure 1, part 2a) to transition from an off state (figure 1, parts 11a, 12a and 13a; off state) to a current conduction state in which current can flow therethrough (figure 1, parts 11a, 12a and 13a; current conduction state) (page 5; lines 4-60; The distribution unit 10 supplies or cuts off the electric power of the power source 1 to the loads 21 to 23 according to the operation of the semiconductor devices 11 to 13. Examples of the semiconductor devices 11 to 13 include semiconductor switches 11a, 12a, 13a, freewheeling diodes 11b, 12b, 13b, current sensors 11c, 12c, 13c, voltage sensors 11d, 12d, 13d, and multiplexers 11e, 12e, 13e, which will be described later. Examples include ICs such as IPDs. The IC such as IPD has a temperature detection circuit and a control circuit (both are not shown), and is protected from overcurrent, overvoltage, or temperature abnormality by the self-diagnosis function of the control circuit), and the processing unit (figure 1, part 40) is configured to transmit a signal (figure 1, part 7) to change a duty ratio of at least one of the second switches (figure 1, parts 11a, 12a and 13a at current limiting function wherein the control unit 40 execute PWM control [change duty ratio]) so as to adjust an average value of current flowing per unit time for a corresponding one of the at least one of the second switches (figure 1, part average value of current flowing per unit time for 11a, 12a and 13a at current limiting function wherein the control unit 40 execute PWM control [change duty ratio]) (page 12, lines 35-46; You may limit the current flowing through. For example, the control unit 40 may execute PWM (Pulse Width Modulation) control on a plurality of semiconductor switches when the resistance value of the wire harness 3 is larger than the reference resistance value. In this case, the storage unit 42 stores in advance the duty ratio corresponding to the priority of the loads 21 to 23 shown in FIG. 1, and the control unit 40 stores the duty ratio corresponding to each load from the storage unit 42. get. Then, the control unit 40 generates a pulse-shaped drive signal according to the duty ratio corresponding to each load, and outputs the pulse-shaped drive signal to each of the semiconductor switches corresponding to each load. When the PWM control is executed by the control unit 40, the semiconductor switches 11a to 13a shown in FIG. 1 perform a switching operation. As a result, the current flowing to each load is repeatedly supplied or cut off, so that the current flowing through each load is substantially reduced, and the current flowing through the wire harness 3 is also reduced), according to one or more second switches that are in the current conduction state (figure 1, parts 11a, 12a and 13a at current conduction state; based on the detection results from 11a-13a [when 11a-13a are in current conduction state] used to calculate the resistance of wire 3) (page 8; lines 50-56; The control unit 44 calculates the resistance value of the wire harness 3 when the loads 21 to 23 are driven by the semiconductor device control function… The resistance value of the wire harness 3 is calculated based on the output results from the semiconductor devices 11 to 13), and thereby sets (figure 1, parts 11a, 12a and 13a; through current limiting function wherein the control unit 40 execute PWM control at second switches 11a-13a) an average value of current flowing per unit time through the first switch (figure 1, part average value of current flowing per unit time through 2a) to less than a sum value of current flowing each of the second switches when the first switch is fixed in an on state (figure 1, part average value of current flowing per unit time through 2a; when 2a and 11a-13a are fixed in on-state) (pages 9-10, lines 53-60 and 1-5; page 12, lines 35-46; the control unit 44 determines that the current flowing through the wire harness 3 needs to be limited, that is, when the calculated resistance value is larger than the reference resistance value… the control unit 44 turns off the semiconductor switches 12a and 13a corresponding to the lower priority loads 22 and 23. The power supply to the loads 22 and 23 is stopped. Further, the control unit 44 keeps the semiconductor switch 11a on, which corresponds to the load 21 having a high priority, and keeps supplying electric power to the load 21. When the semiconductor switches 12a and 13a change from the on state to the off state, the power supply to the loads 22 and 23 is stopped. Therefore, the current flowing through the wire harness 3 is smaller than that when the semiconductor switches 11a to 13a are in the on state. It is reduced by the amount of current required to drive the loads 22 and 23… You may limit the current flowing through. For example, the control unit 40 may execute PWM (Pulse Width Modulation) control on a plurality of semiconductor switches when the resistance value of the wire harness 3 is larger than the reference resistance value. In this case, the storage unit 42 stores in advance the duty ratio corresponding to the priority of the loads 21 to 23 shown in FIG. 1, and the control unit 40 stores the duty ratio corresponding to each load from the storage unit 42. get. Then, the control unit 40 generates a pulse-shaped drive signal according to the duty ratio corresponding to each load, and outputs the pulse-shaped drive signal to each of the semiconductor switches corresponding to each load. When the PWM control is executed by the control unit 40, the semiconductor switches 11a to 13a shown in FIG. 1 perform a switching operation. As a result, the current flowing to each load is repeatedly supplied or cut off, so that the current flowing through each load is substantially reduced, and the current flowing through the wire harness 3 is also reduced). As disclosed above, Hiroki’ reference discloses the processing unit (figure 1, part 40) that calculates the resistance value of the wire harness 3 (when the loads 21 to 23 are driven by the semiconductor devices 11a-13a) and when this calculated resistance value results to be larger than the reference resistance value, the control unit 44 enter in current limiting function (wherein the control unit 44 execute PWM control on a plurality of semiconductor switches (figure 1, parts 11a, 12a and 13a)). Then, the control unit 40 generates a pulse-shaped drive signal according to the duty ratio corresponding to each load, and outputs the pulse-shaped drive signal to each of the semiconductor switches corresponding to each load. When the PWM control is executed by the control unit 40, the semiconductor switches 11a to 13a shown in FIG. 1 perform a switching operation. As a result, the current flowing to each load is repeatedly supplied or cut off, so that the current flowing through each load is substantially reduced. Therefore, as result, sets (figure 1, parts 11a, 12a and 13a; through current limiting function wherein the control unit 40 execute PWM control at second switches 11a-13a) an average value of current flowing per unit time through the first switch (figure 1, part average value of current flowing per unit time through 2a) to less than a sum value of current flowing each of the second switches when the first switch is fixed in an on state (figure 1, part average value of current flowing per unit time through 2a; when 2a and 11a-13a are fixed in on-state) (pages 9-10, lines 53-60 and 1-5; page 12, lines 35-46). Therefore, based the claim language as recited, Hiroki meets with the claimed limitation. Additional, in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., [1] Hiroki does not teach or suggest adjusting a value of an upstream switch (first switch) by adjusting the duty ration of the switches that are downstream the upstream switch, e.g. the second switches; [2] Hiroki does not disclose the "reducing the maximum average current that ever needs to pass through the upstream first switch." Further, Hiroki does not disclose a control action that "sets" or enforces the first-switch current to be the sum of the second-switch currents.) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Furthermore, the reference Hiroki (JP 2019/041509) teaches this feature of change the duty ratio (PWM control) of at least one of the second switches (figure 8, parts 11a-13a) when the current sensor (figure 8, part 20) detects a current value greater than the third threshold (includes the current value of the rated current of the fuse 2). When, the PWM control of a plurality of semiconductor switches is performed. As a result, the inrush current flowing through the fuse 2 is reduced, and it is not necessary to select the fuse 2 whose rated current is excessively large for the peak of the inrush current of each load. As a result, it is possible to prevent the fuse 2 from being melted by the rated current and to suppress the size of the fuse 2. Further, since the value of the current flowing through the fuse 2 is reduced, the power line 3 can be thinned. As a result, the effects of downsizing and weight reduction of the entire power supply system 100 can be obtained. It should be noted that broad claim language as recited does not defines all the features of the invention (more specific: the use of small first switch by reducing the maximum average current that ever needs to pass through the claimed first switch. It does this with a processing unit (microcomputer) that actively manages the downstream second switches so they are not all held fully on at the same time. In particular, the processing unit (1) transitions each second switch between an off state and a current conduction state, e.g. the duty ratio of each second switch, which adjusts the average current of at least one second switch according to which other second switches are currently conducting. Because the average current of one or more second switches is reduced when others are conducting, the resulting average current through the first switch is set to a value less than the "all switches fixed on"). The examiner suggests the applicant to positively recite in the claim language all the features of the invention, in order to distinguish the invention from the prior art of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838