DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Amendments
Acknowledgment of receiving amendments to the claims, which were received by the Office on 06/22/2026.
Response to Arguments
Applicant’s arguments with respect to claims 7 and 19 have been considered but are moot because the arguments do not apply to the same combination or interpretation of references being used in the current rejection. Applicant’s arguments are directed solely to the claimed invention as amended 06/22/2026, which has been rejected under new ground of rejection necessitated by amendment. See rejection below for full detail.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Stark (US 2018/0063459 A1) in view of Gowda et al. (US 5,877,715) in view of Otaka (US 2018/0198997 A1).
Regarding claim 7, Stark teaches a solid-state imaging element (Stark, Figs. 1 and 4) comprising:
a pixel circuit (Stark, Fig. 4, Elements 202, 204, 206, 208 and 210) that outputs a pixel signal as an input signal (Stark, Fig. 4, The signal at node 230 is the pixel output.) and, in a case where a rolling shutter mode to start exposure sequentially row by row is selected, outputs the pixel signal as a first output signal (Stark, Fig. 4B, Paragraphs 0022, 0063 and 0065, The first output signal is the pixel signal output in the rolling shutter mode.);
a sample-hold circuit (Stark, Fig. 4, Elements 210, 212, 214, 216, 218, 220, 222, 224, and 226) that holds the input signal (Stark, Paragraphs 0026, 0029 and 0034) and outputs the input signal as a second output signal in a case where a global shutter mode to start exposure simultaneously for all pixels is selected (Stark, Fig. 4A, Paragraphs 0021, 0063 and 0066-0067, The second output signal is the pixel signal output in the global shutter mode.); and
a changeover switch that selects a selected output from one of the first and second output signals (Stark, Fig. 4, first controllable switching element 401 or second switch 404, Paragraphs 0064-0065) and outputs the selected output to a column signal processing circuit (Stark, Fig. 1, column signal processing circuit 108),
wherein the pixel circuit includes
a photoelectric converting element (Stark, Fig. 4, photodiode 202, Paragraph 0030),
a transfer transistor that transfers a charge from the photoelectric converting element to a floating diffusion layer (Stark, Fig. 4, transistor 204, Paragraph 0030, Gowda, Column 2, Lines 15-25),
a first reset transistor that initializes the floating diffusion layer (Stark, Fig. 4, transistor 206, Paragraph 0031)
an upstream amplification transistor that outputs, as the input signal, a pixel signal obtained by amplifying a voltage of the floating diffusion layer to a predetermined upstream node in the sample-hold circuit (Stark, Fig. 4, transistor 208 and Node 230, Paragraph 0035), and
a selection transistor that outputs, as the first output signal, the pixel signal according to a predetermined control signal (Stark, Fig. 4B, transistor 210 and control signal BIAS, Paragraph 0067, Transistor 210 acts as a selection transistor in the second mode.); wherein
the sample-hold circuit (Stark, Fig. 4, Elements 210, 212, 214, 216, 218, 220, 222, 224, and 226) further includes a current source transistor connected to a drain of the upstream amplification transistor (Stark, Fig. 4A, transistor 210, Paragraph 0035, Transistor 210 acts as a current source transistor in the first mode. Therefore, transistor 210 is interpreted to be both the selection transistor and current source transistor.), and
the current source transistor transitions from an ON state to an OFF state in a readout period following an exposure period (Stark, Fig. 3, “photodiode integration”, Paragraph 0046) so as to stop a bias current supplied to the upstream amplification transistor (Stark, Fig. 3, Paragraphs 0035, 0051 and 0053, At the end of “sample signal voltage” and after “photodiode integration”, transistor 210 transitions to an OFF state and stops the bias current.).
However, Stark does not teach outputting the selected output to an analog-to-digital converter; and a switching section that adjusts a source voltage to be supplied to a source of the upstream amplification transistor,
In reference to Gowda et al. (hereafter referred as Gowda), Gowda teaches outputting a pixel output to an analog-to-digital converter (Gowda, Figs. 3-4, ADC 40, Column 4, Lines 41-58).
These arts are analogous since they are both related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Stark with the teaching of directly outputting to ADC as seen in Gowda to convert the analog pixel signals to the digital domain and since it is a known configuration for a connection of a pixel to an ADC and would provide similar and expected results for A/D conversion.
However, the combination of Stark and Gowda does not teach a switching section that adjusts a source voltage to be supplied to a source of the upstream amplification transistor.
In reference to Otaka, Otaka teaches a switching section that adjusts a source voltage to be supplied to a source of the upstream amplification transistor (Otaka, Fig. 3, power switching portion 22, Paragraph 0067).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Stark and Gowda with the switching section as seen in Otaka to control the power supplied to the pixel when reading.
Regarding claim 19, the combination of Stark, Gowda and Otaka teaches an imaging device (Stark, Fig. 1, digital imaging system 100) comprising the solid-state imaging element according to claim 1 (see claim 1 analysis).
Allowable Subject Matter
Claims 1-3, 5, 8, 10-15, 17 and 20-21 are allowed.
The following is an examiner’s statement of reasons for allowance:
As per claims 1, the closest known prior art fails to teach or fairly suggest alone or in reasonable combination, the limitations (in consideration of the claim as a whole):
“a changeover switch that selects a selected output from one of the first and second output signals and directly outputs the selected output to an analog-to-digital converter, wherein the pixel circuit includes a photoelectric converting element, a transfer transistor that transfers a charge from the photoelectric converting element to a floating diffusion layer, a first reset transistor that initializes the floating diffusion layer, an upstream amplification transistor that outputs, as the input signal, a pixel signal obtained by amplifying a voltage of the floating diffusion layer to a predetermined upstream node in the sample-hold circuit, and a selection transistor that outputs, as the first output signal, the pixel signal according to a predetermined control signal; wherein the pixel signal includes a predetermined reset level and a signal level according to an exposure amount; wherein the sample-hold circuit includes first and second capacitive elements, a selecting circuit that sequentially performs control to connect one of the first and second capacitive elements to a predetermined downstream node, control to disconnect both the first and second capacitive elements from the downstream node, and control to connect the other of the first and second capacitive elements to the downstream node, a downstream reset transistor that initializes a level of the downstream node when both the first and second capacitive elements are disconnected from the downstream node, and a downstream circuit that sequentially reads out and outputs the reset level and the signal level from the first and second capacitive elements via the downstream node; and a control circuit that controls a reset power supply voltage, wherein the first reset transistor initializes a voltage of a floating diffusion layer to the reset power supply voltage, and in a readout period in which the reset level and the signal level are read out, the control circuit makes the reset power supply voltage a voltage different from a voltage in an exposure period.”
Claims 2-3, 5, 8, 15 and 17 depend on, and further limit, independent claim 1. Therefore, claims 2-3, 5, 8, 15 and 17 are considered allowable for the same reasons.
As per claims 10, the closest known prior art fails to teach or fairly suggest alone or in reasonable combination, the limitations (in consideration of the claim as a whole):
“a changeover switch that selects a selected output from one of the first and second output signals and directly outputs the selected output to an analog-to-digital converter, wherein the pixel circuit includes a photoelectric converting element, a transfer transistor that transfers a charge from the photoelectric converting element to a floating diffusion layer, a first reset transistor that initializes the floating diffusion layer, an upstream amplification transistor that outputs, as the input signal, a pixel signal obtained by amplifying a voltage of the floating diffusion layer to a predetermined upstream node in the sample-hold circuit, and a selection transistor that outputs, as the first output signal, the pixel signal according to a predetermined control signal; wherein the pixel signal includes a predetermined reset level and a signal level according to an exposure amount; wherein the sample-hold circuit includes first and second capacitive elements, a selecting circuit that sequentially performs control to connect one of the first and second capacitive elements to a predetermined downstream node, control to disconnect both the first and second capacitive elements from the downstream node, and control to connect the other of the first and second capacitive elements to the downstream node, a downstream reset transistor that initializes a level of the downstream node when both the first and second capacitive elements are disconnected from the downstream node, and a downstream circuit that sequentially reads out and outputs the reset level and the signal level from the first and second capacitive elements via the downstream node; an analog-to-digital converter that converts the output reset level and signal level sequentially into digital signals; wherein the analog-to-digital converter includes a comparator that compares a level of a vertical signal line which transfers the reset level and the signal level and a predetermined ramp signal and that outputs a comparison result, and a counter that performs counting with a count over a period until the comparison result is inverted and that outputs the digital signal representing the count; wherein the comparator includes a comparing section that compares levels of a pair of input terminals and outputs a comparison result, and an input side selector that selects any one of the vertical signal line and a node with a predetermined reference voltage and connects the selected one to one of the pair of input terminals, wherein the ramp signal is input to one of the pair of input terminals; a control section that determines whether or not illuminance is higher than a predetermined value on a basis of the comparison result and that outputs a determination result; a CDS (Correlated Double Sampling) processing section that executes a correlated double sampling process on the digital signal; and an output side selector that outputs any of the digital signal on which the correlated double sampling process has been executed and a digital signal with a predetermined value, on a basis of the determination result.”
Claims 11-13 and 21 depend on, and further limit, independent claim 10. Therefore, claims 11-13 and 21 are considered allowable for the same reasons.
As per claims 14, the closest known prior art fails to teach or fairly suggest alone or in reasonable combination, the limitations (in consideration of the claim as a whole):
“a changeover switch that selects a selected output from one of the first and second output signals and directly outputs the selected output to an analog-to-digital converter, wherein the pixel circuit includes a photoelectric converting element, a transfer transistor that transfers a charge from the photoelectric converting element to a floating diffusion layer, a first reset transistor that initializes the floating diffusion layer, an upstream amplification transistor that outputs, as the input signal, a pixel signal obtained by amplifying a voltage of the floating diffusion layer to a predetermined upstream node in the sample-hold circuit, and a selection transistor that outputs, as the first output signal, the pixel signal according to a predetermined control signal; wherein the pixel signal includes a predetermined reset level and a signal level according to an exposure amount; wherein the sample-hold circuit includes first and second capacitive elements, a selecting circuit that sequentially performs control to connect one of the first and second capacitive elements to a predetermined downstream node, control to disconnect both the first and second capacitive elements from the downstream node, and control to connect the other of the first and second capacitive elements to the downstream node, a downstream reset transistor that initializes a level of the downstream node when both the first and second capacitive elements are disconnected from the downstream node, and a downstream circuit that sequentially reads out and outputs the reset level and the signal level from the first and second capacitive elements via the downstream node; an analog-to-digital converter that converts the output reset level and signal level sequentially into digital signals; wherein the analog-to-digital converter includes a comparator that compares a level of a vertical signal line which transfers the reset level and the signal level and a predetermined ramp signal and that outputs a comparison result, and a counter that performs counting with a count over a period until the comparison result is inverted and that outputs the digital signal representing the count; wherein the comparator includes a comparing section that compares levels of a pair of input terminals and outputs a comparison result, and an input side selector that selects any one of the vertical signal line and a node with a predetermined reference voltage and connects the selected one to one of the pair of input terminals, wherein the ramp signal is input to one of the pair of input terminals; a control section that determines whether or not illuminance is higher than a predetermined value on a basis of the comparison result and that outputs a determination result; a CDS (Correlated Double Sampling) processing section that executes a correlated double sampling process on the digital signal; and an output side selector that outputs any of the digital signal on which the correlated double sampling process has been executed and a digital signal with a predetermined value, on a basis of the determination result.”
Claims 20 depends on, and further limit, independent claim 14. Therefore, claim 20 is considered allowable for the same reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WESLEY JASON CHIU whose telephone number is (571)270-1312. The examiner can normally be reached Mon-Fri: 8am-4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Twyler Haskins can be reached at (571) 272-7406. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WESLEY J CHIU/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639
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