DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 16, 18, 19, 23 and 24 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Krames (US 2021/0151567 A1).
Regarding claim 1, Krames discloses a manufacturing method for a semiconductor device (Figs. 1A-1E) comprising the steps of: preparing a semiconductor substrate in comprising (i) a template substrate including a main substrate (Figure 1A, reference 101)and (ii) a plurality of bar-shaped semiconductor parts (Figure 1B, reference 102) that are positioned above the template substrate (Figure 1A, reference 101) and include a first semiconductor part having longitudinal shape (Figure 1B, reference 102); dividing the first semiconductor part into a plurality of base semiconductor parts so that each cross-section is along a lateral direction (Figure 1B, reference 102); and forming a compound semiconductor part (Figure 1D, reference 106) above at least one of the plurality of base semiconductor parts (Figure 1B, reference 102), wherein the dividing of the first semiconductor part (Figure 1B, reference 102) is performed before the forming of the compound semiconductor part (Figure 1D, reference 107).
Regarding claim 2, Krames discloses wherein the first semiconductor part is divided into the plurality of base semiconductor parts (Figure 1B, reference 102) by forming one or more trenches (Figure 1B, reference 104) in the first semiconductor part (Figure 1B, reference 102).
Regarding claim 3, Krames discloses wherein the first semiconductor part contains a GaN-based semiconductor (Figure 1B, reference 102), the first semiconductor part is separated into the plurality of base semiconductor parts by cleaving the first semiconductor part at an m-plane of the first semiconductor part (paragraph 0051).
Regarding claim 4, Krames discloses wherein the plurality of trenches (Figure 1B, reference 104) are formed by etching (paragraph 0051).
Regarding claim 16, Krames discloses wherein a thickness of the compound semiconductor part (Figure 1D, reference 106) is 1/2 or less of a thickness of at least one of the plurality of base semiconductor parts (Figure 1D, reference 102).
Regarding claim 18, Krames discloses wherein the first semiconductor part (Figure 1A, reference 102) contains a nitride semiconductor (paragraph 0051),the first semiconductor part (Figure 1A, reference 102) is divided into the plurality of base semiconductor parts (Figure 1B, reference 102) by forming a plurality of trenches (Figure 1B, reference 104) in the first semiconductor part (Figure 1B, reference 102), and at least one of the plurality of trenches extends in a <1-100> direction or <11-20> direction of the nitride semiconductor (Figure 1B, reference 104).
Regarding claim 19, Krames discloses wherein the compound semiconductor part (Figure 1D, reference 106) contains a GaN-based semiconductor (paragraph 0054), and the manufacturing method further comprises cleaving the compound semiconductor part at an m-plane of the GaN-based semiconductor (Figure 1E, reference 106).
Regarding claim 23, Krames discloses wherein the compound semiconductor part is formed in island shapes (Figure 1D, reference 106) corresponding to the plurality of base semiconductor parts (Figure 1D, reference 102).
Regarding claim 24, Krames discloses wherein at least one of the plurality of base semiconductor parts (Figure 1D, reference 102) and the compound semiconductor part (Figure 1D, reference 106) constitute an element portion (paragraphs 0051-0054).
Allowable Subject Matter
Claims 7-9, 11, 12, 22, 26, 29-31, 34 and 35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose nor fairly suggest a manufacturing method for a semiconductor device comprising the steps of: wherein the template substrate includes a mask pattern arranged above the main substrate and comprising a mask portion and an opening portion, and the first semiconductor part is formed over the mask portion from the opening portion (claim 7), wherein cleavage of the first semiconductor part is caused to proceed naturally by scribing the first semiconductor part (claim 34) and wherein the compound semiconductor part contains a GaN semiconductor, and the manufacturing method further comprises cleaving the compound semiconductor part at an m-plane of the GaN-based semiconductor (claim 35) further incorporated into the claims from which they depend from, further incorporated into independent claim 1 and in the context of its recited process, along with its depending claims.
Claims 36-37 are allowed over the prior art of record.
The following is an examiner’s statement of reasons for allowance: The prior art does not disclose nor fairly suggest a manufacturing method for a semiconductor device comprising: forming a second semiconductor part containing a GaN-based semiconductor on the first semiconductor part, and separating the first semiconductor part and second semiconductor part into a plurality of element portions by cleaving the first semiconductor part and second semiconductor part at an m-plane of the first semiconductor part and second semiconductor part as described in independent claims 36 and in the context of its recited process, along with its depending claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA D HARRISON/ Primary Examiner, Art Unit 2815
mdh
June 18, 2026
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