DETAILED ACTION
This office action is responsive to application 18/685,715 filed on April 26, 2024. Claims 1-35 are pending in the application and have been examined by the Examiner.
Information Disclosure Statement
The Information Disclosure Statements (IDS) filed on 2/22/2024 and 8/06/2025 were received and have been considered by the Examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 30-34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 30 recites, at line 9 of page 11, “the control block”. However, claim 30 previously recites, at line 6 thereof (see page 10), “a plurality of control blocks”. It is unclear which control block “the control block” on page 11 is referring to. As such, claim 30 is deemed indefinite by the Examiner.
Claims 31-34 are indefinite as depending from claim 30 and not remedying the deficiencies of claim 30.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11, 14-20 and 30-35 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Higuchi (US 2022/0385846).
Consider claim 1, Higuchi teaches:
An imaging element (figure 16), comprising:
a first semiconductor substrate (first substrate, 401, figures 16 and 17A, paragraphs 0283 and 0287) having a pixel unit (pixel region, 410) in which a plurality of pixels (10) are disposed (“a pixel region 410 including the pixel array unit 100 illustrated in FIG. 2” paragraphs 0283 and 0057), each pixel (10, see figure 3) including a photoelectric conversion unit (photodiode, PD) configured to convert light to an electric charge (“photoelectric conversion”, paragraph 0072), a retention unit (capacitor MEM) configured to retain the electric charge of the photoelectric conversion unit (PD, see figure 3, paragraphs 0073 and 0074), a first transfer unit (transfer transistor, TR1) configured to transfer the electric charge from the photoelectric conversion unit (PD) to the retention unit (MEM, see figure 3, paragraphs 0073 and 0074), an accumulation unit (floating diffusion layer, FD) configured to accumulate the electric charge of the retention unit (MEM, i.e. when transfer transistor TR2 is driven, see figure 3, paragraphs 0075-0077), a second transfer unit (transfer transistor, TR2) configured to transfer the electric charge from the retention unit (MEM) to the accumulation unit (FD, see figure 3, paragraphs 0075-0077), and an output unit (amplification transistor, TR4, read path selection transistor, TR5) configured to output a signal based on the electric charge of the accumulation unit (FD, i.e. to the vertical signal line (VSL), paragraphs 0072 and 0078); and
a second semiconductor substrate (second substrate, 402, figures 16 and 17B, paragraphs 0283 and 0287) having a control circuit unit (vertical scanning unit, 110) that is disposed at a position opposing the pixel unit (i.e. in the circuit region (420) which is opposing the pixel region (410), figure 16, see paragraphs 0283 and 0289) and that is configured to control the first transfer unit (TR1) and the second transfer unit (TR2, i.e. via control signals TRG1 and TRG2 of the vertical drive unit (112) of the vertical scanning unit (110), figure 3, paragraphs 0074, 0075 and 0058), and a peripheral circuit unit (drive signal scanning unit, 120, figure 17B) that is disposed outside of the control circuit unit (110, see figure 17B) and that is configured to control the output unit (The drive signal scanning unit (120) controls the output unit (TR4, TR5) by controlling the vertical scanning unit (110) to provide the selection signal (SEL) to the selection transistor (TR5) of the output unit (TR4, TR5), paragraphs 0058, 0065 and 0078.).
Consider claim 2, and as applied to claim 1 above, Higuchi further teaches that the pixel (10, see figure 3) has a discharge unit (overflow gate transistor, TR0, paragraph 0072) configured to discharge the electric charge of the photoelectric conversion unit (PD, see paragraph 0080), and wherein the control circuit unit (110) is configured to control the discharge unit (TR0) of the pixel (10) of the corresponding pixel block among the plurality of pixel blocks (i.e. via control signal OFG, see figure 3, paragraphs 0074 and 0080).
Consider claim 3, and as applied to claim 1 above, Higuchi further teaches that the pixel (10) has a reset unit (reset transistor, TR3) configured to reset a potential of the accumulation unit (FD, see figure 3, paragraph 0081), and wherein the control circuit unit (110) is configured to control the reset unit (i.e. via the vertical scanning unit (110) that controls the reset unit (TR3) via RST, figure 3, paragraph 0071).
Consider claim 4, and as applied to claim 1 above, Higuchi further teaches that the pixel (10) has a reset unit (reset transistor, TR3) configured to reset a potential of the accumulation unit (FD, see figure 3, paragraph 0081), and wherein the peripheral circuit unit (120) is configured to control the reset unit (i.e. by controlling the vertical scanning unit (110) that controls the reset unit (TR3) via RST, figure 3, paragraph 0071).
Consider claim 5, and as applied to claim 1 above, Higuchi further teaches that the output unit (TR4, TR5) includes an amplification unit (TR4) that is connected to the accumulation unit (FD, see figure 3) and is configured to output the signal (see paragraph 0083), and a selection unit (TR5) configured to output the signal to the signal line (VSL, see figure 3, paragraph 0083), and wherein the peripheral circuit unit (120) is configured to control the selection unit (The peripheral circuit (120) controls the vertical scanning unit (110) to supply the selection signal (SEL) to the selection unit (TR5), see figure 3.).
Consider claim 6, and as applied to claim 1 above, Higuchi further teaches that the control circuit additionally has a signal processing unit (column processing unit, 114, figure 17B) configured to perform signal processing on the signal read from the pixels (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061).
Consider claim 7, and as applied to claim 6 above, Higuchi further teaches that the signal processing unit (114) has a conversion unit configured to convert the signal to a digital signal (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061).
Consider claim 8, and as applied to claim 1 above, Higuchi further teaches that the second semiconductor substrate (402) has a signal processing unit (column processing unit, 114, figure 17B) that is disposed outside of the control circuit unit (110, see figure 17B) and that is configured to perform signal processing on the signal read from the pixels (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061).
Consider claim 9, and as applied to claim 8 above, Higuchi further teaches that the signal processing unit (114) has a conversion unit configured to convert the signal to a digital signal (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061).
Consider claim 10, and as applied to claim 1 above, Higuchi further teaches that the control circuit unit (110) includes a first pixel control unit (i.e. the amplifiers (113) of the vertical drive unit (112) shown in figure 3, paragraph 0070) configured to control the first transfer unit (TR1) and the second transfer unit (TR2, see figure 3, paragraph 0070) of a first pixel (10) among the plurality of pixels (see figure 3), and a second pixel control unit configured to control the first transfer unit and/or the second transfer unit of a second pixel among the plurality of pixels (Paragraph 0070 details that figure 3 illustrates a portion of the vertical drive unit (112) corresponding to one row of the matrix array of the pixel array unit (100). The Examiner interprets a set of amplifiers (113) of the vertical drive unit (112) corresponding to a first row of pixels to be a first pixel control unit, and a second set of amplifiers (113) of the vertical drive unit (112) corresponding to a second row of pixels to be a second pixel control unit.).
Consider claim 11, and as applied to claim 10 above, Higuchi further teaches that the pixel (10) includes a discharge unit (overflow gate transistor, TR0, paragraph 0072) configured to discharge the electric charge of the photoelectric conversion unit (PD, see paragraph 0080), wherein the first pixel control unit (113, 112) is configured to control the discharge unit (TRO) of the first pixel (see figure 3, paragraph 0070), and wherein the second pixel control unit is configured to control the discharge unit of the second pixel (i.e. to control the discharge unit of a pixel of a second row of pixels).
Consider claim 14, and as applied to claim 10 above, Higuchi further teaches that the pixel (10) includes a reset unit (reset transistor, TR3) configured to reset a potential of the accumulation unit (FD, see figure 3, paragraph 0081), wherein the first pixel control unit (113, 112) is configured to control the reset unit of the first pixel (see paragraph 0071), and wherein the second pixel control unit is configured to control the reset unit of the second pixel (i.e. to control the reset unit of a pixel of a second row of pixels).
Consider claim 15, and as applied to claim 10 above, Higuchi further teaches that the control circuit unit (110) has a first signal processing unit (column processing unit, 114, figure 17B) configured to perform signal processing on the signal read from the first pixel, and a second signal processing unit configured to perform signal processing on the signal read from the second pixel (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061. An AD conversion circuit for a first pixel of a first row is a first signal processing unit and an AD conversion circuit for a second pixel of a second row is a second signal processing unit.).
Consider claim 16, and as applied to claim 15 above, Higuchi further teaches that the first signal processing unit has a first conversion unit configured to convert the signal read from the first pixel to a digital signal, and wherein the second signal processing unit has a second conversion unit configured to convert the signal read from the second pixel to a digital signal (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061. An AD conversion circuit for a first pixel of a first row is a first conversion unit and an AD conversion circuit of a second pixel of a second row is a second conversion unit.).
Consider claim 17, and as applied to claim 10 above, Higuchi further teaches that the second semiconductor substrate (402) has a first signal processing unit (column processing unit, 114, figure 17B) configured to perform signal processing on the signal read from the first pixel, and a second signal processing unit configured to perform signal processing on the signal read from the second pixel (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061. An AD conversion circuit for a first pixel of a first row is a first signal processing unit and an AD conversion circuit for a second pixel of a second row is a second signal processing unit.),
wherein the first signal processing unit and the second signal processing unit are disposed outside of the control circuit unit (110) on the semiconductor substrate (i.e. due to the column processing unit (114) being disposed outside of the control circuit unit (110), figure 17B).
Consider claim 18, and as applied to claim 17 above, Higuchi further teaches that the first signal processing unit has a first conversion unit configured to convert the signal read from the first pixel to a digital signal, and wherein the second signal processing unit has a second conversion unit configured to convert the signal read from the second pixel to a digital signal (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061. An AD conversion circuit for a first pixel of a first row is a first conversion unit and an AD conversion circuit of a second pixel of a second row is a second conversion unit.).
Consider claim 19, and as applied to 10 above, Higuchi further teaches that the first pixel and the second pixel are arranged in a row direction in the pixel unit (Pixels (10) are arranged two-dimensionally, as shown in figure 17A. A row direction is based on a viewer’s perspective.), and wherein the first pixel control unit (113, 112) and the second pixel control unit (113, 112) are arranged in the row direction in the control circuit unit (see figures 2 and 17B).
Consider claim 20, and as applied to 10 above, Higuchi further teaches that the first pixel and the second pixel are arranged in a column direction in the pixel unit, and wherein the first pixel control unit and the second pixel control unit are arranged in the column direction in the control circuit unit (Pixels (10) are arranged two-dimensionally, as shown in figure 17A. A column direction is based on a viewer’s perspective.), and wherein the first pixel control unit (113, 112) and the second pixel control unit (113, 112) are arranged in the row direction in the control circuit unit (see figures 2 and 17B).
Consider claim 35, Higuchi teaches an imaging device (figure 1) comprising the imaging element (imaging element 4, paragraphs 0047 and 0049) according to claim 1 (see claim 1 rationale).
Consider claim 30, Higuchi teaches:
An imaging element (figure 16), comprising:
a first semiconductor substrate (first substrate, 401, figures 16 and 17A, paragraphs 0283 and 0287) having a pixel unit (pixel array unit, 100, figure 2, paragraph 0288) having disposed therein a plurality of pixel blocks (pixels, 10) arranged in a first direction and a second direction that intersects with the first direction (see figure 2, paragraph 0057); and
a second semiconductor substrate (second substrate, 402, figures 16 and 17B, paragraphs 0283 and 0287) having a control circuit unit (vertical scanning unit, 110, horizontal scanning unit, 115, column processing unit, 114, paragraph 0289) having disposed therein a plurality of control blocks (110, 114 and 115) arranged in the first direction and the second direction (see figure 17B), and a peripheral circuit unit (drive signal scanning unit, 120, figure 17B, paragraph 0289) that is disposed outside of the control circuit unit (see figure 17B),
wherein the pixel unit (100) and the control circuit unit (110, 114, 115) are arranged so as to oppose each other (i.e. wherein the control circuit unit (110, 114, 115) is found in the circuit region (420) which is opposing the pixel region (410), figures 16 and 17B, see paragraphs 0283 and 0289),
wherein the pixel block has at least one pixel (10, see figure 3) including a photoelectric conversion unit (photodiode, PD) configured to convert light to an electric charge (“photoelectric conversion”, paragraph 0072), a retention unit (capacitor MEM) configured to retain the electric charge of the photoelectric conversion unit (PD, see figure 3, paragraphs 0073 and 0074), a first transfer unit (transfer transistor, TR1) configured to transfer the electric charge from the photoelectric conversion unit (PD) to the retention unit (MEM, see figure 3, paragraphs 0073 and 0074), an accumulation unit (floating diffusion layer, FD) configured to accumulate the electric charge of the retention unit (MEM, i.e. when transfer transistor TR2 is driven, see figure 3, paragraphs 0075-0077), a second transfer unit (transfer transistor, TR2) configured to transfer the electric charge from the retention unit (MEM) to the accumulation unit (FD, see figure 3, paragraphs 0075-0077), and an output unit (amplification transistor, TR4, read path selection transistor, TR5) configured to output a signal based on the electric charge of the accumulation unit (FD, i.e. to the vertical signal line (VSL), paragraphs 0072 and 0078),
wherein the control block (110, 114, 115) has a pixel control unit (vertical scanning unit, 110) configured to control the first transfer unit (TR1) and the second transfer unit (TR2) of the pixel in a corresponding pixel block among the plurality of pixel blocks (i.e. via control signals TRG1 and TRG2 of the vertical drive unit (112) of the vertical scanning unit (110), figure 3, paragraphs 0074, 0075 and 0058), and
wherein the peripheral circuit unit (120) is configured to control the output unit (TR4, TR5) of the pixels (10) of the plurality of pixel blocks (The drive signal scanning unit (120) controls the output unit (TR4, TR5) by controlling the vertical scanning unit (110) to provide the selection signal (SEL) to the selection transistor (TR5) of the output unit (TR4, TR5), paragraphs 0058, 0065 and 0078.).
Consider claim 31, and as applied to claim 30 above, Higuchi further teaches that the pixel (10, see figure 3) has a discharge unit (overflow gate transistor, TR0, paragraph 0072) configured to discharge the electric charge of the photoelectric conversion unit (PD, see paragraph 0080), and wherein the pixel control unit (110) is configured to control the discharge unit of the pixel (10) of the corresponding pixel block among the plurality of pixel blocks (i.e. via control signal OFG, see figure 3, paragraphs 0074 and 0080).
Consider claim 32, and as applied to claim 31 above, Higuchi further teaches that the pixel (10) has a reset unit (reset transistor, TR3) configured to reset a potential of the accumulation unit (FD, see figure 3, paragraph 0081), and wherein the peripheral circuit unit (120) is configured to control the reset unit (TR3) of the pixels of the plurality of pixel blocks (i.e. by controlling the vertical scanning unit (110) that controls the reset unit (TR3) via RST, figure 3, paragraph 0071).
Consider claim 33, and as applied to claim 30 above, Higuchi further teaches that the control block (110, 114, 115) has a conversion unit configured to convert to a digital signal the signal read from the pixel of the corresponding pixel block among the plurality of pixel blocks (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061).
Consider claim 34, and as applied to claim 30 above, Higuchi further teaches that the second semiconductor substrate (402) has a conversion unit that is disposed outside of the control circuit unit and that is configured to convert to a digital signal the signal read from the pixel of the corresponding pixel block among the plurality of pixel blocks (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061. For the sake of claim 34, the Examiner interprets the control circuit unit to only comprise the horizontal scanning unit (115) and the vertical scanning unit (110), which comprise a plurality of blocks arranged two-dimensionally, as shown in figure 17B.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Higuchi (US 2022/0385846) in view of Lin (US 2011/0019045).
Consider claim 12, and as applied to claim 11 above, Higuchi does not explicitly teach that the first pixel control unit is configured to control the discharge unit of the first pixel when the second transfer unit of the first pixel transfers the electric charge, and wherein the second pixel control unit is configured to control the discharge unit of the second pixel when the second transfer unit of the second pixel transfers the electric charge.
Lin similarly teaches a pixel (figure 8) with a discharge unit (911, paragraph 0055) and a second transfer unit (918, paragraph 0055).
However, Lin additionally teaches controlling the discharge unit (911) of the pixel when the second transfer unit (918) transfers the electric charge (see 911A and 918A between the 1st and 2nd readouts in figure 12, paragraphs 0069 and 0070).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the transfer units and discharge units taught by Higuchi be simultaneously controlled in the manner taught by Lin for the benefit of improving efficiency (Lin, paragraph 0069).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Higuchi (US 2022/0385846) in view of Shigeta (US 2020/0213502).
Consider claim 13, and as applied to claim 11 above, Higuchi does not explicitly teach that the first pixel control unit is configured to control the period from the discharge of the electric charge by the discharge unit of the first pixel to the transfer of the electric charge to the retention unit by the first transfer unit of the first pixel so as to be shorter than a flickering period, and wherein the second pixel control unit is configured to control the period from the discharge of the electric charge by the discharge unit of the second pixel to the transfer of the electric charge to the retention unit by the first transfer unit of the second pixel so as to be shorter than a flickering period.
Shigeta similarly teaches a pixel (111, figure 2) with a discharge unit (drain transistor, M6, paragraph 0026) and a first transfer unit (first transfer transistor, M1, paragraph 0026).
However, Shigeta additionally teaches controlling the period from the discharge of the electric charge by the discharge unit (M6) of the first pixel to the transfer of the electric charge to the retention unit by the first transfer unit (M1) of the first pixel so as to be shorter than a flickering period (The period (T15, figure 4A) from discharge (POFG) to first charge transfer (PTX1) is set to less than or equal to half the flicker period (T12), paragraph 0058, see figure 4A.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the period between discharge and first charge transfer of the respective pixel control units taught by Higuchi be set shorter than the flickering period as taught by Shigeta for the benefit of improving image quality by reducing the influence of a flicker phenomenon (Shigeta, paragraph 0058).
Claims 21, 22 and 25-29 are rejected under 35 U.S.C. 103 as being unpatentable over Higuchi (US 2022/0385846) in view of Matsumoto et al. (US 2019/0103427).
Consider claim 21, and as applied to 1 above, Higuchi further teaches that the control circuit unit (110) includes a first pixel control unit (i.e. the amplifiers (113) of the vertical drive unit (112) shown in figure 3, paragraph 0070) configured to control the first transfer unit (TR1) and the second transfer unit (TR2, see figure 3, paragraph 0070) of a first pixel (10) among the plurality of pixels (see figure 3), a second pixel control unit configured to control the first transfer unit and/or the second transfer unit of a second pixel among the plurality of pixels, and a third pixel control unit configured to control the first transfer unit and/or the second transfer unit of a third pixel among the plurality of pixels (Paragraph 0070 details that figure 3 illustrates a portion of the vertical drive unit (112) corresponding to one row of the matrix array of the pixel array unit (100). The Examiner interprets a set of amplifiers (113) of the vertical drive unit (112) corresponding to a first row of pixels to be a first pixel control unit, a second set of amplifiers (113) of the vertical drive unit (112) corresponding to a second row of pixels to be a second pixel control unit, a third set of amplifiers (113) of the vertical drive unit (112) corresponding to a third row of pixels to be a third pixel control unit.),
wherein the first pixel (10) and the second pixel (10) are arranged in a first direction in the pixel unit (see figures 2 and 17A), wherein the first pixel control unit (112, 113) and the second pixel control unit (112, 113) are arranged in the first direction in the control circuit unit (see figures 2 and 17A).
However, Higuchi does not explicitly teach that the first pixel and the third pixel are arranged in a second direction that intersects with the first direction in the pixel unit, and wherein the first pixel control unit and the third pixel control unit are arranged in the second direction in the control circuit unit.
Matsumoto et al. similarly teaches an imaging device (figures 1A-1D) comprising a first semiconductor substrate (first chip, 400) including a plurality of pixel blocks (pixel blocks, 101, paragraph 0021) and a second semiconductor substrate (second chip, 410) including a plurality of pixel control units (blocks, 201, paragraphs 0022 and 0023).
However, Matsumoto et al. additionally teaches that the plurality of pixel control units (201) are arranged two-dimensionally in correspondence with the two-dimensional arrangement of the plurality of pixel blocks (101, see paragraphs 0021 and 0023, figures 1A-1C).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first through third pixels and associated pixel control units taught by Higuchi be arranged two dimensionally (i.e. in first and second directions) as taught by Matsumoto et al. for the benefit of enabling speedup and crosstalk prevention (Matsumoto et al., paragraph 0023).
Consider claim 22, and as applied to claim 21 above, Higuchi further teaches that the pixel (10) includes a discharge unit (overflow gate transistor, TR0, paragraph 0072) configured to discharge the electric charge of the photoelectric conversion unit (PD, see paragraph 0080), wherein the first pixel control unit (113, 112) is configured to control the discharge unit (TRO) of the first pixel (see figure 3, paragraph 0070), and wherein the second pixel control unit is configured to control the discharge unit of the second pixel (i.e. to control the discharge unit of a pixel of a second row of pixels).
The combination of Higuchi and Matsumoto et al. teaches a third control circuit unit associated with a third pixel (see claim 20 rationale), and thus teaches a third discharge unit associated with the third pixel.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first through third pixels and associated pixel control units taught by Higuchi be arranged two dimensionally (i.e. in first and second directions) as taught by Matsumoto et al. for the benefit of enabling speedup and crosstalk prevention (Matsumoto et al., paragraph 0023).
Consider claim 25, and as applied to claim 21 above, Higuchi further teaches that the pixel (10) includes a reset unit (reset transistor, TR3) configured to reset a potential of the accumulation unit (FD, see figure 3, paragraph 0081), wherein the first pixel control unit (113, 112) is configured to control the reset unit of the first pixel (see paragraph 0071), and wherein the second pixel control unit is configured to control the reset unit of the second pixel (i.e. to control the reset unit of a pixel of a second row of pixels).
The combination of Higuchi and Matsumoto et al. teaches a third control circuit unit associated with a third pixel (see claim 20 rationale), and thus teaches a third reset unit associated with the third pixel.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first through third pixels and associated pixel control units taught by Higuchi be arranged two dimensionally (i.e. in first and second directions) as taught by Matsumoto et al. for the benefit of enabling speedup and crosstalk prevention (Matsumoto et al., paragraph 0023).
Consider claim 26, and as applied to claim 21 above, Higuchi further teaches that the control circuit unit (110) has a first signal processing unit (column processing unit, 114, figure 17B) configured to perform signal processing on the signal read from the first pixel, and a second signal processing unit configured to perform signal processing on the signal read from the second pixel (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061. An AD conversion circuit for a first pixel of a first row is a first signal processing unit and an AD conversion circuit for a second pixel of a second row is a second signal processing unit.).
Matsumoto et al. teaches a third signal processing unit configured to perform signal processing on the signal read from the third pixel (Each block (201) includes an AD conversion unit (403) for converting the analog pixel signal into a digital signal, paragraph 0030, figure 2B.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first through third pixels and associated pixel control units taught by Higuchi be arranged two dimensionally (i.e. in first and second directions) as taught by Matsumoto et al. for the benefit of enabling speedup and crosstalk prevention (Matsumoto et al., paragraph 0023).
Consider claim 27, and as applied to claim 26 above, Higuchi further teaches that the first signal processing unit has a first conversion unit configured to convert the signal read from the first pixel to a digital signal, and wherein the second signal processing unit has a second conversion unit configured to convert the signal read from the second pixel to a digital signal (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061. An AD conversion circuit for a first pixel of a first row is a first conversion unit and an AD conversion circuit of a second pixel of a second row is a second conversion unit.).
Matsumoto et al. teaches the third signal processing unit has a third conversion unit configured to convert the signal read from the third pixel to a digital signal (Each block (201) includes an AD conversion unit (403) for converting the analog pixel signal into a digital signal, paragraph 0030, figure 2B.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first through third pixels and associated pixel control units taught by Higuchi be arranged two dimensionally (i.e. in first and second directions) as taught by Matsumoto et al. for the benefit of enabling speedup and crosstalk prevention (Matsumoto et al., paragraph 0023).
Consider claim 28, and as applied to claim 21 above, Higuchi further teaches that the second semiconductor substrate (402) has a first signal processing unit (column processing unit, 114, figure 17B) configured to perform signal processing on the signal read from the first pixel, and a second signal processing unit configured to perform signal processing on the signal read from the second pixel (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061. An AD conversion circuit for a first pixel of a first row is a first signal processing unit and an AD conversion circuit for a second pixel of a second row is a second signal processing unit.),
wherein the first signal processing unit, the second signal processing unit and the third signal processing unit are disposed outside of the control circuit unit (110) on the semiconductor substrate (i.e. due to the column processing unit (114) being disposed outside of the control circuit unit (110), figure 17B).
Matsumoto et al. teaches a third signal processing unit configured to perform signal processing on the signal read from the third pixel (Each block (201) includes an AD conversion unit (403) for converting the analog pixel signal into a digital signal, paragraph 0030, figure 2B.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first through third pixels and associated pixel control units taught by Higuchi be arranged two dimensionally (i.e. in first and second directions) as taught by Matsumoto et al. for the benefit of enabling speedup and crosstalk prevention (Matsumoto et al., paragraph 0023).
Consider claim 29, and as applied to claim 28 above, Higuchi further teaches that the first signal processing unit has a first conversion unit configured to convert the signal read from the first pixel to a digital signal, and wherein the second signal processing unit has a second conversion unit configured to convert the signal read from the second pixel to a digital signal (“The column processing unit 114 includes analog to digital (AD) conversion circuits connected to the vertical signal lines VSL in a one-to-one relation and converts the analog pixel signals supplied from the vertical signal lines into digital pixel signals according to the control by the drive signal scanning unit 120” paragraph 0061. An AD conversion circuit for a first pixel of a first row is a first conversion unit and an AD conversion circuit of a second pixel of a second row is a second conversion unit.).
Matsumoto et al. teaches the third signal processing unit has a third conversion unit configured to convert the signal read from the third pixel to a digital signal (Each block (201) includes an AD conversion unit (403) for converting the analog pixel signal into a digital signal, paragraph 0030, figure 2B.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first through third pixels and associated pixel control units taught by Higuchi be arranged two dimensionally (i.e. in first and second directions) as taught by Matsumoto et al. for the benefit of enabling speedup and crosstalk prevention (Matsumoto et al., paragraph 0023).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Higuchi (US 2022/0385846) in view of Matsumoto et al. (US 2019/0103427), as applied to claim 22 above, and further in view of Lin (US 2011/0019045).
Consider claim 23, and as applied to claim 22 above, the combination of Higuchi and Matsumoto et al. does not explicitly teach that the first pixel control unit is configured to control the discharge unit of the first pixel when the second transfer unit of the first pixel transfers the electric charge, wherein the second pixel control unit is configured to control the discharge unit of the second pixel when the second transfer unit of the second pixel transfers the electric charge, and wherein the third pixel control unit is configured to control the discharge unit of the second pixel when the second transfer unit of the third pixel transfers the electric charge.
Lin similarly teaches a pixel (figure 8) with a discharge unit (911, paragraph 0055) and a second transfer unit (918, paragraph 0055).
However, Lin additionally teaches controlling the discharge unit (911) of the pixel when the second transfer unit (918) transfers the electric charge (see 911A and 918A between the 1st and 2nd readouts in figure 12, paragraphs 0069 and 0070).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the transfer units and discharge units taught by the combination of Higuchi and Matsumoto et al. be simultaneously controlled in the manner taught by Lin for the benefit of improving efficiency (Lin, paragraph 0069).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Higuchi (US 2022/0385846) in view of Matsumoto et al. (US 2019/0103427), as applied to claim 22 above, and further in view of Shigeta (US 2020/0213502).
Consider claim 24, and as applied to claim 22 above, the combination of Higuchi and Matsumoto et al. does not explicitly teach that the first pixel control unit is configured to control the period from the discharge of the electric charge by the discharge unit of the first pixel to the transfer of the electric charge to the retention unit by the first transfer unit of the first pixel so as to be shorter than a flickering period, wherein the second pixel control unit is configured to control the period from the discharge of the electric charge by the discharge unit of the second pixel to the transfer of the electric charge to the retention unit by the first transfer unit of the second pixel so as to be shorter than the flickering period, and wherein the third pixel control unit is configured to control the period from the discharge of the electric charge by the discharge unit of the third pixel to the transfer of the electric charge to the retention unit by the first transfer unit of the third pixel so as to be shorter than the flickering period.
Shigeta similarly teaches a pixel (111, figure 2) with a discharge unit (drain transistor, M6, paragraph 0026) and a first transfer unit (first transfer transistor, M1, paragraph 0026).
However, Shigeta additionally teaches controlling the period from the discharge of the electric charge by the discharge unit (M6) of the first pixel to the transfer of the electric charge to the retention unit by the first transfer unit (M1) of the first pixel so as to be shorter than a flickering period (The period (T15, figure 4A) from discharge (POFG) to first charge transfer (PTX1) is set to less than or equal to half the flicker period (T12), paragraph 0058, see figure 4A.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the period between discharge and first charge transfer of the respective pixel control units taught by the combination of Higuchi and Matsumoto et al. be set shorter than the flickering period as taught by Shigeta for the benefit of improving image quality by reducing the influence of a flicker phenomenon (Shigeta, paragraph 0058).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shirini et al. (US 2019/0104268) teaches an image sensor (figure 24) having a pixel substrate (610) and a control substrate (620), wherein a pixel of the image sensor (see figure 25) includes a photoelectric conversion unit (120), a discharge unit (114), a first transfer unit (130), a retention unit (140), a second transfer unit (150) and an accumulation unit (160).
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637