DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 4 is objected to because of the following informalities:
As to claim 4, line 3 recites “electrically connected through the first type pixel circuit electrically connected.” The “electrically connected” is stated twice. Examiner suggests the claim is amended to recite “electrically connected through the first type pixel circuit.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 30, and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chinese Pub. No. CN 113178537 A by Huang (“Huang”).
For purposes of translation, the Office will utilize U.S. Pub. No. 2024/0074268 by Huang as it is the U.S. patent publication of the Chinese Pub. No. CN 113178537 A by Huang.
As to claim 1, Huang discloses a display substrate (Huang, array substrate 34, Figure 3), comprising:
a display region (Huang, first display region 11 and second display region 12, Figures 1-3) and a peripheral region at least partially surrounding the display region (edges of the display regions 11 and 12), wherein the display region comprises a light-transmitting display region (Huang, first display region 11, Figures 1-3) and a conventional display region (Huang, second display region 12, Figures 1-3) located on at least one side of the light-transmitting display region, and a light transmittance of the light-transmitting display region is greater than a light transmittance of the conventional display region (Huang, To ensure that the sensor of the first display region 11 can receive enough external natural light, the first display region 11 is generally provided with a large light-transmissive region. For example, the number of first sub-pixels 111 is reduced to increase the area of the light-transmissive region. However, the reduction of the number of first sub-pixels 111 may reduce the brightness of the first display region 11. As a result, there is a brightness difference between the first display region 11 and the second display region 12. Figures 1-3, ¶ [0054]);
the display substrate (Huang, array substrate 34, Figure 3) comprises a base substrate (Huang, array substrate 34, Figure 3) and a plurality of light emitting elements (Huang, the first red sub-pixel 41, the first green sub-pixel 42 and the first blue sub-pixel 43. Figures 2 and 3, ¶ [0076]) and a plurality of pixel circuits (Huang, first sub-pixel circuit 231, third sub-pixel circuit 232, and fourth sub-pixel circuit 233, Figure 7) located on one side of the base substrate, the plurality of light emitting elements comprise a plurality of first type light emitting elements (Huang, the first red sub-pixel 41, the first green sub-pixel 42 and the first blue sub-pixel 43. Figures 2 and 3, ¶ [0076]) located in the light-transmitting display region (Huang, first display region 11, Figures 1-3), the plurality of pixel circuits (Huang, first sub-pixel circuit 231, third sub-pixel circuit 232, and fourth sub-pixel circuit 233, Figure 7) comprise a plurality of first type pixel circuits located in the light-transmitting display region (Huang, first display region 11, Figure 7), at least one first type pixel circuit among the plurality of first type pixel circuits is electrically connected with at least two first type light emitting elements emitting light of a same color (Huang, As shown in FIGS. 14 to 16, optionally, the first sub-pixel circuit 231 is configured to drive at least two first green sub-pixels 42 to emit light. Figure 14, ¶ [0089]), and the first type pixel circuit is configured to drive the at least two first type light emitting elements to emit light (Huang, As shown in FIGS. 14 to 16, optionally, the first sub-pixel circuit 231 is configured to drive at least two first green sub-pixels 42 to emit light. Figure 14, ¶ [0089]);
an orthographic projection of the at least one first type pixel circuit on the base substrate (Huang, first sub-pixel circuit 231, third sub-pixel circuit 232, and fourth sub-pixel circuit 233, Figure 7)(Huang, the first-type first sub-pixel 21 also includes a first pixel opening 31. The first-type second sub-pixel 22 also includes a second pixel opening 32. The first anode 211 includes a first anode effective region 2113. The vertical projection of the first pixel opening 31 on the plane where the first anode 211 is located covers the first anode effective region 2113. The second anode 221 includes a second anode effective region 2212. The vertical projection of the second pixel opening 32 on the plane where the second anode 221 is located covers the second anode effective region 2212. The area of the first anode effective region 2113 is less than the area of the second anode effective region 2212. Figures 1-3, ¶ [0056]) is overlapped with an orthographic projection of the at least one first type light emitting element on the base substrate (Huang, the first red sub-pixel 41, the first green sub-pixel 42 and the first blue sub-pixel 43. Figures 2, 3, and 7, ¶ [0076]) (Huang, On the plane where the substrate 341 is located, the vertical projection of the first transparent conductive layer 351 overlaps the vertical projection of the first pixel circuit 23 configured to drive the first-color light-emitting sub-pixels to emit light. Figure 14, ¶ [0102]).
As to claim 2, Huang discloses the display substrate wherein the orthographic projection of the at least one first type pixel circuit on the base substrate is overlapped with an orthographic projection of at least partial first type light emitting element in at least two first type light emitting elements electrically connected with the at least one first type pixel circuit on the base substrate (Huang, first sub-pixel circuit 231, third sub-pixel circuit 232, and fourth sub-pixel circuit 233, Figure 7)(Huang, the first-type first sub-pixel 21 also includes a first pixel opening 31. The first-type second sub-pixel 22 also includes a second pixel opening 32. The first anode 211 includes a first anode effective region 2113. The vertical projection of the first pixel opening 31 on the plane where the first anode 211 is located covers the first anode effective region 2113. The second anode 221 includes a second anode effective region 2212. The vertical projection of the second pixel opening 32 on the plane where the second anode 221 is located covers the second anode effective region 2212. The area of the first anode effective region 2113 is less than the area of the second anode effective region 2212. Figures 1-3, ¶ [0056])(Huang, On the plane where the substrate 341 is located, the vertical projection of the first transparent conductive layer 351 overlaps the vertical projection of the first pixel circuit 23 configured to drive the first-color light-emitting sub-pixels to emit light. Figure 14, ¶ [0102]).
As to claim 3, Huang discloses the display substrate further comprising:
a plurality of first signal lines, wherein the at least one first type pixel circuit is electrically connected with at least one first signal line (Huang, as shown in FIGS. 7, 8, 14, 15, 17 and 18, the first pixel circuit 23 is a 7T1C pixel circuit (seven transistors and one storage capacitor). The display panel may include a first scan line 51, a second scan line 52, a light emission control signal line 53, a first power signal line 54, a second power signal line 55, a reference voltage line 56 and a data line 57. Figures 7, 8, 14, 15, 17, and 18, ¶ [0113]);
the plurality of first signal lines comprise at least one of following: a scan signal line (Huang, first scan signal (Scan1), Figure 18), a reset signal line (Huang, Vref line, Figure 18), an initial signal line (Huang, The light-emitting reset transistor M7 is configured to provide an initialization voltage for a first sub-pixel 111 before the display stage. Figure 18, ¶ [0114]), and a light emitting signal line (Huang, The light emission control signal Emit controls the first light emission control transistor M1 and the second light emission control transistor M6 to be turned on or cut off. Figure 18, ¶ [0114]).
As to claim 4, Huang discloses the display substrate wherein the first signal line comprises: a plurality of sub-signal lines (Huang, The display panel may include a first scan line 51, a second scan line 52, a light emission control signal line 53, a first power signal line 54, a second power signal line 55, a reference voltage line 56 and a data line 57. Figures 7, 8, 14, 15, 17, and 18, ¶ [0113]); adjacent sub-signal lines of the first signal line are electrically connected through the first type pixel circuit electrically connected (Huang, as shown in FIGS. 7, 8, 14, 15, 17 and 18, the first pixel circuit 23 is a 7T1C pixel circuit (seven transistors and one storage capacitor). The display panel may include a first scan line 51, a second scan line 52, a light emission control signal line 53, a first power signal line 54, a second power signal line 55, a reference voltage line 56 and a data line 57. Figures 7, 8, 14, 15, 17, and 18, ¶ [0113]).
As to claim 5, Huang discloses the display substrate further comprising: a plurality of second signal lines, wherein the at least one first type pixel circuit is electrically connected with at least one second signal line (Huang, as shown in FIGS. 7, 8, 14, 15, 17 and 18, the first pixel circuit 23 is a 7T1C pixel circuit (seven transistors and one storage capacitor). The display panel may include a first scan line 51, a second scan line 52, a light emission control signal line 53, a first power signal line 54, a second power signal line 55, a reference voltage line 56 and a data line 57. Figures 7, 8, 14, 15, 17, and 18, ¶ [0113]);
the plurality of second signal lines comprise at least one of following: a data signal line (Huang, Data signal line (Vdata), Figure 18) and a first power supply line (Huang, PVDD is a first power signal input to the first power signal line 54, Figure 18, ¶ [0113]); the plurality of data signal lines and the plurality of first power supply lines extend along a first direction (there are multiple data signal lines and power supply lines to provide inputs to the separate pixel circuits); a data signal line and a first power supply line electrically connected with the first type pixel circuit are located between adjacent sub-signal lines of the first signal line (Huang, as shown in FIGS. 7, 8, 14, 15, 17 and 18, the first pixel circuit 23 is a 7T1C pixel circuit (seven transistors and one storage capacitor). The display panel may include a first scan line 51, a second scan line 52, a light emission control signal line 53, a first power signal line 54, a second power signal line 55, a reference voltage line 56 and a data line 57. Figures 7, 8, 14, 15, 17, and 18, ¶ [0113]), and orthographic projections of the data signal line and the first power supply line electrically connected with the first type pixel circuit on the base substrate are overlapped with an orthographic projection of the first type pixel circuit on the base substrate (Huang, On the plane where the substrate 341 is located, the vertical projection of the first transparent conductive layer 351 overlaps the vertical projection of the first pixel circuit 23 configured to drive the first-color light-emitting sub-pixels to emit light. Figure 14, ¶ [0102]).
As to claim 6, Huang discloses the display substrate wherein an orthographic projection of at least one of the scan signal line, the reset signal line, the initial signal line, the light emitting signal line, the data signal line, and the first power supply line on the base substrate (Huang, as shown in FIGS. 7, 8, 14, 15, 17 and 18, the first pixel circuit 23 is a 7T1C pixel circuit (seven transistors and one storage capacitor). The display panel may include a first scan line 51, a second scan line 52, a light emission control signal line 53, a first power signal line 54, a second power signal line 55, a reference voltage line 56 and a data line 57. Figures 7, 8, 14, 15, 17, and 18, ¶ [0113]) is partially overlapped with an orthographic projection of the first type light emitting element on the base substrate (Huang, On the plane where the substrate 341 is located, the vertical projection of the first transparent conductive layer 351 overlaps the vertical projection of the first pixel circuit 23 configured to drive the first-color light-emitting sub-pixels to emit light. Figure 14, ¶ [0102]).
As to claim 7, Huang discloses the display substrate wherein the plurality of first type light emitting elements at least comprise a plurality of first light emitting elements emitting light of a first color, a plurality of second light emitting elements emitting light of a second color, and a plurality of third light emitting elements emitting light of a third color (Huang, the first red sub-pixel 41, the first green sub-pixel 42 and the first blue sub-pixel 43. Figures 2, 3, and 7, ¶ [0076]);
an anode area of at least one first light emitting element among the plurality of first light emitting elements is greater than an anode area of at least one third light emitting element among the plurality of third light emitting elements, an anode area of at least one second light emitting element among the plurality of second light emitting elements is greater than the anode area of the at least one third light emitting element, and an anode area of at least one second light emitting element among the plurality of second light emitting elements is greater than an anode area of at least one first light emitting element among the plurality of first light emitting elements (Huang, The first-type first sub-pixel 21 includes a first anode 211. The first-type second sub-pixel 22 includes a second anode 221. The area of the first anode 211 is less than the area of the second anode 221. Figures 1-3, ¶ [0049])(Huang, As shown in FIGS. 2 and 3, in this embodiment, the first-type first sub-pixels 21 is configured to include the first red sub-pixel 41 and/or the first blue sub-pixel 43. That is, the area of the first anode effective region 2113 of the first red sub-pixel 41 is configured to be less than the area of the second anode effective region 2212 of the second red sub-pixel 44, and/or the area of the first anode effective region 2113 of the first blue sub-pixel 43 is configured to be less than the area of the second anode effective region 2212 of the second blue sub-pixel 46 to reduce the area of the first anode effective region 2113 of the first red sub-pixel 41 and/or reduce the area of the first anode effective region 2113 of the first blue sub-pixel 43. Then the distance between the first anode effective region 2113 of the first red sub-pixel 41 and the first anode effective region 2113 of the first-type first sub-pixel 21 adjacent to the first anode effective region 2113 of the first red sub-pixel 41 is increased, and/or the distance between the first anode effective region 2113 of the first blue sub-pixel 43 and the first anode effective region 2113 of the first-type first sub-pixel 21 adjacent to the first anode effective region 2113 of the first blue sub-pixel 43 is increased. ¶ [0078]);
the light of the first color is red light, the light of the second color is blue light, and the light of the third color is green light (Huang, the first red sub-pixel 41, the first green sub-pixel 42 and the first blue sub-pixel 43. Figures 2, 3, and 7, ¶ [0076]).
As to claim 30, Huang discloses the display substrate wherein the plurality of light emitting elements further comprise a plurality of second type light emitting elements located in the conventional display region, and the plurality of pixel circuits further comprise a plurality of second type pixel circuits located in the conventional display region (Huang, The second sub-pixel 121 located in the second display region 12 includes the second red sub-pixel 44, the second green sub-pixel 45 and the second blue sub-pixel 46 to implement the color display of the second display region 12. Figures 2 and 3, ¶ [0077]);
at least one second type light emitting element among the plurality of second type light emitting elements is electrically connected with at least one second type pixel circuit among the plurality of second type pixel circuits, and an orthographic projection of the second type light emitting element on the base substrate is overlapped with an orthographic projection of a second type pixel circuit electrically connected on the base substrate (Huang, the first-type first sub-pixel 21 also includes a first pixel opening 31. The first-type second sub-pixel 22 also includes a second pixel opening 32. The first anode 211 includes a first anode effective region 2113. The vertical projection of the first pixel opening 31 on the plane where the first anode 211 is located covers the first anode effective region 2113. The second anode 221 includes a second anode effective region 2212. The vertical projection of the second pixel opening 32 on the plane where the second anode 221 is located covers the second anode effective region 2212. The area of the first anode effective region 2113 is less than the area of the second anode effective region 2212. Figures 1-3, ¶ [0056]).
As to claim 31, Huang discloses a display apparatus, comprising a display substrate according to claim 1 (Huang, display panel and display device, Abstract, Figure 1).
Allowable Subject Matter
Claims 8-13, 15-17, 21, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 8, Huang (Chinese Pub. No. CN 113178537 A utilizing the translation of U.S. Pub. No. 2024/0074268) discloses the display substrate wherein the first type pixel circuit comprises: a plurality of transistors and at least one capacitor (Huang, as shown in FIGS. 7, 8, 14, 15, 17 and 18, the first pixel circuit 23 is a 7T1C pixel circuit (seven transistors and one storage capacitor). The display panel may include a first scan line 51, a second scan line 52, a light emission control signal line 53, a first power signal line 54, a second power signal line 55, a reference voltage line 56 and a data line 57. Figures 7, 8, 14, 15, 17, and 18, ¶ [0113]); on a direction perpendicular to the display substrate, the light-transmitting display region (Huang, first display region 11, Figures 1-3 and 16) at least comprises a semiconductor layer (Huang, active layer 71, Figure 16), a first insulation layer (Huang, gate insulating layer 72, Figure 16), a first conductive layer (Huang, gate layer 73, Figure 16), a second insulation layer (Huang, interlayer insulating layer 74, Figure 16), a second conductive layer (Huang, a source and drain layer 75, Figure 16), a third insulation layer (Huang, planarization layer 76, Figure 16),
the semiconductor layer at least comprises: active layers of the plurality of transistors of the first type pixel circuit (Huang, active layer 71, Figure 16);
the first conductive layer at least comprises: control electrodes of the plurality of transistors (Huang, gate layer 73, Figure 16) and a first electrode plate of the capacitor of the first type pixel circuit;
the second conductive layer at least comprises: a second electrode plate of the capacitor of the first type pixel circuit;
the third conductive layer at least comprises: first electrodes and second electrodes of the plurality of transistors of the first type pixel circuit and a plurality of connection electrodes (Huang, a source and drain layer 75, Figure 16);
Huang does not expressly disclose
a third conductive layer, a fourth insulation layer, a transparent conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer disposed on the base substrate;
the first conductive layer at least comprises: control electrodes of the plurality of transistors and a first electrode plate of the capacitor of the first type pixel circuit;
the transparent conductive layer at least comprises: a plurality of first signal lines, a plurality of second signal lines, and a plurality of anode connection lines, and at least one anode connection line among the plurality of anode connection lines is electrically connected with at least one first type pixel circuit and anodes of at least two first type light emitting elements emitting light of a same color; and
the fourth conductive layer at least comprises: a plurality of signal connection lines.
Additional prior art of Shang et al. (U.S. Pub. No. 2021/0320156) teaches a display device with similar pixel structure. However, Shang does not teach the specific conductive and other layers for the light-transmitting display region as required by the claim.
Additional prior art of Kim et al. (U.S. Pub. No. 2021/0366409) teaches a display device with multiple display areas. However, Kim does not teach the specific conductive and other layers for the light-transmitting display region as required by the claim.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to dependent claims 9-13, 15-17, 21, and 22, these claims are objected to for the same reasons as claim 8 as they depend upon objected dependent claim 8.
Conclusion
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/BRENT D CASTIAUX/Primary Examiner, Art Unit 2623
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