Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 11-20 are pending for examination. Claims 11 and 20 are independent.
Specification
The disclosure is objected to because of the following informalities: Para 0022 of the specification recites "ROM" without detailing what the abbreviation stands for.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“a receiving device” in claim 11.
“a transformation processing device” in claims 11-18.
“a generation device” in claims 11 and 18.
“an estimation device” in claim 11.
“an output device” in claim 11.
“a nonlinear calculation unit” in claims 12, and 15-17. Spec para 0022 provides structure “ROM.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim limitation “a receiving device" "a transformation processing device" a generation device" "an estimation device" and "an output device” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification does not describe any structures for devices. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Dependent claims 12-19 do not resolve the 112(b) rejection from independent claims 1 and 20 and are also rejected under 112(b).
Claim 12 recites the limitation "the input data" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation "the number of neuron cell circuits" in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 11 and 20 rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1
According to the first part of the analysis, in the instant case, claims 11-19 are directed to apparatus, and claim 20 is directed to a non-transitory recording medium. Thus, each of the claims falls within one of the four statutory categories (i.e., process, machine, manufacture, or composition of matter).
Regarding Claim 11:
2A Prong 1:
(This step for transforming parameters is practically performable in the human mind and is understood to be a recitation of a mental process with pen and paper (i.e., evaluation).)
(This step for generating production information is practically performable in the human mind and is understood to be a recitation of a mental process with pen and paper (i.e., evaluation).)
(This step for generating estimation information is practically performable in the human mind and is understood to be a recitation of a mental process with pen and paper (i.e., evaluation).)
2A Prong 2: This judicial exception is not integrated into a practical application.
Additional elements:
An information processing apparatus comprising: a receiving device […] a transformation processing device […] a generation device […] an estimation device […] and an output device (The apparatus comprising a receiving, transformation processing, generation, estimation, and output device is understood to be a generic computer elements - See MPEP 2106.05(f).)
a receiving device which receives an input of a machine learning parameter for a first- type neural network which has machine-learned an output corresponding to a predetermined input; (This step is directed to receiving information, which is understood to be insignificant extra-solution activity and data gathering. See MPEP 2106.05(g).)
an output device which outputs the production information and the estimate information. (This step is directed to transmitting information, which is understood to be insignificant extra-solution activity and data gathering. See MPEP 2106.05(g).)
The additional elements as disclosed above alone or in combination do not integrate the judicial exception into practical application as they are insignificant extra solution activity in combination of generic computer functions that are implemented to perform the disclosed abstract idea above.
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
An information processing apparatus comprising: a receiving device […] a transformation processing device […] a generation device […] an estimation device […] and an output device (The apparatus comprising a receiving, transformation processing, generation, estimation, and output device is understood to be a generic computer elements - See MPEP 2106.05(f).)
a receiving device which receives an input of a machine learning parameter for a first- type neural network which has machine-learned an output corresponding to a predetermined input; (This step is directed to receiving information, which is understood to be insignificant extra-solution activity and is well understood, routine and conventional activity of transmitting and receiving data as identified by the court (MPEP2106.05(d)(ll)(i))))
an output device which outputs the production information and the estimate information. (This step is directed to transmitting information, which is understood to be insignificant extra-solution activity and is well understood, routine and conventional activity of transmitting and receiving data as identified by the court (MPEP2106.05(d)(ll)(i))))
The additional elements as disclosed above in combination of the abstract idea
are not sufficient to amount to significantly more than the judicial exception as they are
well, understood, routine and conventional activity as disclosed in combination
of generic computer functions that are implemented to perform the disclosed abstract idea above.
Regarding Claim 20: see the rejection of claim 11 above. Same rationale applies.
2A Prong 2 & 2B: The claim recites another additional element “A computer readable and non-transitory recording medium which stores a program by which a computer functions as:” (mere instructions to apply the exception using a generic computer component - see MPEP 2106.05(f))
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. ("AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs", hereinafter "Xu") in view of Cao et al. (US 10,387,774 B1, hereinafter "Cao").
Regarding Claim 11
Xu discloses: An information processing apparatus comprising: ([Section 7] describes AutoDNNChip on 20 DNN models across 4 platforms (3 edge devices including edge FPGA/TPU/GPU and 2 ASIC-based accelerators).)
a receiving device which receives an input of a machine learning parameter for a first- type neural network which has machine-learned an output corresponding to a predetermined input; ([Section 3 and Fig 1-2] describes user-defined input deep neural network (DNN) with application spec & budget. Section 3 first para states “the high-level DNN descriptions trained in desired datasets”, which discloses an output corresponding to a predetermined input.)
a transformation processing device which transforms the received machine learning parameter for the first-type neural network to a machine learning parameter for a second-type neural network which is a different type ([Section 3, Section 5, and Fig 1-2] describes user-defined DNN models/datasets and application-driven specifications (i.e. first type) to generate an optimized FPGA- or ASIC-based DNN accelerator designs (i.e. a second-type neural network).)
a generation device which generates production information for producing the second- type neural network, on the basis of the transformed machine learning parameter; ([Section 3 and Fig 1-2] describes generating synthesizable Verilog/RTL for the selected accelerator design.)
an estimation device which generates estimate information regarding at least one of a scale and performance, relating to the second-type neural network produced in accordance with the production information; ([Abstract, Section 3, and Fig 1-2] describes Chip Predictor estimate energy, throughput, latency, (i.e. performance) and area (i.e. scale) overhead of DNN accelerators based on the parameters that can characterize the algorithms hardware architectures,) and
an output device which outputs the production information and the estimate information. ([Abstract, Section 3, and Fig 1-2] describes the Chip Builder generating Verilog/RTL implementation and the Chip Predictor providing predicted/estimated hardware metrics (e.g. energy and area).)
Xu does not explicitly disclose: a different type neural network from the first-type neural network.
However, Cao discloses in the same field of endeavor: a second-type neural network which is a different type neural network from the first-type neural network ([Abstract, Col 8 lines 19-40] describes converting a deep neural network (i.e. CNN) into a spiking neural network (SNN).)
It would have been obvious to a person of ordinary skill in art before the effective filling date of the invention to implement the function of converting neural networks to spiking neural networks disclosed by Cao into the method of AutoDNNchip disclosed by Xu to transform a first type neural network to a different type of neural network. The modification would have been obvious because one of the ordinary skills of the art would be motivated to utilize the feature of converting neural networks to spiking neural networks disclosed by Cao as all the references are in the field of machine learning. A person of ordinary skill of the art would have been motivated to perform the combination for being able to convert a neural network into a SNN implemented on neuromorphic hardware resulting in reduced power consumption.
Regarding Claim 20
Xu in view of Cao discloses: A computer readable and non-transitory recording medium which stores a program by which a computer functions as: (Claim 20 is a non-transitory recording medium claim that corresponds to claim 11 and the rest of the limitations are rejected on the same ground)
Claim(s) 12-13, 15-16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Cao and Duong et al. (US 10,977,338 B1, hereinafter "Duong").
Regarding Claim 12
Xu in view of Cao discloses: An information processing apparatus according to claim 11, wherein the first-type neural network is a deep learning neural network, ([Section 3 and Fig 1-2], Xu describes a input deep neural network (DNN)362.)
Xu in view of Cao does not explicitly discloses: the transformation processing device is a transformation processing device which virtually sets a neuron cell circuit for an output node of each layer of the first-type neural network, at least one of the set neuron cell circuits is provided with an input port, an inverter, an adder, and a nonlinear calculation unit, and the inverter is an inverter which invers a sign of the input data, when the transformation processing device sets each of the neuron cell circuits, on the basis of weight information for an input node connected to the output node of the corresponding first-type neural network, the transformation processing device arranges an input port corresponding to the input node, and sets each of the arranged input port so that the data input to the input port is directly output, or the data input to the input port is output after being inverted by the provided invertor, the transformation processing device sets the adder so that the adder accumulates the directly output data or the data output through the inverter, and the transformation processing device sets the nonlinear calculation unit so that the nonlinear calculation unit receives the accumulated value output from the adder, and outputs a function value of a predetermined nonlinear function corresponding to the received accumulated value.
However, Duong discloses in the same field of endeavor: the transformation processing device is a transformation processing device which virtually sets a neuron cell circuit for an output node of each layer of the first-type neural network, ([Col 11 lines 18-67 and Fig 5] describes a partial dot product computation circuits (i.e. neural cell circuit))
at least one of the set neuron cell circuits is provided with an input port, an inverter, an adder, and a nonlinear calculation unit, and the inverter is an inverter which invers a sign of the input data, ([Col 11 lines 20-25, Col 12 lines 65-67, Col 14 lines 11-67, and Fig 5-7] describes a partial dot product computation circuit provided input cicuirt/multiplexers, binary inversions, adder trees, and activation post processor to apply nion-linear activation function)
when the transformation processing device sets each of the neuron cell circuits, on the basis of weight information for an input node connected to the output node of the corresponding first-type neural network, ([Col 11 lines 18-67 and Fig 5] describes assigning input values to dot product inputs based on the predefined weights.)
the transformation processing device arranges an input port corresponding to the input node, and sets each of the arranged input port so that the data input to the input port is directly output, or the data input to the input port is output after being inverted by the provided invertor, ([Col 11 lines 18-67 and Fig 5-7] describes for a positive weight the circuit passes the input value to the adder, for a negative weight it passes the binary inversion of the input value.)
the transformation processing device sets the adder so that the adder accumulates the directly output data or the data output through the inverter, and the transformation processing device sets the nonlinear calculation unit so that the nonlinear calculation unit receives the accumulated value output from the adder, and outputs a function value of a predetermined nonlinear function corresponding to the received accumulated value. ([Col 11 lines 18-67, Col 12 lines 65-67, Col 14 lines 11-67, and Fig 5-7] describes further processing the full adder and adder tree and post processor applies nodes non linear activation function.
It would have been obvious to a person of ordinary skill in art before the effective filling date of the invention to implement the function of Circuit for dot product computation disclosed by Duong into the method of Xu in view of Cao to describe neuron cell circuits provided with an input port, an inverter, an adder, and a nonlinear calculation unit. The modification would have been obvious because one of the ordinary skills of the art would be motivated to utilize the feature of Circuit for dot product computation disclosed by Duong as all the references are in the field of neural networks. A person of ordinary skill of the art would have been motivated to perform the combination for being able to provide circuitry that performs multiply-accumulation.
Regarding Claim 13
Xu in view of Cao and Duong discloses: An information processing apparatus according to claim 12, wherein when the transformation processing device sets each of the neuron cell circuits, the transformation processing device executes a pruning process by which, an input port is set only when the input port corresponds to the input node with weight information larger than a predetermined threshold value, among the input nodes connected to the output node corresponding to the first-type neural network. ([Col 11 lines 20-35 and Fig 5], Duong describes sparsity constraint for mandating that a weight values equal to zero (i.e. pruning))
Regarding Claim 15
Xu in view of Cao and Duong discloses: An information processing apparatus according to claim 12, wherein when the transformation processing device sets each of the neuron cell circuits, the transformation processing device sets a weight value corresponding to the input port set for each neuron cell circuit, and thereafter, sets a nonlinear function calculated by the nonlinear calculation unit set for each neuron cell circuit by a machine learning process using a predetermined training information. ([Col 11 lines 18-67 and Fig 5-7], Doung describes for a positive weight the circuit passes the input value to the adder, for a negative weight it passes the binary inversion of the input value, and further to a non-linear activation function.)
Regarding Claim 16
Xu in view of Cao and Duong discloses: An information processing apparatus according to claim 15, wherein when the transformation processing device performs machine learning of the nonlinear function calculated by the nonlinear calculation unit, the transformation processing device sets the nonlinear function as a linear sum of a predetermined plurality of types of nonlinear functions, and sets a coefficient value for multiplying the nonlinear function of each type by machine learning. ([Col 4 lines 60-67 – Col 5 lines 1-65 and Fig 1-3], Duong describes linear component for nonlinear activations.)
Regarding Claim 18
Xu in view of Cao and Duong discloses: An information processing apparatus according to claim 12, wherein the production information generated by the generation device is production information for producing each of the neuron cell circuits set by the transformation processing device as a hardware, and is expressed by a hardware description language. ([Section 3 and Fig 1-2], Xu describes generating synthesizable Verilog/RTL for the selected accelerator design.)
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Cao, Duong, and Zhu et al (US 2020/0302283 A1, hereinafter "Zhu").
Regarding Claim 17
Xu in view of Cao and Duong discloses: An information processing apparatus according to claim 12 wherein when the transformation processing device sets each of the neuron cell circuits,
Xu in view of Cao and Duong does not explicitly disclose: the transformation processing device sets the number of bits of the output from the nonlinear calculation unit of the neuron cell circuit to be set, corresponding to the position of a layer in the first-type neural network which includes the output node corresponding to the neuron cell circuit to be set.
However, Zhu discloses in the same field of endeavor: the transformation processing device sets the number of bits of the output from the nonlinear calculation unit of the neuron cell circuit to be set, corresponding to the position of a layer in the first-type neural network which includes the output node corresponding to the neuron cell circuit to be set. ([Para 0059-0060, 0071-0079, Fig 3 and Fig 7] describes activation function outputs and setting activation value bit width, per layer bit width, and using different first/second layer width.)
It would have been obvious to a person of ordinary skill in art before the effective filling date of the invention to implement the function of Mixed Precision Training disclosed by Zhu into the method of Xu in view of Cao and Duong to set a number of bits. The modification would have been obvious because one of the ordinary skills of the art would be motivated to utilize the feature of Mixed Precision Training disclosed by Zhu as all the references are in the field of neural networks. A person of ordinary skill of the art would have been motivated to perform the combination for being able to Storage reduce storage requiring fewer bits to store weights, activations, and other values used during ANN training.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Umuroglu et al. (US 20200401882 A1) describes defining hardware building blocks for neural networks. Driscoll (US 2020/0210832 A1, hereinafter "Driscoll") describes adapting a neural network on a hardware platform.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TEWODROS E MENGISTU whose telephone number is (571)270-7714. The examiner can normally be reached Mon-Fri 9:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ABDULLAH KAWSAR can be reached at (571)270-3169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TEWODROS E MENGISTU/Primary Examiner, Art Unit 2127
