Prosecution Insights
Last updated: October 25, 2026
Application No. 18/686,082

ENHANCED COOLING PACKAGE FOR IMPROVED THERMAL MANAGEMENT FOR ELECTRICAL COMPONENTS

Non-Final OA §103
Filed
Feb 23, 2024
Priority
Aug 26, 2021 — nonprovisional of PCTUS2021047758
Examiner
HOQUE, MOHAMMAD M
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Vishay General Semiconductor LLC
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
658 granted / 771 resolved
+17.3% vs TC avg
Moderate +9% lift
Without
With
+9.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
29 currently pending
Career history
806
Total Applications
across all art units

Statute-Specific Performance

§103
55.4%
+15.4% vs TC avg
§102
26.0%
-14.0% vs TC avg
§112
16.9%
-23.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 771 resolved cases

Office Action

§103
DETAILED ACTION Examiner’s Note Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182. Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Election/Restrictions Applicant’s election without traverse of Invention I (semiconductor device), reflected in claims 1-21 in the reply filed on 08/17/2026 is acknowledged. Claims 22-30 are withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group. Restriction of species is withdrawn here. Abstract The abstract filed 02/23/2024 appears to be NOT acceptable. Applicant is reminded of the proper content of an abstract of the disclosure. A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art. If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives. Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps. Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length. See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts. Drawings The drawings are objected to because the component pointed in fig. 2 as below doesn’t have any reference number. This is not clear what component matching the descriptions in the specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. PNG media_image1.png 508 834 media_image1.png Greyscale Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 3-18 are rejected under 35 U.S.C. 103 as being unpatentable over WATANABE MASAKAZU et al. (JP 2009267054 A, hereinafter Watanabe’054) in view of Yoneda et al. (JP H06349985 A, hereinafter Yoneda’985). Regarding independent claim 1, Watanabe’054 teaches, “ An electrical component package (10, figs. 1-5, related descriptions) arranged for mounting on a printed circuit board, the electrical component package (10) comprising: an electrical component (18, fig. 1) having a first side with at least one electrical contact (source electrode 30A, gate electrode 30B) and a second side opposite the first side with at least one electrical contact (drain electrode); a lead frame (14, 12) arranged for receiving and electrically connecting to the second side of electrical component (18); a conductive clip (16A, metal connection plates) having a first end electrically connected to the first side of the electrical component (18) and having a portion extending from the first end to electrically connect with at least a first terminal lead (12A); a second terminal lead (12B) extending from the electrical component package; a packaging material (24) encapsulating the electrical component (18) and conductive clip (16A), and at least a portion of the first terminal lead (12A) and at least a portion of the second terminal leads (12B); and, a heat sink (14, 20, 22) comprising a first planar portion (14, 20, 22) extending from the lead frame, ((a second planar portion in spaced relation from the packaging material defining a gap therebetween, and a fold portion extending between the first and second planar portions;)) wherein the electrical component package (10, fig. 3) comprises a top side (top surface of sealing resin 24) and a bottom side, wherein the lead frame (14, 12) is arranged along either the top side or the bottom side (bottom side) of the electrical component package (10), and wherein the first planar portion (14) of the heat sink extends from the lead frame (14, 12) along either the top side or the bottom side (bottom side) of the electrical component package”. PNG media_image2.png 1051 824 media_image2.png Greyscale Regarding, ‘An electrical component package arranged for mounting on a printed circuit board’, the examiner notes that MPEP 2111.04 states that claim scope is not limited by claim language that suggests or makes optional but does not require steps to be performed, or by claim language that does not limit a claim to a particular structure. It appears that the claim language “arranged for mounting” does not limit a claim to a particular structure. An arrangement can be made for mounting the electrical component package on a printed circuit board, but it is not clear to the examiner that the mounting is actually performed, i.e., the electrical component package is mounted on the printed circuit board (final structure). Appropriate correction would clarify the metes and bounds of the claim. Referring to fig. fig. 3, Watanabe’054 teaches a heat sink (14, 20, 22) comprising a first planar portion (14, 20, 22) extending from the lead frame (14, 12). But Watanabe’054 is silent upon the provision of wherein, a second planar portion in spaced relation from the packaging material defining a gap therebetween, and a fold portion extending between the first and second planar portions. However, Yoneda’985 teaches a similar package (‘semiconductor device’, fig. 1) comprising: a heat sink (6) comprising a first planar portion (see annotation) extending from the lead frame (2), a second planar portion (see annotation) in spaced relation from the packaging material defining a gap therebetween, and a fold portion (see annotation) extending between the first and second planar portions; Watanabe’054 and Yoneda’985 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Watanabe’054 with the features of Yoneda’985 because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Watanabe’054 and Yoneda’985 to include heat sink comprising a second planar portion and a fold portion according to the teachings of Yoneda’985 with a motivation of cooling the entire device uniformly. Regarding claim 3, Watanabe’054 modified with Yoneda’985 further teaches, “The electrical component package of claim 1, wherein the fold portion is integral with the first planar portion and the second planar portion (fig. 1, Yoneda’985). Regarding claim 4, Watanabe’054 modified with Yoneda’985 further teaches, “The electrical component package of claim 1, wherein the heat sink includes at least one through hole (10, fig. 1, Yoneda’985) for receiving the packaging material”. Regarding claim 5, Watanabe’054 modified with Yoneda’985 further teaches, “The electrical component package of claim 4, wherein the at least one through hole (10, fig. 1, Yoneda’985) comprises a closed through hole (closed with element 9)”. Regarding claims 6-8, Watanabe’054 teaches, the electrical component is a diode (page 4, 7, claim 2). This is known in the relevant field, that a diode has two terminals-anode and a cathode. This is also conventional to place the anode and the cathode either on the top and bottom side of the diode or on the bottom and top side of the diode. Watanabe’054 also teaches using conductive clip to connect the anode and the cathode with the terminal leads. Regarding claim 9, Watanabe’054 modified with Yoneda’985 further teaches, “The electrical component package of claim 1, wherein the first terminal lead and the second terminal lead extend to a position that is adapted to contact the printed circuit board (see the rejection of claim 1 about the printed circuit board) ”. Regarding claim 10, Watanabe’054 modified with Yoneda’985 further teaches, “The electrical component package of claim 1, wherein the first side of the electrical component (18, Watanabe’054) is an anode, and the second side of the electrical component is a cathode, and wherein the heat sink (14, 20) is part of the cathode”. Regarding claim 11, Watanabe’054 modified with Yoneda’985 further teaches, “The electrical component package of claim 1, wherein the first side of the electrical component is a cathode, and the second side of the electrical component is an anode, and wherein the heat sink (14, 20) is part of the anode”. Regarding claim 12, Watanabe’054 modified with Yoneda’985 further teaches, “The electrical component package of claim 1, wherein the electrical component (18, Watanabe’054) comprises a diode (‘a diode’)”. Regarding claim 13, Watanabe’054 modified with Yoneda’985 further teaches, “The 13. The electrical component package of claim 1, wherein the second planar portion (fig. 3-4, Yoneda’985) of the heat sink is generally rectangular in shape”. Regarding claim 14, Watanabe’054 modified with Yoneda’985 further teaches, “The electrical component package of claim 1, further comprising a central pin (12C, fig. 1, Watanabe’054) situated between the first terminal lead (12A) and the second terminal lead (12B)”. Regarding claim 15, Watanabe’054 modified with Yoneda’985 further teaches, “The electrical component package of claim 1, wherein the first planar portion and the second planar portion of the heat sink are substantially parallel (Yoneda’985, fig. 1)”. Regarding claim 16, Watanabe’054 modified with Yoneda’985 further teaches, “The electrical component package of claim 1, wherein the lead frame (6, fig. 1, Yoneda’985) extends along the bottom side of the electrical component package, and wherein the first planar portion of the heat sink extends from the lead frame along the bottom side of the electrical component package, and wherein the second planar portion of the heat sink extends from the fold portion along the top side of the electrical component package. Regarding claim 17, Watanabe’054 modified with Yoneda’985 further teaches, “The electrical component package of claim 1, wherein the lead frame extends along the top side of the electrical component package, and wherein the first planar portion of the heat sink extends from the lead frame along the top side of the electrical component package, and wherein the second planar portion of the heat sink extends from the fold portion along the bottom side of the electrical component package (rotate the devices of Watanabe’054 modified with Yoneda’985 by 180°)”. Regarding claim 18, Watanabe’054 modified with Yoneda’985 further teaches, “The electrical component package of claim 1, wherein the electrical component (18, Watanabe’054) is a semiconductor chip”. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe’054 modified with Yoneda’985 as applied to claim 1 as above, and further in view of Noquil et al. (US 20070267728 A1, hereinafter Noquil’728). Regarding claim 2, Watanabe’054 modified with Yoneda’985 teaches all the limitations described in claim 1. But Watanabe’054 modified with Yoneda’985 is silent upon the provision of wherein the fold portion includes a cut-out portion to define opposed arms extending from the first planar portion to the second planar portion. However, Noquil’728 teaches a similar device (fig. 1A), wherein the fold portion includes a cut-out portion to define opposed arms extending from the first planar portion to the second planar portion. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Watanabe’054 modified with Yoneda’985 and Noquil’728 to include cut-out portion in the fold portion of the heat sink according to the teachings of Noquil’728 with a general motivation of reducing material cost and stress. Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe’054 modified with Yoneda’985 as applied to claim 1 as above, and further in view of Patel (US 5396403 A, hereinafter Patel’403). Regarding claim 19, Watanabe’054 modified with Yoneda’985 teaches all the limitations described in claim 1. But Watanabe’054 modified with Yoneda’985 is silent upon the provision of wherein the electrical component package of claim 1, further comprising an external heat sink arranged for positioning over the electrical component package. However, Patel’403 teaches a similar device (fig. 1A), comprising an external heat sink (23) arranged for positioning over the electrical component package. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Watanabe’054 modified with Yoneda’985 and Patel’403 to include two layers of heat sink according to the teachings of Patel’403 with a general motivation of increase the cooling of the package structure. Regarding claim 20, Watanabe’054 modified with Yoneda’985 and Patel’403 further teaches, “The electrical component package of claim 19, wherein the external heat sink (23) is formed of a thermally conductive material”. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe’054 modified with Yoneda’985 as applied to claim 1 as above, and further in view of Sato (JP 09139444 A, hereinafter Sato’444). Regarding claim 21, Watanabe’054 modified with Yoneda’985 teaches all the limitations described in claim 1. But Watanabe’054 modified with Yoneda’985 is silent upon the provision of wherein the packaging material includes a recessed portion. However, Sato’444 teaches a similar electrical component package (fig. 6), wherein the packaging material includes a recessed portion (24a). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Watanabe’054 modified with Yoneda’985 and Sato’444 to include a recessed portion in the packaging material according to the teachings of Sato’444 with a motivation of improving heat radiating effect with low costs without changing a lead pattern. See Sato’444, Abstract. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Feb 23, 2024
Application Filed
Sep 22, 2025
Response after Non-Final Action
Oct 15, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+9.3%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 771 resolved cases by this examiner. Grant probability derived from career allowance rate.

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