DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9, and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 11,469877 (Raj).
For claim 1, Raj figure 3 teaches a DLL circuit (372) comprising: a first delay line (314) having a first delay buffer that provides a delay corresponding to a control voltage (output of 312) to an input clock signal (output of 302), and configured to output an output clock signal (Fout) via the first delay buffer;
a control voltage generation unit (306, 324, 310a, 310b, and 312) having a phase comparator (306 and 324) that compares phases of the input clock signal and the output clock signal, and configured to generate the control voltage based on an output of the phase comparator;
a charge storage unit (310a and 310b) configured to store charges for holding the control voltage; and
a drive control unit (FSM 374) configured to output a drive control signal (376a and 376b) for stopping an operation of the phase comparator based on a determination result regarding a delay-locked state (see, e.g. column 9, line 25 “The PFD 306, when enabled by the switch 308a with… a control signal 376a,”).
For claim 2, Raj further teaches the drive control unit determines that the delay-locked state is created when a first time elapsed since the start of delay lock control (see, e.g., column 11 line 31, “Once lock is achieved, a lock detection circuitry 374a of the FSM 374 may generate a signal (not shown) indicating that the PFD-based PLL is both frequency and phase locked to the RX reference clock signal 322.”).
For claim 3, Raj further teaches the drive control unit determines that the delay-locked state is created when a difference between the control voltage and a target voltage is less than a predetermined value (when a DLL reaches lock that means that the difference between the input and output has dropped below a certain threshold).
For claim 4, Raj further teaches the control voltage generation unit includes a charge pump circuit (charge pumps 310a and 310b) configured to perform current control according to the output of the phase comparator, and the drive control unit stops an operation of the charge pump circuit based on the determination result of the delay-locked state (lock detection unit disables the charge pump’s inputs).
For claim 5, Raj further teaches the drive control unit stops the operation of the first delay line based on a determination result of the delay-locked state (performed through signal 376h).
For claim 6, Raj further teaches the drive control unit restarts the operation of the phase comparator according to a predetermined condition being established after stopping the operation of the phase comparator (see, e.g., column 10 line 47, “The PD-based PLL may be enabled or disabled by controlling a switch 308b arranged between the PD 324 and the second charge pump system 310b with, for example, a control signal 376b generated by the FSM 374.”).
For claim 7, Raj further the predetermined condition is the elapse of a second time (see, e.g., specification, FSM will enable a certain time after lock has been achieved according to NVM).
For claim 9, Raj further teaches the charge storage unit holds charges using a capacitor (the capacitors in 312) included in the low-pass filter.
For claim 11, Raj figure 3 further teaches the first delay line includes a plurality of the first delay buffers, the first delay line outputs an output data signal via N first delay buffers, and the output clock signal is a signal output via M first delay buffers different from the N delay buffers (314 outputs signals of different phases, that is created by running the signal through different number of delay units).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0112641 (Li) in view of Raj.
For claim 15, Li abstract teaches a light-emitting device comprising:
a light-emitting unit (“light emitting device can be an LED display”); and
a light emission pulse generation unit (“to drive an [sic] light emitting device”) configured to generate a light emission pulse signal to be supplied to the light-emitting unit and having a DLL circuit (“a multiphase PLL or DLL”).
However, Li does not explicitly teach how to implement its DLL.
Nevertheless, Raj figure 3 teaches a DLL circuit (372) including a first delay line (314) having a first delay buffer that provides a delay corresponding to a control voltage (output of 312) to an input clock signal (output of 302) and configured to output an output clock signal (Fout) via the first delay buffer;
a control voltage generation unit (306, 324, 310a, 310b, and 312) having a phase comparator (306 ad 324) that compares phases of the input clock signal and the output clock signal, and configured to generate the control voltage based on an output of the phase comparator;
a charge storage unit (310a and 310b) that stored charges for holding the control voltage; and
a drive control unit (FSM 374) configured to output a drive control signal (376) for stopping an operation of the phase comparator based on a determination result regarding a delay-locked state (see, e.g. column 9, line 25 “The PFD 306, when enabled by the switch 308a with… a control signal 376a,”).
Allowable Subject Matter
Claims 8, 10, 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D HOUSTON whose telephone number is (571)270-3901. The examiner can normally be reached M-F 10-7 CST.
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/ADAM D HOUSTON/Primary Examiner, Art Unit 2842