DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 and 12-21 are pending for examination. Claim 11 was cancelled. Claims 16-21 are newly added.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) are: “an artificial neural network configured to", “a first control module” and “second control module”, “processing unit” and “inhibiter” in claims 1, 12-13 and 15, “adjustment module” in claim 6, “a first conversion module” and “a second conversion module” in claim 8.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Claim limitations “an artificial neural network configured to", “a first control module” and “second control module”, “processing unit” and “inhibiter” in claims 1, 12-13 and 15, “adjustment module” in claim 6, “a first conversion module” and “a second conversion module” in claim 8 invokes 35 U.S.C. 112(f). The specification page 7 discloses that “The terms "node", "cell" or "neural cell" may refer to a neuron, such as a neuron of an artificial neural network, another processing element, such as a processor, of a network of processing elements or a combination thereof”. And page 13 of the specification discloses “The method may be implemented in analog hardware/electronics circuit, in digital circuits, e.g., gates and flipflops, in mixed signal circuits, in software and in any combination thereof.” as performing corresponding structure. However, said “an artificial neural network configured to", “a first control module” and “second control module”, “processing unit” and “inhibiter” in claims 1, 12-13 and 15, “adjustment module” in claim 6, “a first conversion module” and “a second conversion module” in claim 8 without the detail about the means to accomplish the functions are not an adequate disclosure of corresponding structure (i.e., they are general purpose computer and they are not sufficient structure to be corresponding structure under 112(f). That is, the general purpose computer must be transformed into a specially programmed computer by way of an algorithm). MPEP § 2181(II)(B) specifically indicated that “For a computer-implemented 35 U.S.C. 112(f) claim limitation, the specification must disclose an algorithm for performing the claimed specific computer function, or else the claim is indefinite under 35 U.S.C. 112(b). See Net MoneyIN, Inc. v. Verisign. Inc., 545 F.3d 1359, 1367, 88 USPQ2d 1751, 1757 (Fed. Cir. 2008). See also In re Aoyama, 656 F.3d 1293, 1297, 99 USPQ2d 1936, 1939 (Fed. Cir. 2011) ("[W]hen the disclosed structure is a computer programmed to carry out an algorithm, ‘the disclosed structure is not the general purpose computer, but rather that special purpose computer programmed to perform the disclosed algorithm.’") (quoting WMS Gaming, Inc. v. Int’l Game Tech., 184 F.3d 1339, 1349, 51 USPQ2d 1385, 1391 (Fed. Cir. 1999))” and “The corresponding structure is not simply a general purpose computer by itself but the special purpose computer as programmed to perform the disclosed algorithm. Aristocrat, 521 F.3d at 1333, 86 USPQ2d at 1239. Thus, the specification must sufficiently disclose an algorithm to transform a general purpose microprocessor to the special purpose computer” Therefore, the claims (i.e., 1-10 and 12-21) are indefinite and is rejected under 35 U.S.C. 112(b).
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f);
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 and 12-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement.
The claims 1-10 and 12-21 contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention. As described above in 112(f) (i.e., “an artificial neural network configured to", “a first control module” and “second control module”, “processing unit” and “inhibiter” in claims 1, 12-13 and 15, “adjustment module” in claim 6, “a first conversion module” and “a second conversion module” in claim 8), the disclosure does not provide adequate structure to perform the claimed functions. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. See MPEP § 2181(II)(B) “When a claim containing a computer-implemented 35 U.S.C. 112(f) claim limitation is found to be indefinite under 35 U.S.C. 112(b) for failure to disclose sufficient corresponding structure (e.g., the computer and the algorithm) in the specification that performs the entire claimed function, it will also lack written description under 35 U.S.C. 112(a)”.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10 and 12-21 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
As per claims 1-10 and 12-21:
As described above in 112(f) (i.e., “an artificial neural network configured to", “a first control module” and “second control module”, “processing unit” and “inhibiter” in claims 1, 12-13 and 15, “adjustment module” in claim 6, “a first conversion module” and “a second conversion module” in claim 8) without the detail about the means to accomplish the functions are not an adequate disclosure of corresponding structure. The MPEP § 2181(II)(B) specifically indicated that “For a computer-implemented 35 U.S.C. 112(f) claim limitation, the specification must disclose an algorithm for performing the claimed specific computer function, or else the claim is indefinite under 35 U.S.C. 112(b). See Net MoneyIN, Inc. v. Verisign. Inc., 545 F.3d 1359, 1367, 88 USPQ2d 1751, 1757 (Fed. Cir. 2008). See also In re Aoyama, 656 F.3d 1293, 1297, 99 USPQ2d 1936, 1939 (Fed. Cir. 2011) ("[W]hen the disclosed structure is a computer programmed to carry out an algorithm, ‘the disclosed structure is not the general purpose computer, but rather that special purpose computer programmed to perform the disclosed algorithm.’") (quoting WMS Gaming, Inc. v. Int’l Game Tech., 184 F.3d 1339, 1349, 51 USPQ2d 1385, 1391 (Fed. Cir. 1999))”. Therefore, the claims (i.e., 1-10 and 12-21) are indefinite and is rejected under 35 U.S.C. 112(b).
As per claim 1:
In line 8, it recites the phrase “a processing unit input”. However, prior to this phrase at line 4, it recites “processing unit input”. Thus, it is unclear whether the second recitation of “a processing unit input” is the same or different from the first recitation of “processing unit input”.
As per claim 2:
Line 3, “the gain” lacks antecedence basis
As per claims 4 and 5 (line# refers to claim 4):
Line 1, it recites “the input”, however, prior to this phrase in claim 1, it recites “processing unit input”, “system input” and “scaled input”. Thus, it is unclear whether the recitation of “the input” is the same or different from the recitations of “processing unit input”, “system input” and “scaled input”. Same applies to claim 5.
As per claim 9:
Line 4, “the artificial neural network system” lacks antecedence basis
As per claim 10:
Line 4, “the system” lacks antecedence basis.
As per claim 12:
Line 5, “the population activity” lacks antecedence basis.
As per claim 20:
Line 2, “the activity values” and “the activity value” lacks antecedence basis.
As per claims 2-10, 13-14 and 16-21:
They are computer-implemented method, artificial neural network and first control module claims that depend from rejected claims and do not resolve the deficiencies thereof and are therefore rejected for the same reasons as above.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 9-10, 12-13, 15-16, 18 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over CANOY et al. (US Pub. 2015/0178617 A1) in view of PARK et al. (US Pub. 2021/0012207 A1) and further in view of Wang et al. (US Patent. 10,558,908 B2).
CANOY was cited in the IDS filed on 02/27/2024.
As per claim 1, CANOY teaches the invention substantially as claimed including A computer-implemented method for managing activity on an artificial neural network configured to process data, the artificial neural network comprising a first control module, a second control module, a processing unit configured to produce processing unit output responsive to receiving processing unit input, wherein the processing unit comprises one or more nodes of the artificial neural network, and an inhibiter (CANOY, Abstract, A method of monitoring a neural network includes monitoring activity of the neural network. The method also includes detecting a condition based on the activity. The method further includes performing an exception event based on the detected condition; Fig. 5, 504, (As processing unit), 506 (as first control module), 508 (as second control module), 510 (as inhibiter); [0028] The transfer of spikes from one level of neurons (as one or more nodes of artificial neural network) to another may be achieved through the network of synaptic connections (or simply "synapses") 104, as illustrated in FIG. 1. Relative to the synapses 104, neurons of level 102 may be considered pre-synaptic neurons and neurons of level 106 may be considered post-synaptic neurons. The synapses 104 may receive output signals (i.e., spikes) from the level 102 neurons and scale those signals according to adjustable synaptic weights w.sub.1.sup.(i,i+1),.., w.sub.P.sup.(i,i+1) where P is a total number of synaptic connections between the neurons of levels 102 and 106 and i is an indicator of the neuron level. In the example of FIG. 1, i represents neuron level 102 and i+1 represents neuron level 106; [0034] The neuron 202 may combine the scaled input signals and use the combined scaled inputs to generate an output signal 208 (i.e., a signal Y). The output signal 208 may be a current, or a voltage, real-valued or complex-valued. The output signal may be a numerical value with a fixed-point or a floating-point representation. The output signal 208 may be then transferred as an input signal to other neurons of the same neural system, or as an input signal to the same neuron 202, or as an output of the neural system; see Fig. 1, as to processing the input to generate output; also see [0041]) , the method comprising:
measuring, by the first control module, a population activity of the processing unit responsive to the processing unit receiving a processing unit input and producing a processing unit output, wherein the population activity of the processing unit is determined from activity levels of one or more nodes in a population of the processing unit (CANOY, Fig. 5, 506 activity monitor (as first control module); [0066] A typical neural monitor reacts to specified activity. For example, a neural monitor may cut the power to a CPU when the system temperature is above a specified value. One aspect of the present disclosure is directed to a neural monitor that detects instability or imbalance conditions in one or more neural elements and/or processes based on neural activity. That is, the neural monitor may monitor activity patterns of a neural network to determine whether the activity is excepted (e.g., within a range of baseline activity). More specifically, the activity patterns may indicate the potential for a system failure and/or component failure. The neural monitor may be referred to as a probabilistic neural monitor; [0070] the neural model execution engine 504 is a processing block that executes the neural network (e.g., neural model). The activity monitor 506 monitors the execution of the neural model to detect conditions that specify a response. That is, the activity monitor 506 may monitor the activity of the neural model execution engine 504 and may trigger the activity regulator 508 to regulate (e.g., control) the neural model execution engine 504 to mitigate the detected condition. Alternatively, or in addition, the neural model execution engine 504 may trigger the reset block 510 to reset the neural model execution engine 504);
providing, by the first control module, a first control signal, the first control signal being based on the processing unit output produced by the processing unit processing the processing unit input and based on the measured population activity of the processing unit (CANOY, Fig. 5, see arrow from 506 to 508 activity regulator; [0070] the neural model execution engine 504 is a processing block that executes the neural network (e.g., neural model). The activity monitor 506 monitors the execution of the neural model to detect conditions that specify a response. That is, the activity monitor 506 may monitor the activity of the neural model execution engine 504 and may trigger (as providing first control signal) the activity regulator 508 to regulate (e.g., control) the neural model execution engine 504 to mitigate the detected condition. Alternatively, or in addition, the neural model execution engine 504 may trigger the reset block 510 to reset the neural model execution engine 504);
scaling, by the second control module, the system input, based on the first control signal, thereby providing a scaled input to the processing unit in a next time step (CANOY, Fig. 5, see arrow from 506 to 508 activity regulator (as received by the second control module); [0072] the activity regulator 508 controls (e.g., corrects) the execution of the neural model execution engine 504 to mitigate the exception condition. In one configuration, the activity regulator 508 reconfigures the neural model execution engine 504 to mitigate the exception condition. That is, the activity regulator 508 may change the connectivity of the neurons in the neural model execution engine 504. Alternatively, or in addition, the activity regulator 508 may change the number of active neurons and/or change a probabilistic neuron. In another configuration, the activity regulator 508 disables blocks of neurons of the neural model execution engine 504 to mitigate the exception condition. In yet another configuration, the activity regulator 508 applies a correction factor to the neural model execution engine 504 to mitigate the exception condition. In still another aspect, the activity regulator 508 drops neuron spikes. In still a further aspect, the activity regulator 508 reads out network parameters, values, connectivity, and/or history of last time prior to the exception event. In still yet another aspect of the present disclosure, the activity regulator 508 may adjust the gains of neural modulators (e.g., global data) that affect the execution of a neural model. Alternatively, or in addition to, the activity regulator 508 may also adjust the gains to affect the rate of change of system parameters, such as spike generation or internal neuron state; [0028] The transfer of spikes from one level of neurons to another may be achieved through the network of synaptic connections (or simply "synapses") 104, as illustrated in FIG. 1. Relative to the synapses 104, neurons of level 102 may be considered pre-synaptic neurons and neurons of level 106 may be considered post-synaptic neurons. The synapses 104 may receive output signals (i.e., spikes) from the level 102 neurons and scale those signals according to adjustable synaptic weights w.sub.1.sup.(i,i+1), . . . , w.sub.P.sup.(i,i+1) where P is a total number of synaptic connections between the neurons of levels 102 and 106 and i is an indicator of the neuron level. In the example of FIG. 1, i represents neuron level 102 and i+1 represents neuron level 106. Further, the scaled signals may be combined as an input signal of each neuron in the level 106. Every neuron in the level 106 may generate output spikes 110 based on the corresponding combined input signal. The output spikes 110 may be transferred to another level of neurons using another network of synaptic connections; also see [0033] These input signals may be delivered to the neuron 202 through synaptic connections that scale the signals according to adjustable synaptic weights 206.sub.1-206.sub.N (W.sub.1-W.sub.N), where N may be a total number of input connections of the neuron 202; [0041] because a neuron generally produces an output spike when many of its inputs occur within a brief period, (i.e., inputs being sufficiently cumulative to cause the output), the subset of inputs that typically remains includes those that tended to be correlated in time. In addition, because the inputs that occur before the output spike are strengthened, the inputs that provide the earliest sufficiently cumulative indication of correlation will eventually become the final input to the neuron);
utilizing the processing unit output as a system output (CANOY, [0034] The neuron 202 may combine the scaled input signals and use the combined scaled inputs to generate an output signal 208 (i.e., a signal Y). The output signal 208 may be a current, or a voltage, real-valued or complex-valued. The output signal may be a numerical value with a fixed-point or a floating-point representation. The output signal 208 may be then transferred as an input signal to other neurons of the same neural system, or as an input signal to the same neuron 202, or as an output of the neural system);
checking if the measured population activity of the processing unit is larger than a target population activity (CANOY, [0066] A typical neural monitor reacts to specified activity. For example, a neural monitor may cut the power to a CPU when the system temperature is above a specified value. One aspect of the present disclosure is directed to a neural monitor that detects instability or imbalance conditions in one or more neural elements and/or processes based on neural activity. That is, the neural monitor may monitor activity patterns of a neural network to determine whether the activity is excepted (e.g., within a range of baseline activity) (as checking if the measured population activity of the processing unit is larger than a target population activity (i.e., out of range of baseline activity). More specifically, the activity patterns may indicate the potential for a system failure and/or component failure. The neural monitor may be referred to as a probabilistic neural monitor); and
wherein responsive to the measuring determining the measured population activity of the processing unit is larger than the target population activity, the method further comprises: inhibiting, by the inhibiter, the processing unit input based on a difference between the measured population activity of the processing unit and the target population activity to manage activity on the artificial neural network (CANOY, [0066] A typical neural monitor reacts to specified activity. For example, a neural monitor may cut the power to a CPU when the system temperature is above a specified value. One aspect of the present disclosure is directed to a neural monitor that detects instability or imbalance conditions in one or more neural elements and/or processes based on neural activity. That is, the neural monitor may monitor activity patterns of a neural network to determine whether the activity is excepted (e.g., within a range of baseline activity); [0069] a reset block 510 (as inhibiter) may be coupled to the neural processing system 502. In one configuration, the reset block 510 may be a component of the neural model execution engine 504 or the neural monitor 512. In another configuration, one or more of the activity monitor 506, activity regulator 508, and/or reset block 510 are components of another neural network; [0070 trigger the reset block 510 to reset the neural model execution engine 504;; [0029] If enough excitatory signals are received within a certain time period to depolarize the membrane potential above a threshold, an action potential occurs in the postsynaptic neuron. In contrast, inhibitory signals generally hyperpolarize (i.e., lower) the membrane potential Inhibitory signals, if strong enough, can counteract the sum of excitatory signals and prevent the membrane potential from reaching a threshold. In addition to counteracting synaptic excitation, synaptic inhibition can exert powerful control over spontaneously active neurons. A spontaneously active neuron refers to a neuron that spikes without further input, for example due to its dynamics or a feedback. By suppressing the spontaneous generation of action potentials in these neurons, synaptic inhibition can shape the pattern of firing in a neuron, which is generally referred to as sculpturing. The various synapses 104 may act as any combination of excitatory or inhibitory synapses, depending on the behavior desired).
CANOY fails to specifically teach when managing activity, it is managing a processing load on an artificial neural network.
However, PARK teaches managing a processing load on an artificial neural network (PARK, Fig. 5, 508 workload; [0038] The processing load table 508 relates each neural network unit (e.g., neural network layer) with the processing load level resulting from execution of that neural network unit on each of the SoC processors. The term “processing load level” refers to a measurement of the workload expended by the processor to execute the neural network unit by itself, i.e., without concurrently executing any other software. Processing time or the amount of time that the processor takes to execute the neural network unit is an example of a processing load measurement. Percent utilization or the percentage of the processor's maximum processing capability that is utilized to execute the neural network unit by itself is another example of a processing load measurement. To compile the processing load table 508, a neural network unit may be executed on each SoC processor, and the resulting processing load level of that processor may be measured and stored. Such a process of executing a neural network unit, measuring the processing load level, and storing it in the table 508 may be repeated for each processor until the neural network unit has been executed on each processor. The stored processing load level for a particular neural network unit executing on a particular SoC processor thus represents an estimate of the processing load level that would result if that particular neural network unit were later executed on that particular processor. The process may be repeated for each neural network unit. In the illustrated embodiment, in which each neural network unit is a layer of a neural network, the resulting table 508 represents the measured processing load or workload of each layer; [0039] re-allocation in an SoC having two or more heterogeneous processors. The method 600 may be performed, for example, under the control of the above-described workload allocation processor 210 (FIG. 2) or other SoC components that may relate to allocation of tasks or workloads among processors.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of CANOY with PARK because PARK’s teaching of managing the processing load of the artificial neural network for processing reallocation would have provided CANOY’s system with the advantage and capability to allow the system to minimize adverse thermal effects as well as adverse effects upon performance in order to improving the system efficiency (see PARK, [0003]).
CANOY and PARK fail to specifically teach receiving, by the second control module, a system input comprising data to be processed.
However, Wang teaches receiving, by the second control module, a system input comprising data to be processed (Wang, Fig, 2B, 212 input module (as second control module) receives the high resolution input image and scaling down into 4 sub-images 204; claim 1, receiving, by a computer, an input face image which is primarily occupied by a human face; determining, using the computer, if a size of the input face image is greater than a maximum input image size supported by the small-scale CNN module according to the maximum input size constraint; and if so, determining if the size of the input face image meets a predetermined input image size constraint, wherein the predetermined input image size constraint is a given image size among a plurality of image sizes which satisfy a condition for partitioning an input image into multiple sub-images of a second size, and wherein the second size is smaller than the maximum input image size).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of CANOY and PARK with Wang because Wang’s teaching of partitioning the image into four different sub-images based on the capability of neural network node would have provided CANOY and PARK’s system with the advantage and capability to allow the system to manage high-complexity tasks such as processing high-resolution input images without requiring large-scale, high-complexity, expensive hardware modules, thereby improving trade-off between performance and cost (see Wang, Col 12, lines 15-19).
As per claim 2, CANOY, PARK and Wang teach the invention according to claim 1 above. Wang further teaches wherein the inhibiting is gradual so that the larger the difference between the measured population activity of the processing unit and the target activity, the more the system input or the gain of the system input is scaled (Wang, Col 13, lines 41-64, FIG. 2B shows a block diagram of a sub-image-based CNN system 210. In the disclosed CNN system 210, a resolution-limited small-scale CNN module, such as CNN module 100 described in conjunction with FIGS. 1A and 1B or the hardware CNN module inside Hi3519 SoC can be used as a building block of subimage-based CNN system 210. As mentioned above, such a small-scale CNN module has a limitation on the maximum input image size, e.g., up to 1280 pixels. To be able to use this small-scale CNN module on a high-resolution input image 202 (e.g., an image having >1280 pixels), the CNN system 210 includes an input module 212 which is configured to partition the high-resolution input image 202 into a set of smaller subimages 204, wherein each of the subimages 204 has a size which is smaller than or equal to the maximum input image size allowed/supported by the small-scale CNN module used as a building block of CNN system 210. In some embodiments, input module 212 is configured to partition the high-resolution input image 202 by including properly designed overlaps between the adjacent subimages 204, as shown in FIG. 2B. Note that the set of four subimages 204 in two rows and two columns with the illustrated gaps and overlaps are shown in FIG. 2B for the convenience of understanding the concept and not meant for representing an actual partition [Examiner noted: the larger difference between the measure population activity level (i.e., CNN module has a limitation on the maximum input image size, e.g., up to 1280 pixels) and target activity (i.e., received high high-resolution input, if it is very large, the more of system input is scaled)]).
As per claim 3, CANOY, PARK and Wang teach the invention according to claim 1 above. CANOY further teaches wherein the target population activity changes over time (CANOY, [0029] Biological synapses may be classified as either electrical or chemical. While electrical synapses are used primarily to send excitatory signals, chemical synapses can mediate either excitatory or inhibitory (hyperpolarizing) actions in postsynaptic neurons and can also serve to amplify neuronal signals. Excitatory signals depolarize the membrane potential (i.e., increase the membrane potential with respect to the resting potential). If enough excitatory signals are received within a certain time period to depolarize the membrane potential above a threshold, an action potential occurs in the postsynaptic neuron. In contrast, inhibitory signals generally hyperpolarize (i.e., lower) the membrane potential Inhibitory signals, if strong enough, can counteract the sum of excitatory signals and prevent the membrane potential from reaching a threshold. In addition to counteracting synaptic excitation, synaptic inhibition can exert powerful control over spontaneously active neurons. A spontaneously active neuron refers to a neuron that spikes without further input, for example due to its dynamics or a feedback. By suppressing the spontaneous generation of action potentials in these neurons, synaptic inhibition can shape the pattern of firing in a neuron, which is generally referred to as sculpturing. The various synapses 104 may act as any combination of excitatory or inhibitory synapses, depending on the behavior desired).
As per claim 4, CANOY, PARK and Wang teach the invention according to claim 1 above. CANOY further teaches wherein the input comprises an input, and the method further comprises: checking if the population activity of the processing unit is above a second threshold for a first amount of time steps; and responsive to the checking determining the population activity of the processing unit is above the second threshold for the first amount of time steps, resetting the processing unit and restarting the input (CANOY, [0058] the model may be defined to spike when the voltage v reaches a value v.sub.s. Subsequently, the state may be reset at a reset event (which may be one and the same as the spike event); [0062] If a spike is defined as occurring at the time the voltage state v reaches v.sub.s, then the closed-form solution for the amount of time, or relative delay, until a spike occurs as measured from the time that the voltage is at a given state v is; [0072] the activity regulator 508 reconfigures the neural model execution engine 504 to mitigate the exception condition. That is, the activity regulator 508 may change the connectivity of the neurons in the neural model execution engine 504. Alternatively, or in addition, the activity regulator 508 may change the number of active neurons and/or change a probabilistic neuron. In another configuration, the activity regulator 508 disables blocks of neurons of the neural model execution engine 504 to mitigate the exception condition. In yet another configuration, the activity regulator 508 applies a correction factor to the neural model execution engine 504 to mitigate the exception condition. In still another aspect, the activity regulator 508 drops neuron spikes. In still a further aspect, the activity regulator 508 reads out network parameters, values, connectivity, and/or history of last time prior to the exception event. In still yet another aspect of the present disclosure, the activity regulator 508 may adjust the gains of neural modulators (e.g., global data) that affect the execution of a neural model. Alternatively, or in addition to, the activity regulator 508 may also adjust the gains to affect the rate of change of system parameters, such as spike generation or internal neuron state; [0073] Additionally, the activity monitor 506 and the activity regulator 508 may control the neural model execution engine 504 to delay a reset. That is, the reset of the neural model execution engine 504 may be undesirable. Therefore, the activity monitor 506 and the activity regulator 508 may work together to reconfigure the neural model execution engine 504 to delay a reset of the neural model execution engine 504 (as checking if the population activity of the processing unit is above a second threshold for a first amount of time steps (i.e., the delay time before reset); and responsive to the checking determining the population activity of the processing unit is above the second threshold for the first amount of time steps (after delay time), resetting the processing unit and restarting the input)). In addition, Wang teaches input sequence (Wang, Fig. 2B; Col 14, lines 35-49, process the set of subimages 204 generated by input module 212, single CNN1 module 214 is used multiple times by sequentially processing the set of subimages 204, one subimage at a time. That is, each instance of CNN1 block 214 within the first processing stage 220 of CNN system 210 represents one of the multiple applications of the same CNN1 module 214 on one of the set of subimages 204 at a different processing time. However, because the processing speed of each subimage 204 by CNN1 module 214 can be very fast, the overall processing time for processing the set of subimages 204 also can be quite fast. The outputs of multiple applications of CNN1 module 214 contain an array of feature maps 206 corresponding to the set of subimages 204 after multiple layers of convolution, ReLU, and pooling operations).
As per claim 6, CANOY, PARK and Wang teach the invention according to claim 1 above. CANOY further teaches wherein the step of receiving comprises receiving, by the adjustment module, the system input (CANOY, Fig. 5 512 as adjustment module; [0069] FIG. 5 illustrates a diagram 500 of a neural processing system 502 that includes a neural monitor 512 according to an aspect of the present disclosure. As shown in FIG. 5, the neural monitor 512 includes a neural model execution engine 504, (as to receive the input for processing) an activity monitor 506, and an activity regulator 508. Additionally, a reset block 510 may be coupled to the neural processing system 502. In one configuration, the reset block 510 may be a component of the neural model execution engine 504 or the neural monitor 512. In another configuration, one or more of the activity monitor 506, activity regulator 508, and/or reset block 510 are components of another neural network).
In addition, Wang teaches providing the processing unit output to an adjustment module; adjusting, by the adjustment module, the system input based on the processing unit output (Wang, Fig. 2B, 222 as adjustment module, 206 as processing unit output to the 222; and using 222 to adjusting the system input; Col 15, line 58 – Col 16, line 19, FIG. 2B shows that the merged feature maps 208 generated by merging module 222 are fed into the second processing stage 224 of CNN system 210 for further processing. More specifically, the second processing stage 224 of CNN system 210 includes at least one CNN2 module 216, which further includes a set of FC layers and ReLU layers as described above. As mentioned above, CNN2 module 216 in CNN system 210 can be implemented by a dedicated hardware submodule CNN2 described in conjunction with FIGS. 1A and 1B. In these embodiments, CNN2 module 216 within CNN system 210 can include only FC layers and ReLU layers. In some embodiments, CNN2 module 216 can be implemented by taking an entire hardware CNN module 100 described in FIGS. 1A and 1B which includes both CNN1 and CNN2 submodules. In these embodiments, implementing CNN2 module 216 in CNN system 210 further includes bypassing the CONV-ReLU-pooling layers, i.e., bypassing the submodule CNN1 within CNN module 100. In some systems such as Hi3519, it may be difficult to bypass the CONV-ReLU-pooling layers to use the FC layers and ReLU layers directly. In these cases, CNN2 module 216, i.e., the FC layers and ReLU layers can be implemented by software. Because most of the computational complexity of CNN system 210 is in the CONV layers, implementing the FC and ReLU layers in software typically has minor effect on the overall speed of the system. Furthermore, systems such as Hi3519 also provide additional tools to optimize the speed of such a software implementation).
As per claim 9, CANOY, PARK and Wang teach the invention according to claim 1 above. CANOY further teaches repeating the steps of measuring, providing, receiving, scaling, utilizing, checking, inhibiting and optionally one or more of the steps of converting, converting, checking, resetting, restarting, providing, and adjusting until the artificial neural network system is fully trained. wherein the artificial neural network system is fully trained when the population activity is below a population activity threshold (CANOY, [0030] The neuron membrane charged to the threshold value initiating the output spike may be implemented, for example, as a capacitor that integrates an electrical current flowing through it; [0035] The computational network (neural system or neural network) using such processing units may be utilized in a large range of applications, such as image and pattern recognition, machine learning, motor control, and the like; [0036] During the course of training a neural network, synaptic weights (e.g., the weights w.sub.1.sup.(i,i+1), . . . , w.sub.P.sup.(i,i+1) from FIG. 1 and/or the weights 206.sub.1-206.sub.N from FIG. 2) may be initialized with random values and increased or decreased according to a learning rule. Those skilled in the art will appreciate that examples of the learning rule include, but are not limited to the spike-timing-dependent plasticity (STDP) learning rule, the Hebb rule, the Oja rule, the Bienenstock-Copper-Munro (BCM) rule, etc. In certain aspects, the weights may settle or converge to one of two values (i.e., a bimodal distribution of weights). This effect can be utilized to reduce the number of bits for each synaptic weight, increase the speed of reading and writing from/to a memory storing the synaptic weights, and to reduce power and/or processor consumption of the synaptic memory (as including fully trained based on repeating steps of measuring, providing, receiving, scaling, utilizing, checking and inhibiting to ensuring the level is within the baseline range); see [0066] whether the activity is excepted (e.g., within a range of baseline activity). More specifically, the activity patterns may indicate the potential for a system failure and/or component failure. The neural monitor may be referred to as a probabilistic neural monitor; [0070] mitigate the detected condition. Alternatively, or in addition, the neural model execution engine 504 may trigger the reset block 510 to reset the neural model execution engine 504).
As per claim 10, CANOY, PARK and Wang teach the invention according to claim 1 above. CANOY further teaches repeating the steps of measuring, providing, receiving, scaling, utilizing, checking, inhibiting and optionally one or more of the steps of converting, converting, checking, resetting, restarting, providing, and adjusting until the system is fully trained. wherein the system is fully trained when measured population activity is below a population activity threshold (CANOY, [0030] The neuron membrane charged to the threshold value initiating the output spike may be implemented, for example, as a capacitor that integrates an electrical current flowing through it; [0035] The computational network (neural system or neural network) using such processing units may be utilized in a large range of applications, such as image and pattern recognition, machine learning, motor control, and the like; [0036] During the course of training a neural network, synaptic weights (e.g., the weights w.sub.1.sup.(i,i+1), . . . , w.sub.P.sup.(i,i+1) from FIG. 1 and/or the weights 206.sub.1-206.sub.N from FIG. 2) may be initialized with random values and increased or decreased according to a learning rule. Those skilled in the art will appreciate that examples of the learning rule include, but are not limited to the spike-timing-dependent plasticity (STDP) learning rule, the Hebb rule, the Oja rule, the Bienenstock-Copper-Munro (BCM) rule, etc. In certain aspects, the weights may settle or converge to one of two values (i.e., a bimodal distribution of weights). This effect can be utilized to reduce the number of bits for each synaptic weight, increase the speed of reading and writing from/to a memory storing the synaptic weights, and to reduce power and/or processor consumption of the synaptic memory (as including fully trained based on repeating steps of measuring, providing, receiving, scaling, utilizing, checking and inhibiting to ensuring the level is within the baseline range); see [0066] whether the activity is excepted (e.g., within a range of baseline activity). More specifically, the activity patterns may indicate the potential for a system failure and/or component failure. The neural monitor may be referred to as a probabilistic neural monitor; [0070] mitigate the detected condition. Alternatively, or in addition, the neural model execution engine 504 may trigger the reset block 510 to reset the neural model execution engine 504).
As per claim 12, it is an artificial neural network claim of claim 1 above (i.e., all the limitation are recited in the claim 1 above). Therefore, it is rejected for the same reason as claim 1 above.
As per claim 13, CANOY, PARK and Wang teach the invention according to claim 12 above. CANOY further teaches wherein the inhibiter is configured to inhibit the processing unit input gradually (CANOY, [0073] the activity monitor 506 and the activity regulator 508 may control the neural model execution engine 504 to delay a reset. That is, the reset of the neural model execution engine 504 may be undesirable. Therefore, the activity monitor 506 and the activity regulator 508 may work together to reconfigure the neural model execution engine 504 to delay a reset of the neural model execution engine 504; also see [0072] the activity regulator 508 controls (e.g., corrects) the execution of the neural model execution engine 504 to mitigate the exception condition. In one configuration, the activity regulator 508 reconfigures the neural model execution engine 504 to mitigate the exception condition. That is, the activity regulator 508 may change the connectivity of the neurons in the neural model execution engine 504. Alternatively, or in addition, the activity regulator 508 may change the number of active neurons and/or change a probabilistic neuron. In another configuration, the activity regulator 508 disables blocks of neurons of the neural model execution engine 504 to mitigate the exception condition. In yet another configuration, the activity regulator 508 applies a correction factor to the neural model execution engine 504 to mitigate the exception condition. In still another aspect, the activity regulator 508 drops neuron spikes. In still a further aspect, the activity regulator 508 reads out network parameters, values, connectivity, and/or history of last time prior to the exception event. In still yet another aspect of the present disclosure, the activity regulator 508 may adjust the gains of neural modulators (e.g., global data) that affect the execution of a neural model. Alternatively, or in addition to, the activity regulator 508 may also adjust the gains to affect the rate of change of system parameters, such as spike generation or internal neuron state; [0028 scale those signals according to adjustable synaptic weights).
As per claim 15, it is a first control module claim of claim 1 above. Therefore, it is rejected for the same reason as claim 1 above (i.e., all the limitations of the claim 15 are recited in the claim 1).
As per claim 16, CANOY, PARK and Wang teach the invention according to claim 1 above. CANOY further teaches wherein the artificial neural network system performs learning when needed even when the artificial neural network is in an operating mode (CANOY, [0030] The neural system 100 may be emulated by a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, a software module executed by a processor, or any combination thereof. The neural system 100 may be utilized in a large range of applications, such as image and pattern recognition, machine learning, motor control, and alike. Each neuron in the neural system 100 may be implemented as a neuron circuit. The neuron membrane charged to the threshold value initiating the output spike may be implemented, for example, as a capacitor that integrates an electrical current flowing through it).
As per claim 18, CANOY, PARK and Wang teach the invention according to claim 1 above. PARK further teaches wherein measuring a population activity of a group of nodes comprises measuring the total activity level of the group of nodes (PARK, [0036] each neural network unit (e.g., neural network layer) (as include group of node); [0038] The term “processing load level” refers to a measurement of the workload expended by the processor to execute the neural network unit by itself, i.e., without concurrently executing any other software. Processing time or the amount of time that the processor takes to execute the neural network unit is an example of a processing load measurement. Percent utilization or the percentage of the processor's maximum processing capability that is utilized to execute the neural network unit by itself is another example of a processing load measurement. To compile the processing load table 508, a neural network unit may be executed on each SoC processor, and the resulting processing load level of that processor may be measured and stored. Such a process of executing a neural network unit, measuring the processing load level, and storing it in the table 508 may be repeated for each processor until the neural network unit has been executed on each processor. The stored processing load level for a particular neural network unit executing on a particular SoC processor thus represents an estimate of the processing load level that would result if that particular neural network unit were later executed on that particular processor. The process may be repeated for each neural network unit. In the illustrated embodiment, in which each neural network unit is a layer of a neural network, the resulting table 508 represents the measured processing load or workload of each layer executing on each SoC processor, such as the NPU 204-4, DSP 204-3, GPU 204-2 and CPU 204-1 described above with regard to FIG. 2. It may be appreciated that the foregoing tables 506 and 508 are intended only as examples, and in other examples the metadata may comprise other types of information, organized in other ways, etc).
As per claim 21, CANOY, PARK and Wang teach the invention according to claim 1 above. PARK further teaches wherein managing the processing load on the artificial neural network prevents underloading and/or overloading of the processing unit (PARK, [0043] a target processor may be identified, based on results of the comparisons (block 604) and on the metadata associated with the identified or candidate neural network unit. For example, a processor that is not associated with a high temperature measurement or that can accommodate execution of the candidate neural network unit without becoming overloaded may be a good target).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over CANOY, PARK and Wang, as applied to claim 1 above, and further in view of Gyorffy (US Pub. 2012/0159267 A1).
As per claim 5, CANOY, PARK and Wang teach the invention according to claim 1 above. CANOY further teaches wherein the input comprises an input, and the method further comprises: checking if the population activity of the processing unit is above a second threshold for a first amount of time steps; and responsive to the checking determining the population activity of the processing unit is above the second threshold for the first amount of time steps, resetting the processing unit and restarting the input (CANOY, [0058] the model may be defined to spike when the voltage v reaches a value v.sub.s. Subsequently, the state may be reset at a reset event (which may be one and the same as the spike event); [0062] If a spike is defined as occurring at the time the voltage state v reaches v.sub.s, then the closed-form solution for the amount of time, or relative delay, until a spike occurs as measured from the time that the voltage is at a given state v is; [0072] the activity regulator 508 reconfigures the neural model execution engine 504 to mitigate the exception condition. That is, the activity regulator 508 may change the connectivity of the neurons in the neural model execution engine 504. Alternatively, or in addition, the activity regulator 508 may change the number of active neurons and/or change a probabilistic neuron. In another configuration, the activity regulator 508 disables blocks of neurons of the neural model execution engine 504 to mitigate the exception condition. In yet another configuration, the activity regulator 508 applies a correction factor to the neural model execution engine 504 to mitigate the exception condition. In still another aspect, the activity regulator 508 drops neuron spikes. In still a further aspect, the activity regulator 508 reads out network parameters, values, connectivity, and/or history of last time prior to the exception event. In still yet another aspect of the present disclosure, the activity regulator 508 may adjust the gains of neural modulators (e.g., global data) that affect the execution of a neural model. Alternatively, or in addition to, the activity regulator 508 may also adjust the gains to affect the rate of change of system parameters, such as spike generation or internal neuron state; [0073] Additionally, the activity monitor 506 and the activity regulator 508 may control the neural model execution engine 504 to delay a reset. That is, the reset of the neural model execution engine 504 may be undesirable. Therefore, the activity monitor 506 and the activity regulator 508 may work together to reconfigure the neural model execution engine 504 to delay a reset of the neural model execution engine 504 (as checking if the population activity of the processing unit is above a second threshold for a first amount of time steps (i.e., the delay time before reset); and responsive to the checking determining the population activity of the processing unit is above the second threshold for the first amount of time steps (after delay time), resetting the processing unit and restarting the input)). In addition, Wang teaches input sequence (Wang, Fig. 2B; Col 14, lines 35-49, process the set of subimages 204 generated by input module 212, single CNN1 module 214 is used multiple times by sequentially processing the set of subimages 204, one subimage at a time. That is, each instance of CNN1 block 214 within the first processing stage 220 of CNN system 210 represents one of the multiple applications of the same CNN1 module 214 on one of the set of subimages 204 at a different processing time. However, because the processing speed of each subimage 204 by CNN1 module 214 can be very fast, the overall processing time for processing the set of subimages 204 also can be quite fast. The outputs of multiple applications of CNN1 module 214 contain an array of feature maps 206 corresponding to the set of subimages 204 after multiple layers of convolution, ReLU, and pooling operations).
CANOY, PARK and Wang fail to specifically teach wherein the second threshold changes over time.
However, Gyorffy teaches wherein the second threshold changes over time (Gyorffy, [0063] Step 814: If, at any point during the operation, the client processing time as tracked in step 812 exceeds a client processing time threshold dynamically determined by the thresholds manager 654, control proceeds to step 816; otherwise, control proceeds to step 818. Since some operations may require more client processing time than other operations, the client processing time threshold utilized in this step may be dynamically determined based on a type of the operation. Additionally, the client log 656 may save a history of client processing times, and the operation time threshold may be dynamically determined based upon an average or other function of a plurality of recent values of the same type).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of CANOY, PARK and Wang with Gyorffy because Gyorffy’s teaching of the threshold changes overtime (i.e., determined dynamically) would have provided CANOY, PARK and Wang’s system with the advantage and capability to allow the system to adjusting the neural network dynamically based on the dynamically changed threshold which improving the system performance and efficiency.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over CANOY, PARK and Wang, as applied to claim 1 above, and further in view of Han et al. (US Pub. 2019/0393918 A1).
As per claim 7, CANOY, PARK and Wang teach the invention according to claim 1 above. Wang further teaches wherein the system input is time-continuous data generated by one or more sensors, wherein each sensor of the one or more sensors comprises a sensor selected from the group (Wang, Col 12, lines 4-23, The outputs from the first stage based on the set of subimages are subsequently merged. In some embodiments, the subimage-based CNN system includes provisions to the sizes of the input images and subimages to ensure that the merged result to be substantially or exactly identical to the output of a large-scale high-complexity CNN module that processes the entire high-resolution input image without partition. Next, the merged result is processed by the second stage of the subimage-based CNN system, which can also be implemented with one or more small-scale hardware CNN modules or be implemented with software. In this manner, the disclosed CNN system manages high-complexity tasks such as processing high-resolution input images without requiring large-scale, high-complexity, expensive hardware modules, thereby improving trade-off between performance and cost. Hence, this subimage-based CNN system can be highly applicable to resource-limited embedded systems, such as various surveillance cameras, machine vision cameras, drones, robots, self-driving cars, and mobile phones).
CANOY, PARK and Wang fail to specifically teach the group consisting of camera; a touch sensor; a sensor associated with a frequency band of an audio signal; a sensor related to a speaker; and a microphone.
However, Han teaches the group consisting of camera; a touch sensor; a sensor associated with a frequency band of an audio signal; a sensor related to a speaker; and a microphone (Han, [0112] one or more camera modules (e.g., cameras) mounted within housing; [0098] touch sensor circuitry (e.g., touch sensor electrodes) for display 1; [0061] device orientation information from an orientation sensor, device motion data from…radio-frequency range and angle of arrival data, microphone data from one or more microphones or other audio sensors, information on desired frequency bands to use for communications).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of CANOY, PARK and Wang with Han because Han’s teaching of the sensor data obtained from group the sensors would have provided CANOY, PARK and Wang’s system with the advantage and capability to allow the system to easily identifying and analyzing different information obtained from the different types of sensors in order to improving the system performance and efficiency.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over CANOY, PARK and Wang, as applied to claim 1 above, and further in view of Kimijima et al. (US Pub. 2007/0110258 A1).
As per claim 8, CANOY, PARK and Wang teach the invention according to claim 1 above. CANOY further teaches wherein the first control signal is further based on the first gain A and optionally the second gain B (CANOY, [0072] the activity regulator 508 controls (e.g., corrects) the execution of the neural model execution engine 504 to mitigate the exception condition. In one configuration, the activity regulator 508 reconfigures the neural model execution engine 504 to mitigate the exception condition. That is, the activity regulator 508 may change the connectivity of the neurons in the neural model execution engine 504. Alternatively, or in addition, the activity regulator 508 may change the number of active neurons and/or change a probabilistic neuron. In another configuration, the activity regulator 508 disables blocks of neurons of the neural model execution engine 504 to mitigate the exception condition. In yet another configuration, the activity regulator 508 applies a correction factor to the neural model execution engine 504 to mitigate the exception condition. In still another aspect, the activity regulator 508 drops neuron spikes. In still a further aspect, the activity regulator 508 reads out network parameters, values, connectivity, and/or history of last time prior to the exception event. In still yet another aspect of the present disclosure, the activity regulator 508 may adjust the gains of neural modulators (e.g., global data) that affect the execution of a neural model. Alternatively, or in addition to, the activity regulator 508 may also adjust the gains to affect the rate of change of system parameters, such as spike generation or internal neuron state).
CANOY, PARK and Wang fail to specifically teach converting, by a first conversion module, the system input to a first gain A, the first gain A being positive; and optionally, converting, by a second conversion module, the processing unit output to a second gain B the second gain B being negative.
However, Kimijima teaches converting, by a first conversion module, the system input to a first gain A, the first gain A being positive; and optionally, converting, by a second conversion module, the processing unit output to a second gain B the second gain B being negative (Kimijima, Fig. 4, gain calculator; [0191] each operation information corresponding to operation by each of the knob operators 6-1 to 6-5 is input to the system controller 5 and converted into a gain designating signal for each individual range. As shown in FIG. 12 below as well, such a gain designating signal for each individual range is supplied to each of the band-specific gain calculating circuits 12-1 to 12-n within an audio signal processing section 43).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of CANOY, PARK and Wang with Kimijima because Kimijima’s teaching of gain converting mechanism would have provided CANOY, PARK and Wang’s system with the advantage and capability to allow the system to easily identifying the gain for the system input in order to improving the system performance and efficiency.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over CANOY, PARK and Wang, as applied to claim 12 above, and further in view of LI et al. (US Pub. 2020/0012531 A1).
As per claim 14, CANOY, PARK and Wang teach the invention according to claim 12 above. CANOY further teaches wherein one or more of the processing unit, the first control module and the second control module comprises a population of nodes and a learning function and the system input, the processing unit, the first control module and the second control module (CANOY, Fig. 5, 504, 512, 506, 508; Fig. 1, including nodes; [0030] The neural system 100 may be emulated by a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, a software module executed by a processor, or any combination thereof. The neural system 100 may be utilized in a large range of applications, such as image and pattern recognition, machine learning, motor control, and alike. Each neuron in the neural system 100 may be implemented as a neuron circuit. The neuron membrane charged to the threshold value initiating the output spike may be implemented, for example, as a capacitor that integrates an electrical current flowing through it).
CANOY, PARK and Wang fail to specifically teach wherein the system input, the processing unit, the first control module and the second control module are multidimensional and implemented as arrays or matrices.
However, LI teaches wherein the system input, the processing unit, the first control module and the second control module are multidimensional and implemented as arrays or matrices (LI, Fig. 13 A, Fig. 13B; [0208] The convolution kernel can be a multidimensional array of parameters, where the parameters are adapted by the training process for the neural network).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of CANOY, PARK and Wang with LI because LI’s teaching of multidimensional array would have provided CANOY, PARK and Wang’s system with the advantage and capability to allow the system to further increasing the processing speed for machine learning tasks in order to improving the system performance and efficiency (see [0004]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over CANOY, PARK and Wang, as applied to claim 1 above, and further in view of NAGANO et al. (US Pub. 2024/0255384 A1) and Karras et al. (US Pub. 2019/0171936 A1).
As per claim 17, CANOY, PARK and Wang teach the invention according to claim 1 above. CANOY, PARK and Wang fail to specifically teach wherein the artificial neural network system switches from a learning mode to an operating mode once the population activity is below a population activity threshold, wherein in the learning mode the artificial neural network is trained to provide system output having an information content which follows an information content of input to the artificial neural network system as closely as possible.
However, NAGANO teaches wherein the artificial neural network system switches from a learning mode to an operating mode once the population activity is below a population activity threshold (NAGANO, Claim 9, wherein the operation mode switching unit is configured to switch the operation mode from the learning mode to the monitoring mode when the deviation index value is equal to or less than the diagnostic threshold value; [0100] In the configuration according to (2), during the operation of the plant monitoring device in the monitoring mode, the operation mode of the plant monitoring device is switched to the learning mode when it is determined that the deviation index value is greater than the diagnostic threshold value due to a factor (for example, a change in the operating state of the plant) other than the abnormality of the plant or when it is determined that the operation of the plant can be continued even though there is an abnormality in the plant).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of CANOY, PARK and Wang with NAGANO because NAGANO’s teaching of switching the operation mode from the learning mode to the monitoring mode based on the threshold would have provided CANOY, PARK and Wang’s system with the advantage and capability to allow the system to easily detecting the abnormality of the activity order to improving the system reliability and efficiency (see NAGANO, [0100]).
CANOY, PARK, Wang and NAGANO fail to specifically teach wherein in the learning mode the artificial neural network is trained to provide system output having an information content which follows an information content of input to the artificial neural network system as closely as possible.
However, Karras teaches wherein in the learning mode the artificial neural network is trained to provide system output having an information content which follows an information content of input to the artificial neural network system as closely as possible (Karras, [0034] In the context of the following description, the neural network 110 operates in a supervised setting using a training dataset including training input data and training output data (ground truth) pairs. Depending on the task, the input and/or output may be an image, class label, per-pixel class label, per-region object class, object bounding boxes, confidence value, audio data, video data, or the like. The neural network 110 is trained so that the network output data produced by the neural network 110 matches the training output data as closely as possible when the training input data paired with the training output data is processed by the neural network 110).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of CANOY, PARK, Wang and NAGANO with Karras because Karras’s teaching of the network output data produced by the neural network matches the training output data as closely as possible when the training input data paired with the training output data is processed by the neural network would have provided CANOY, PARK, Wang and NAGANO’s system with the advantage and capability to allow the system to ensuring the maximum accuracy of the training results in order to improving the system performance and efficiency.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over CANOY, PARK and Wang, as applied to claim 1 above, and further in view of Lopes (US Pub. 2009/0318161 A1).
As per claim 19, CANOY, PARK and Wang teach the invention according to claim 1 above. CANOY, PARK and Wang fail to specifically teach wherein measuring a population activity of a group of nodes comprises measuring an average or mean of the activity levels of the group of nodes.
However, Lopes teaches wherein measuring a population activity of a group of nodes comprises measuring an average or mean of the activity levels of the group of nodes (Lopes, [0057] the selection of the subset of base stations 101-103 is based on a statistical evaluation of the previous operation of the individual base stations 101-107. Specifically, the load characteristic processor 203 monitors the activity of each base station 101-107 and averages this to determine an averaged reselection activity level).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of CANOY, PARK and Wang with Lopes because Lopes’s teaching of monitoring the activity of each base station and averages this to determine an averaged reselection activity level would have provided CANOY, PARK and Wang’s system with the advantage and capability to allow the system to easily identifying the average activity level by each node in order to improving the system performance and efficiency.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over CANOY, PARK and Wang, as applied to claim 1 above, and further in view of Lim (US Pub. 2010/0007778 A1).
As per claim 20, CANOY, PARK and Wang teach the invention according to claim 1 above. CANOY teaches measuring a population activity of a group of nodes (CANOY, Fig. 5, 506 activity monitor; [0066] A typical neural monitor reacts to specified activity. For example, a neural monitor may cut the power to a CPU when the system temperature is above a specified value. One aspect of the present disclosure is directed to a neural monitor that detects instability or imbalance conditions in one or more neural elements and/or processes based on neural activity. That is, the neural monitor may monitor activity patterns of a neural network to determine whether the activity is excepted (e.g., within a range of baseline activity). More specifically, the activity patterns may indicate the potential for a system failure and/or component failure. The neural monitor may be referred to as a probabilistic neural monitor).
CANOY, PARK and Wang fail to specifically teach subsampling the activity values of the group of nodes so as to select the activity value of one or more nodes in the group.
However, Lim teaches subsampling the activity values of the group of nodes so as to select the activity value of one or more nodes in the group (Lim, [0052] Subsampling may include selection of a single value among a plurality of values in a region or may average the plurality of values within the region. Subsampling using averaged values may include analog vertical averaging, in which quantization occurs after averaging, and digital vertical averaging, in which quantization occurs for each value during averaging, as well as after averaging).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of CANOY, PARK and Wang with Lim because Lim’s teaching of subsampling that include selection of a single value among a plurality of values would have provided CANOY, PARK and Wang’s system with the advantage and capability to allow the system to selecting a single activity value among the different monitored activity values in order to improving the system efficiency.
Conclusion
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/ZUJIA XU/Examiner, Art Unit 2195
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