Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-5 are objected for not defining the acronyms e.g. SS/PBCH, MIB, PDCCH, DBTW etc.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the 20claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Si et al. (US 2020/0322807, hereinafter Si) in view of Intel (“Discussion on initial access aspects for extending NR up to 71GHz”, hereinafter Intel).
Regarding claim 1, Si discloses a terminal device (116 of fig. 3) comprising: reception circuitry (325) configured to receive a SS/PBCH block (para 0005; 0085-0086; BS transmits SS/PBCH block), a MIB (para 0130; and 0135; an indication of all the actually transmitted SS/PBCH blocks within the DRS transmission window by the PBCH payload (e.g., MIB), and a PDCCH (para 0058; 0062; 0069; A UE typically monitors multiple candidate locations for respective potential PDCCH transmissions to decode multiple candidate DCI formats in a slot. Monitoring a PDCCH candidates means receiving and decoding the PDCCH candidate according to DCI formats the UE is configured to receive).
Si does not explicitly disclose wherein the MIB includes a first MIB payload bit and a second MIB payload bit; and the first MIB payload bit is used for indication of a candidate SS/PBCH block index corresponding to the SS/PBCH block; and a Q' value is indicated only by the second MIB payload bit; wherein the Q' value is used for quasi co-location assumption among SS/PBCH blocks.
In an analogous art, Intel discloses wherein the MIB includes a first MIB payload bit (page 13; last para; 1 additional bit is required for encoding a candidate SSB index)
and a second MIB payload bit (page 14; para 01; 2 bits or 1 bit Nssb QCL information); and the first MIB payload bit is used for indication of a candidate SS/PBCH block index corresponding to the SS/PBCH block (page 13; last para; 1 additional bit is required for encoding a candidate SSB index); and a Q' value is indicated only by the second MIB payload bit (page 14; para 01; the parameter NssbQCL was introduced to indicate QCL relationship across QCL – to indicate NssbQCL parameter value in PBCH payload , two bits or one bit for indication); wherein the Q' value is used for quasi co-location assumption among SS/PBCH blocks (page 14; para 01; 2 bits or 1 bit Nssb QCL information). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Si’s method/system by having Intel’s disclosure in order reduce latency in a communication system.
Regarding claim 3, Si discloses a terminal device (116 of fig. 3) comprising:
reception circuitry (325) configured to receive a SS/PBCH block (para 0005; 0085-0086; BS transmits SS/PBCH block), a MIB (para 0130; and 0135; an indication of all the actually transmitted SS/PBCH blocks within the DRS transmission window by the PBCH payload (e.g., MIB), and a PDCCH (para 0058; 0062; 0069; A UE typically monitors multiple candidate locations for respective potential PDCCH transmissions to decode multiple candidate DCI formats in a slot. Monitoring a PDCCH candidates means receiving and decoding the PDCCH candidate according to DCI formats the UE is configured to receive); and a Q' value is predefined without indication by the MIB (para 0171-0172; where q is the wrapped-around modulo value (e.g., QCL assumption), i+n*Q is smaller or equal to the maximum number of candidate SS/PBCH blocks within the DRS transmission window. para 0152; SS/PBCH blocks within the slot actually transmitted are predefined)); wherein the Q' value is used for quasi co-location assumption among SS/PBCH blocks (para 0213 -0214; a parameter for quasi-co-location (QCL) assumption Q).
Si does not explicitly disclose wherein the MIB includes a MIB payload bit; and the MIB payload bit is used for indication of a candidate SS/PBCH block index
corresponding to the SS/PBCH block.
In an analogous art, Intel discloses wherein the MIB includes a MIB payload bit (page 13; last para; 1 additional bit is required for encoding a candidate SSB index); and the MIB payload bit is used for indication of a candidate SS/PBCH block index corresponding to the SS/PBCH block (page 13; last para; 1 additional bit is required for encoding a candidate SSB index). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Si’s method/system by having Intel’s disclosure in order reduce latency in a communication system.
Regarding claim 4, Si discloses a base station device (102 of fig. 2) comprising: a transmission circuitry (215) configured to transmit a SS/PBCH block (para 0005; 0085-0086; BS transmits SS/PBCH block), a MIB (para 0130; and 0135; an indication of all the actually transmitted SS/PBCH blocks within the DRS transmission window by the PBCH payload (e.g., MIB) and a PDCCH (para 0058; 0062; 0069; A UE typically monitors multiple candidate locations for respective potential PDCCH transmissions to decode multiple candidate DCI formats in a slot. Monitoring a PDCCH candidates means receiving and decoding the PDCCH candidate according to DCI formats the UE is configured to receive).
Si does not explicitly disclose wherein the MIB includes a first MIB payload bit and a second MIB payload bit; and the first MIB payload bit is used for indication of a candidate SS/PBCH block index corresponding to the SS/PBCH block; and a Q' value is indicated only by the second MIB payload bit; wherein the Q' value is used for quasi co-location assumption among SS/PBCH blocks.
In an analogous art, Intel discloses wherein the MIB includes a first MIB payload bit (page 13; last para; 1 additional bit is required for encoding a candidate SSB index)
and a second MIB payload bit (page 14; para 01; 2 bits or 1 bit Nssb QCL information); and the first MIB payload bit is used for indication of a candidate SS/PBCH block index corresponding to the SS/PBCH block (page 13; last para; 1 additional bit is required for encoding a candidate SSB index); and a Q' value is indicated only by the second MIB payload bit (page 14; para 01; the parameter NssbQCL was introduced to indicate QCL relationship across QCL – to indicate NssbQCL parameter value in PBCH payload , two bits or one bit for indication); wherein the Q' value is used for quasi co-location assumption among SS/PBCH blocks (page 14; para 01; 2 bits or 1 bit Nssb QCL information). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Si’s method/system by having Intel’s disclosure in order reduce latency in a communication system.
Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Si/Intel in view of NEC (“Discussion on initial access aspects supporting NR from 52.6 to 71GHz”, hereinafter NEC).
Regarding claims 2 and 5, Si does not explicitly disclose that the MIB includes a third MIB payload bit, wherein the third MIB payload bit indicates whether a DBTW is enabled or disabled.
In an analogous art, Intel discloses indicating whether a DBTW is enabled or disabled (page 14; line 29; support signaling of enable/disable of DBTW). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Si’s method/system by having Intel’s disclosure in order to improve resource allocation in a communication system.
Si/Intel does not explicitly disclose that that the MIB includes a third MIB payload bit, wherein the third MIB payload bit indicates whether the DBTW is enabled or disabled.
In an analogous art, NEC discloses that that the MIB includes a third MIB payload bit, wherein the third MIB payload bit indicates whether the DBTW is enabled or disabled (page 3; last para; enabling/disabling DBTW is applied, DBTW indication combined with candidate SSB indices and QCL relation indication is necessary at least for the UE in the serving cell). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Si/Intel’s method/system by having NEC’s disclosure in order to reduce interference and improve efficiency of the communication system.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMINA CHOUDHRY whose telephone number is (571)270-7102. The examiner can normally be reached on Monday to Thursday (7:30 a.m. to 5.00p.m.).
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/SAMINA F CHOUDHRY/
Primary Examiner, Art Unit 2462